MC10H680, MC100H680 4−Bit Differential ECL Bus to TTL Bus Transceiver Description The MC10H/100H680 is a dual supply 4−bit differential ECL bus to TTL bus transceiver. It is designed to allow the system designer to no longer be limited in bus speed associated with standard TTL busses. Using a differential ECL Bus will increase the frequency of operation and increase noise immunity. Both the TTL and the ECL ports are capable of driving a bus. The ECL outputs have the ability to drive 25 W, allowing both ends of the bus line to be terminated in the characteristic impedance of 50 W. The TTL outputs are specified to source 15 mA and sink 48 mA, allowing the ability to drive highly capacitive loads. The ECL output levels are VOH approximately equal to −1.0 V and VOL cutoff equal to −2.0 V (VTT). When the ECL ports are disabled both EIOx and EIOxB go to the VOL cutoff level. The ECL input receivers have special circuitry which detects this disabled condition, prevents oscillation, and forces the TTL output to the low state. The noise margin in this disabled state is greater than 600 mV. Multiple ECL VCCO pins are utilized to minimize switching noise. The TTL ports have standard levels. The TTL input receivers have PNP input devices to significantly reduce loading. Multiple TTL power and ground pins are utilized to minimize switching noise. The control pins (EDIR and ECEB) of the 10H version is compatible with MECL 10H™ ECL logic levels. The control pins of the 100H version are compatible with 100K levels. Features http://onsemi.com PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MCxxxH680G AWLYYWW xxx A WL YY WW G • Differential ECL Bus (25 W) I/O Ports • High Drive TTL Bus I/O Ports • Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise • Dual Supply • Direction and Chip Enable Control Pins • Pb−Free Packages are Available* = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 11 1 Publication Order Number: MC10H680/D GT3 VT2 GT4 TIO3 TCEB 25 24 23 22 21 20 ECEB TIO2 MC10H680, MC100H680 Table 1. PIN DESCRIPTIONS Pin 27 17 VCCO4 VT1 28 16 EIO3 GT1 1 15 VCCE TIO0 2 14 EIO2B TDIR 3 13 VCCO3 EDIR 4 8 12 11 9 10 EIO3B Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 EIO2 EIO1B 7 VCCO2 6 EI01 EIO0 5 VEE GT2 EIO0B 26 VCCO1 T101 19 18 Figure 1. Pinout: PLCC−28 (Top View) GT1 TIO0 TDIR EDIR EIO0 VCCO1 EIO0B VEE EIO1 VCCO2 EIO1B EIO2 VCCO3 EIO2B VCCE EIO3 VCCO4 EIO3B ECEB TCEB TIO3 GT4 VT2 GT3 TIO2 TIO1 GT2 VT1 Function TTL Ground 1 TTL I/O Bit 0 TTL Direction Control ECL Direction Control ECL I/O Bit 0 ECL VCC 1 (0 V) − Outputs ECL I/O Bit 0 Bar ECL Supply (−5.2/−4.5 V) ECL I/O Bit 1 ECL VCC 2 (0 V) − Outputs ECL I/O Bit 1 Bar ECL I/O Bit 2 ECL VCC 3 (0 V) − Outputs ECL I/O Bit 2 Bar ECL VCC (0 V) ECL I/O Bit 3 ECL VCC 4 (0 V) − Outputs ECL I/O Bit 3 Bar ECL Chip Enable Bar Control TTL Chip Enable Bar Control TTL I/O Bit 3 TTL Ground 4 TTL Supply 2 (5.0 V) TTL Ground 3 TTL I/O Bit 2 TTL I/O Bit 1 TTL Ground 2 TTL Supply 1 (5.0 V) Table 2. TRUTH TABLE ECEB TCEB EDIR TDIR EIN EINB EOUT EOUTB TIN TOUT H X X X X X LC LC X Z ECL and TTL Outputs Disabled X H X X X X LC LC X Z ECL and TTL Outputs Disabled L L H X H LC NA H ECL to TTL Direction L L H X LC H NA L ECL to TTL Direction L L H X LC LC NA L ECL to TTL Direction (L−L Condition) L L X H H LC NA H ECL to TTL Direction L L X H LC H NA L ECL to TTL Direction L L X H LC LC NA L ECL to TTL Direction (L−L Condition) L L L L NA NA H LC H TTL to ECL Direction L L L L NA NA LC H L TTL to ECL Direction TDIR − Direction Control TTL Levels EDIR − Direction Control ECL Levels TCEB − Chip Enable Bar Control TTL Levels H − HIGH L − LOW LC − ECL Low Cutoff (VTT = −2.0 V) X − Don’t Care Z − High Impedance ECEB − Chip Enable Bar Control ECL Levels TIN − TTL Input TOUT − TTL Output http://onsemi.com 2 COMMENTS EIN − ECL Input EINB − ECL Input Bar EOUT − ECL Output EOUTB − ECL Output Bar MC10H680, MC100H680 Table 3. MAXIMUM RATINGS Symbols Rating Unit Power Supply Voltage Parameter VEE (ECL) −8.0 to 0 Vdc Power Supply Voltage VCCT (TTL) −0.5 to +7.0 Vdc VI (ECL) VI (TTL) 0.0 to VEE −0.5 to +7.0 Vdc Disabled 3−State Output Vout (TTL) 0.0 to VCCT Vdc Output Source Current Continuous Iout (ECL) 100 mAdc Output Source Current Surge Iout (ECL) 200 mAdc Storage Temperature Tstg −65 to 150 °C Operating Temperature Tamb 0.0 to +75 °C Input Voltage Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. DC CHARACTERISTICS, ECL VCCT = + 5.0 V ± 10%, VEE = − 5.2 ± 5% (10H Version); VEE = − 4.2 V to − 5.5 V (100H Version) TA = 0°C Symbol Parameter Condition Min Max TA = 25°C Min Max TA = 75°C Min Max Unit IEE Supply Current/ECL −110 −110 −110 mA IINH Input HIGH Current 255 175 175 mA IINL Input LOW Current VOH VOL Output HIGH Voltage Output LOW Voltage 0.5 −1100 −2.1 25 W to − 2.1 V 0.5 −840 −2.03 −1100 −2.1 0.3 −810 −2.03 −1100 −2.1 mA −735 −2.03 mV V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 5. 10H DC CHARACTERISTICS (CONTROL INPUTS ONLY), ECL VCCT = + 5.0 ± 10%, VEE = − 5.2 ± 5% TA = 05C Parameter Symbol VIH VIL Input HIGH Voltage Input LOW Voltage TA = 255C TA = 755C Min Max Min Max Min Max Unit −1170 −1950 −840 −1480 −1130 −1950 −810 −1480 −1070 −1950 −735 −1450 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 3 MC10H680, MC100H680 Table 6. 100H DC CHARACTERISTICS (CONTROL INPUTS ONLY), ECL VCCT = + 5.0 ± 10%, VEE = − 4.2 V to − 5.5 V TA = 0°C Parameter Symbol VIH VIL Input HIGH Voltage Input LOW Voltage TA = 25°C TA = 75°C Min Max Min Max Min Max Unit −1165 −1810 −880 −1475 −1165 −1810 −880 −1475 −1165 −1810 −880 −1475 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 7. DC CHARACTERISTICS, TTL VCCT = + 5.0 V ± 10%, VEE = − 5.2 ± 5% (10H Version); VEE = − 4.2 V to − 5.5 V (100H Version) TA = 0°C Symbol Parameter Condition Min 2.0 Max TA = 25°C Min Min Unit Standard Input Standard Input VIK Input Clamp VOH Output HIGH Voltage Output HIGH Voltage IOH = − 3.0 mA IOH = −15 mA VOL Output LOW Voltage IOL = 48 mA 0.55 0.55 0.55 V IIH* TTL (Input HIGH) TTL (Input HIGH) Vin = 2.7 V Vin = 7.0 V 20 100 20 100 20 100 mA IIL* TTL (Input LOW) Vin = 0.5 V −0.6 −0.6 −0.6 mA ICCL Supply Current 75 75 75 mA ICCH Supply Current 70 70 70 mA ICCZ Supply Current 70 mA IOS Output Short Circuit Current −225 mA IIN = −18 mA −1.2 2.5 2.0 −1.2 2.5 2.0 70 VOUT = 0 V −100 0.8 −225 2.0 Max VIH VIL 0.8 2.0 Max TA = 75°C −1.2 2.5 2.0 70 −100 0.8 −225 −100 Vdc Vdc V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *TTL Control Inputs only Table 8. DC (I/O CHARACTERISTICS ONLY), TTL TA = 0°C Symbol IIH/IOZH IIL/IOZL Parameter Output Disable Current Condition Min VOUT = 2.7 V VOUT = 0.5 V Max 70 200 TA = 25°C Min Max 70 200 TA = 75°C Min Max Unit 70 200 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 4 MC10H680, MC100H680 Table 9. ECL TO TTL DIRECTION / AC TEST TA = 0°C TA = 25°C TA = 75°C Parameter Waveforms Condition Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay to Output 2, 4 CL = 50 pF 2.7 4.8 2.7 4.8 2.7 4.8 ns tPZH tPZL ECEB to Output Enable Time 2, 5, 6 CL = 50 pF 3.5 3.5 6.5 6.0 3.5 3.5 6.5 6.0 3.7 3.7 6.7 6.4 ns tPHZ tPLZ ECEB to Output Disable Time 2, 5, 6 CL = 50 pF 3.5 3.5 8.6 6.5 3.5 3.5 8.6 6.5 3.7 3.7 8.8 7.3 ns tPZH tPZL TCEB to Output Enable Time 2, 5, 6 CL = 50 pF 5.7 5.4 7.7 6.9 5.7 5.4 7.7 6.9 5.9 5.9 7.9 7.4 ns tPHZ tPLZ TCEB to Output Disable Time 2, 5, 6 CL = 50 pF 4.0 4.0 8.5 5.8 4.1 4.2 8.4 6.0 4.2 4.7 8.3 6.5 ns tr/tf 1.0 to 2.0 Vdc 3 CL = 50 pF 0.4 1.5 0.4 1.5 0.4 1.5 ns Symbol NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 10. TTL TO ECL DIRECTION / AC TEST TA = 0°C TA = 25°C TA = 75°C Parameter Waveforms Condition Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay to Output 1, 4 25 W to − 2.0 V 1.8 4.6 1.8 4.6 2.0 4.9 ns tPLH tPHL ECEB to Output 1, 4 25 W to − 2.0 V 2.9 5.1 3.0 5.2 3.4 5.7 ns tPLH tPHL TCEB to Output 1, 4 25 W to − 2.0 V 3.4 6.3 3.5 6.6 3.8 7.4 ns tr/tf Output Rise/Fall Time 20% −80% 1, 3 25 W to − 2.0 V 1.0 3.4 1.0 3.4 1.0 3.4 ns Symbol NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 5 MC10H680, MC100H680 CONTROL INPUTS EOE TDIR EDIR TOE TCE VCCE VEE VCCO1 ECE GND1 TTL I/O EIO0 TIO0 ECL I/O EIO0 VCCT1 VCCO2 GND2 EIO1 TIO1 EIO1 VCCO3 GND3 EIO2 TIO2 EIO2 VCCT2 VCCO4 GND4 EIO3 TIO3 EIO3 Figure 2. Block Diagram SWITCHING CIRCUIT ECL VEE USE 0.1 mF CAPACITORS FOR DECOUPLING. PULSE GENERATOR 50 W COAX +7 V IN DEVICE UNDER TEST 50 W OUT 50 W COAX CH A CH B DEVICE UNDER TEST 50 pF OSCILLOSCOPE Figure 3. Switching Circuit ECL Figure 4. http://onsemi.com 6 OPEN ALL OTHERS tPZL, tPLZ 50 W COAX USE OSCILLOSCOPE INTERNAL 50 W LOAD FOR TERMINATION. TTL VCC & VCCO R1 500 W R2 500 W MC10H680, MC100H680 WAVEFORMS ECL/TTL ECL/TTL 50%/1.5 V VIN 80%/2.0 V 20%/1.0 V VOUT TRISE TPLH TPHL TPD++ TPD − − 50%/1.5 V TFALL VOUT Figure 5. WAVEFORMS: Rise and Fall Times Figure 6. Propagation Delay − Single Ended TTL TTL VE VE 1.5 V 1.5 V 1.5 V 1.5 V VE VE TPZL TPZH TPLZ 1.5 V VOUT w VOH ≈ 3.5 V 1.5 V VOUT VOL TPHZ 0.3 V 0.3 V Figure 7. 3−State Output Low Enable and Disable Times TTL I/O Figure 8. 3−State Output High Enable and Disable Times ECL I/O ECL I/O 50 W 50 W 50 W VTT TTL I/O 50 W VTT 1 of 4 1 of 4 Figure 9. ECL I/O Link Application Recommended Termination (Directional Control Intentionally Excluded) http://onsemi.com 7 MC10H680, MC100H680 ORDERING INFORMATION Package Shipping † MC10H680FN PLCC−28 37 Units / Rail MC10H680FNG PLCC−28 (Pb−Free) 37 Units / Rail MC10H680FNR2 PLCC−28 500 / Tape & Reel MC10H680FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel MC100H680FN PLCC−28 37 Units / Rail MC100H680FNG PLCC−28 (Pb−Free) 37 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 8 MC10H680, MC100H680 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE E −N− 0.007 (0.180) B Y BRK T L−M M 0.007 (0.180) U M N S T L−M S S N S D Z −M− −L− W 28 D X V 1 A 0.007 (0.180) R 0.007 (0.180) C M M T L−M T L−M S S N S N S 0.007 (0.180) H N S S G J 0.004 (0.100) −T− SEATING T L−M S N T L−M S N S K PLANE F VIEW S G1 M K1 E S T L−M S VIEW D−D Z 0.010 (0.250) 0.010 (0.250) G1 VIEW S S NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10_ 0.410 0.430 0.040 −−− http://onsemi.com 9 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10_ 10.42 10.92 1.02 −−− 0.007 (0.180) M T L−M S N S MC10H680, MC100H680 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). MECL 10H is a trademark of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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