NB3N111K 3.3V Differential 1:10 Fanout Clock Driver with HCSL Outputs Description http://onsemi.com The NB3N111K is a differential 1:10 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N111K is designed with PCI Express HCSL clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 10. Input pins incorporate separate internal 50 W termination resistors allowing additional single ended system interconnect flexibility. Output drive current is set by connecting a 475 W resistor from IREF (Pin 1) to GND per Figure 6. Outputs can also interface to LVDS receivers when terminated per Figure 11. The NB3N111K specifically guarantees low output–to–output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB3N111K’s performance to distribute low skew clocks across the backplane or the motherboard. Features • • • • • • • • • • Typical Input Clock Frequency 100, 133, 166, or 400 MHz 220 ps Typical Rise and Fall Times 800 ps Typical Propagation Delay Dtpd 100 ps Maximum Propagation Delay Variation per Diff Pair 0.1 ps Typical RMS Additive Phase Jitter LVDS Output Levels Optional with Interface Termination Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V Typical HCSL Output Levels (700 mV Peak−to−Peak) LVDS Output Levels with Interface Termination These are Pb−Free Devices Applications • • • • • 1 32 QFN32 MN SUFFIX CASE 488AM MARKING DIAGRAM* 1 NB3N 111K AWLYYWWG A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. Q0 VTCLK Q0 Q1 Q1 CLK CLK Q8 Q8 Q9 VTCLK Clock Distribution PCIe I, II, III Networking High End Computing Routers VCC GND IREF Q9 RREF Figure 1. Simplified Logic Diagram End Products • Servers • FBDIMM Memory Card ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2012 April, 2012 − Rev. 5 1 Publication Order Number: NB3N111K/D VCC Q0 Q0 Q1 Q1 Q2 Q2 VCC NB3N111K 32 31 30 29 28 27 26 25 Exposed Pad (EP) IREF 1 24 VCC VTCLK 2 23 Q3 CLK 3 22 Q3 CLK 4 21 Q4 NB3N111K 7 18 Q5 GND 8 17 VCC VCC 9 10 11 12 13 14 15 16 VCC Q9 Q6 19 Q5 Q6 6 Q7 Q9 Q7 20 Q4 Q8 5 Q8 VTCLK Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 IREF 2, 5 VTCLK, VTCLK − 3 CLK LVPECL, HCSL, LVDS Input Clock and Data (TRUE) Input 4 CLK LVPECL, HCSL, LVDS Input Clock and Data (INVERT) Input 6, 10, 12, 14, 18, 20, 22, 26, 28, 30 Q[9−0] HCSL or LVDS (Note 1) Output Output (INVERT) (Note 1) 7, 11, 13, 15, 19, 21, 23, 27, 29, 31 Q[9−0] HCSL or LVDS (Note 1) Output Output (TRUE) (Note 1) 8 GND − Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 9, 16, 17, 24, 25, 32 VCC − Positive Voltage Supply pin. VCC pins must be externally connected to a power supply to guarantee proper operation. Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat−sinking conduit for proper thermal operation and electrically connected to the circuit board ground (GND). Use the IREF pin to set the output drive. Connect a 475 W RREF resistor from the IREF pin to GND to produce 2.6 mA of IREF current. A current mirror multiplies IREF by a factor of 5.4x to force 14 mA through a 50 W output load. See Figures 6 and 12. Internal 50 W Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to self−oscillation. 1. Outputs can also interface to LVDS receiver when terminated per Figure 11. http://onsemi.com 2 NB3N111K Table 2. ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 2) Flammability Rating >2 kV 200 V QFN32 Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 286 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS (Note 3) Symbol Rating Unit VCC Positive Power Supply Parameter GND = 0 V Condition 1 4.6 V VI Positive Input GND = 0 V GND − 0.3 ≤ VI ≤ VCC V VINPP Differential Input Voltage VCC V IOUT Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range QFN32 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm QFN32 QFN32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 3) QFN32 12 °C/W Tsol Wave Solder 265 °C Pb−Free Condition 2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB3N111K Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = −40°C to +85°C Note 4) Symbol Typ Max Unit GND Supply Current (All Outputs Loaded) 60 90 mA ICC Power Supply Current (All Outputs Loaded) 210 260 mA IIH Input HIGH Current 2.0 150 mA IIL Input LOW Current IGND RTIN Characteristic Min Internal Input Termination Resistor −150 −2.0 45 50 mA 55 W DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED Vth Input Threshold Reference Voltage Range (Note 5) VIH Single*Ended Input HIGH Voltage VIL Single*Ended Input LOW Voltage 350 VCC − 1000 mV VCC mV GND Vth − 150 mV Vth + 150 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8 and 9) VIHD Differential Input HIGH Voltage 425 VCC − 850 mV VILD Differential Input LOW Voltage GND VCC − 1000 mV VID Differential Input Voltage (VIHD * VILD) 150 VCC − 850 mV Input Common Mode Range 350 VCC − 1000 mV VCMR HCSL OUTPUTS (Figure 4) VOH Output HIGH Voltage 600 740 900 mV VOL Output LOW Voltage −150 0 150 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measurements taken with outputs loaded 50 W to GND. Connect a 475 W resistor from IREF (Pin 1) to GND. See Figure 6. 5. Vth is applied to the complementary input when operating in single ended mode per Figure 4. http://onsemi.com 4 NB3N111K Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +85°C (Note 6) Symbol VOUTPP tPLH, tPHL Characteristic Min Output Voltage Amplitude (@ VINPPmin) fin ≤ 400 MHz Propagation Delay (See Figure 3a) CLK/CLK to Qx/Qx DtPLH, DtPHL Propagation Delay Variation Per Each Diff Pair (Note 7) (See Figure 3a) CLK/CLK to Qx/Qx tSKEW Duty Cycle Skew (Note 8) Within −Device Skew Device to Device Skew (Note 9) tJITq VINPP VCROSS DVCROSS tr , tf Dtr, Dtf 550 Typ Max Unit 725 1000 mV 800 1100 ps 100 20 100 150 Additive Integrated Phase Jitter at Fc = 100 MHz (Note 10) 0.1 Input Voltage Swing/Sensitivity (Differential Configuration) Absolute Crossing Magnitude Voltage (See Figure 3b) Qx, Qx Variation in Magnitude of Risetime and Falltime (Single−Ended) (See Figure 3b) Qx, Qx ps ps 0.150 VCC − 0.85 V 250 550 mV 150 mV Variation in Magnitude of VCROSS (See Figure 3b) Absolute Magnitude in Output Risetime and Falltime (from 175 mV to 525 mV) (See Figure 3b) ps 150 220 400 125 ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Measured by forcing VINPP (MIN) from a 50% duty cycle. Measurement taken with all outputs loaded 50 W to GND. Connect a 475 W resistor from IREF (Pin 1) to GND. See Figure 6. 7. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges per Figure 3. 8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+. 9. Skew is measured between outputs under identical transition conditions @ 50 MHz. 10. Phase noise integrated from 12 kHz to 20 MHz. Qx 525 mV 175 mV tr Qx CLK tf Qx VINPP = VIH(CLK) − VIL(CLK) = VIH(CLK) − VIL(CLK) 525 mV CLK tPLH tPHL Qx Q VOUTPP = VOH(Qx) − VOL(Qx) = VOH(Qx) − VOL(Qx) Q tfMAX trMAX 175 mV DtPLH trMIN trMAX − trMIN = Dtr tfMIN tfMAX − tfMIN = Dtf (b) tr, tf and Dtr, Dtf Qx DtPHL VCROSS (a) Propagation Delay and Propagation Delay Variation DVCROSS Qx Figure 3. AC Reference Measurement http://onsemi.com 5 (c) VCROSS and DVCROSS NB3N111K VCC VIHDmax VILDmax VCMRmax CLK IN Vth VCMR VIHDtyp VILDtyp IN CLK VID = VIHD − VILD VIHDmin VCMRmin VILDmin Vth VEE Figure 4. Single−Ended Interconnect Vth Reference Voltage Qx RS1B Figure 5. Vth Diagram Z0 = 50 W Receiver HCSL Driver RS2B IREF Qx Z0 = 50 W CL1C 2 pF RL1D 50 W CL2C 2 pF RL2D 50 W RREFA A. Connect 475 W resistor RREF from IREF pin to GND. B. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. C. CL1, CL2: Receiver Input Simulation (for test only not added to application circuit) Load capacitance only. D. DL1, DL2 Termination and Load Resistors Located at Receiver Inputs. Figure 6. Typical Termination Configuration for Output Driver and Device Evaluation VCC = 3.3 V / 2.5 V VCC = 3.3 V Z0 = 50 W CLK VCC = 3.3 V / 2.5 V / 1.8 V VCC = 3.3 V Z0 = 50 W NB3N111K CLK NB3N111K 50 W* LVPECL Driver 50 W* VTCLK LVDS Driver VTCLK 50 W* Z0 = 50 W CLK VTCLK Z0 = 50 W CLK 50 W* VTCLK = VTCLK VTCLK = VTCLK = VCC − 2.0 V GND VTCLK GND GND GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 7. LVPECL Interface Figure 8. LVDS Interface http://onsemi.com 6 NB3N111K VCC = 3.3 V / 2.5 V / 1.8 V VCC Z0 = 50 W NB3N111K CLK GND HCSL Driver VCC = 3.3 V / 2.5 V / 1.8 V VCC Z0 = 50 W CLK 50 W* 50 W* VTCLK VTCLK LVCMOS/ LVTTL Driver VTCLK 50 W* Z0 = 50 W CLK VTCLK Vth VTCLK = VTCLK = GND GND GND GND *RTIN, Internal Input Termination Resistor Qx VTCLK = OPEN VTCLK = OPEN CLK = Vth Zo = 50 W LVDS Device 100 W Zo = 50 W RL = 150 W IREF RL = 150 W RREF GND Figure 11. HCSL Interface Termination to LVDS 2.6 mA 14 mA IREF RREF 50 W* GND Figure 10. LVCMOS/LVTTL Interface 100 W Qx CLK *RTIN, Internal Input Termination Resistor Figure 9. Standard 50 W Load HCSL Interface NB3N111K HCSL Device NB3N111K Qx 475 W RL1 Qx 50 W RL2 Figure 12. HCSL Simplified Output Structure http://onsemi.com 7 50 W NB3N111K ORDERING INFORMATION Package Shipping† NB3N111KMNG QFN32 (Pb−Free) 74 Units / Rail NB3N111KMNR4G QFN32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB3N111K PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O PIN ONE LOCATION 2X ÉÉ ÉÉ 0.15 C 2X A B D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 32 X 0.08 C C L 32 X 9 D2 SEATING PLANE A1 SIDE VIEW SOLDERING FOOTPRINT* EXPOSED PAD 16 5.30 K 32 X 17 MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 −−− −−− 0.300 0.400 0.500 3.20 8 32 X 0.63 E2 1 24 32 3.20 25 b 0.10 C A B 32 X 5.30 e 0.05 C 32 X 0.28 BOTTOM VIEW 28 X 0.50 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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