NB4N111K D

NB4N111K
3.3V Differential In 1:10
Differential Fanout Clock
Driver with HCSL Level
Output
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Description
The NB4N111K is a differential input clock 1 to 10 HCSL fanout
buffer, optimized for ultra low propagation delay variation. The
NB4N111K is designed with HCSL clock distribution for FBDIMM
applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single−ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors. Outputs can interface with LVDS with proper
termination (See Figure 15).
The NB4N111K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N111K’s performance to distribute low skew
clocks across the backplane or the motherboard.
1
32
1
NB4N
111K
AWLYYWWG
A
WL
YY
WW
G
• Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and
400 MHz
•
•
•
•
Differential Pair
<1 ps RMS Additive Clock jitter
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Differential HCSL Output Level or LVDS with Proper Termination
These are Pb−Free Devices
32
MARKING DIAGRAM*
Features
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each
QFN32
MN SUFFIX
CASE 488AM
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
VTCLK
Q1
Q1
CLK
CLK
Q8
Q8
VTCLK
Q9
VCC
GND
RREF
IREF Q9
Figure 1. Pin Configuration (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 5
1
Publication Order Number:
NB4N111K/D
VCC
Exposed Pad (EP)
25
Q2
26
Q2
27
Q1
28
Q1
29
Q0
30
Q0
31
32
VCC
NB4N111K
IREF
1
24
VCC
VTCLK
2
23
Q3
CLK
3
22
Q3
CLK
4
21
Q4
VTCLK
5
20
Q4
Q9
6
19
Q5
Q9
7
18
Q5
GND
8
17
VCC
9
10
11
12
13
14
15
16
VCC
Q8
Q8
Q7
Q7
Q6
Q6
VCC
NB4N111K
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IREF
Output
2, 5
VTCLK,
VTCLK
−
3
CLK
LVPECL Input
CLOCK Input (TRUE)
4
CLK
LVPECL Input
CLOCK Input (INVERT)
8
GND
−
Supply Ground. GND pin must be externally connected to power supply to
guarantee proper operation.
9, 16, 17, 24, 25, 32
VCC
−
Positive Supply pins. VCC pins must be externally connected to a power supply to
guarantee proper operation.
6, 10, 12, 14, 18, 20,
22, 26, 28, 30
Q[09−0]
HCSL or
LVDS Output
Noninverted Clock Output. (For LVDS levels see Figure 15)
7, 11, 13, 15, 19, 21,
23, 27, 29, 31
Q[09−0]
HCSL or
LVDS Output
Inverted Clock Output. (For LVDS levels see Figure 15)
Exposed Pad
EP
GND
Output current programming pin. Connect to GND. (See Figure 9).
Internal 50 W Termination Resistor connection Pins. In the differential configuration
when the input termination pins are connected to the common termination voltage,
and if no signal is applied then the device may be susceptible to self−oscillation.
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a sufficient heat−sinking conduit for proper thermal
operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
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NB4N111K
Table 2. ATTRIBUTES
Characteristic
Value
Input Default State Resistors
ESD Protection
None
Human Body Model
Moisture Sensitivity (Note 2)
>2 kV
QFN32
Flammability Rating Oxygen Index: 28 to 34
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
622
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS (Note 3)
Parameter
Symbol
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
4.6
V
VI
Positive Input
GND = 0 V
GND − 0.3 v VI v VCC
V
VINPP
Differential Input Voltage
IOUT
Output Current
Continuous
Surge
TA
Operating Temperature Range
QFN32
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN32
QFN32
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 4)
QFN32
Tsol
Wave Solder
|CLK − CLK|
Pb−Free
VCC
V
50
100
mA
mA
−40 to +70
°C
−65 to +150
°C
31
27
°C/W
°C/W
12
°C/W
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4N111K
Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = −40°C to +70°C Note 5)
Symbol
Characteristic
IGND
GND Supply Current (All Outputs Loaded)
ICC
Power Supply Current (All Outputs Loaded)
IIH
Input HIGH Current CLKx, CLKx
IIL
Input LOW Current CLKx, CLKx
Min
Typ
Max
Unit
70
98
120
mA
300
mA
150
mA
2.0
−150
−2.0
mA
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 5 and 7)
Vth
Input Threshold Reference Voltage Range (Note 6)
1050
VCC − 150
mV
VIH
Single−Ended Input HIGH Voltage
Vth + 150
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
Vth − 150
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8)
VIHD
Differential Input HIGH Voltage
1200
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 75
mV
VID
Differential Input Voltage (VIHD − VILD)
75
2400
mV
VCMR
Input Common Mode Range
1163
VCC − 75
HCSL OUTPUTS (Figure 4)
VOH
Output HIGH Voltage
600
740
900
mV
VOL
Output LOW Voltage
−150
0
150
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with VCC. Measurements taken with all outputs loaded 50 W to GND, see Figure 9.
6. Vth is applied to the complementary input when operating in single ended mode.
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NB4N111K
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +70°C (Note 7)
Symbol
Characteristic
Typ
Max
Unit
725
1000
mV
800
1100
ps
Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8)
(See Figure 3)
100
ps
tSKEW
Duty Cycle Skew (Note 9)
Within−Device Skew
Device−to−Device Skew (Note 10)
20
100
150
ps
ps
ps
tJITTER
RMS Random Clock Jitter (Note 11)
1
ps
Vcross
Absolute Crossing Magnitude Voltage
550
mV
DVcross
Variation in Magnitude of Vcross
150
mV
tr, tf
Absolute Magnitude in Output Risetime and Falltime
(From 175 mV to 525 mV)
Qx, Qx
700
ps
Dtr, Dtf
Variation in Magnitude of Risetime and Falltime (Single−Ended)
(See Figure 4)
Qx, Qx
125
ps
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
tPLH,
tPHL
Propagation Delay to (See Figure 3)
DtPLH,
DtPHL
Min
fin = 400 MHz
CLK/CLK to Qx/Qx
550
fin = 400 MHz
250
175
340
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with all outputs loaded 50 W to GND,
see Figure 9. Typical gain is 20 dB.
8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges.
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+.
10. Skew is measured between outputs under identical transition @ 400 MHz.
11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz
CLK
VINPP = VIH(CLK) − VIL(CLK)
= VIH(CLK) − VIL(CLK)
CLK
tPLH
tPHL
Q
VOUTPP = VOH(Q) − VOL(Q)
= VOH(Q) − VOL(Q)
Q
DtPHL
DtPLH
Figure 3. AC Reference Measurement
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5
NB4N111K
525 mV
DVCROSS
VCROSS
175 mV
tr
tf
Figure 4. HCSL Output Parameter Characteristics
CLK
CLK
CLK
CLK
Vth
Vth
Figure 5. Differential Input Driven
Single−Ended (Vth = VREFAC)
VCC
Vthmax
Figure 6. Differential Inputs Driven
Differentially
VCC
VCMmax
VIHmax
VILmax
Vth
Vthmin
GND
VIH
Vth
VIL
VCMR
VIHDmax
VILDmax
VID = VIHD − VILD
VIHDtyp
VILDtyp
VIHmin
VCMmin
VILmin
GND
Figure 7. Vth Diagram
VIHDmin
VILDmin
Figure 8. VCMR Diagram
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NB4N111K
Qx
Z0 = 50 W
RS1B
Receiver
HCSL
Driver
RS2B
Z0 = 50 W
Qx
CL1C
2 pF
IREFA
CL2C
2 pF
RL1
50
RL2
50
A. Connect IREF pin to GND.
B. RS1, RS2: 0 W for Test and
Evaluation. Select to Minimizing Ringing.
C. CL1, CL2: Receiver Input Simulation
Load Capacitance Only.
Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation
CLx for Test Only (Representing Receiver Input Loading); Not Added to Application
VCC = 3.3 V
VCC = 3.3 V
Z0 = 50 W
LVPECL
Driver
VCC = 3.3 V
Z0 = 50 W
NB4N111K
D
50 W*
VTCLK
LVDS
Driver
VTCLK
Z0 = 50 W
50 W*
D
NB4N111K
D
50 W*
VTCLK
VTCLK
Z0 = 50 W
VTCLK = VTCLK = VCC − 2.0 V
GND
VCC = 3.3 V
50 W*
D
VTCLK = VTCLK
GND
GND
GND
*RTIN, Internal Input Termination Resistor
*RTIN, Internal Input Termination Resistor
Figure 10. LVPECL Interface
Figure 11. LVDS Interface
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NB4N111K
VCC
VCC
Z0 = 50 W
VCC
VCC
NB4N111K
D
50 W*
Z0 = 50 W
VTCLK
CML
Driver
LVCMOS/
LVTTL
Driver
VTCLK
Z0 = 50 W
VCC
50 W*
D
VTCLK
VTCLK
50 W*
D
Vth
VTCLK = OPEN
VTCLK = OPEN
D = Vth
VTCLK = VTCLK = VCC
GND
NB4N111K
D
50 W*
GND
GND
*RTIN, Internal Input Termination Resistor
*RTIN, Internal Input Termination Resistor
Figure 12. Standard 50 W Load CML Interface
Figure 13. LVCMOS/LVTTL Interface
VCC
VDR
INTQb
INTQ
Q
Qb
Figure 14. HCSL Output Structure
HCSL
Driver
Qx
Zo = 50 W
100 W
Qx
GND
100 W
Zo = 50 W
RL = 150 W
RL = 150 W
Figure 15. HCSL Interface Termination to LVDS
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8
LVDS
Receive
NB4N111K
ORDERING INFORMATION
Package
Shipping†
NB4N111KMNG
QFN32
(Pb−Free)
79 Units / Rail
NB4N111KMNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NB4N111K
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM−01
ISSUE O
PIN ONE
LOCATION
2X
ÉÉ
ÉÉ
0.15 C
2X
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
SOLDERING FOOTPRINT*
5.30
EXPOSED PAD
16
K
3.20
32 X
17
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
8
32 X
0.63
E2
1
3.20
24
32
25
32 X b
0.10 C A B
5.30
e
32 X
0.05 C
0.28
BOTTOM VIEW
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NB4N111K/D