INTERSIL 5962F9862201V9A

ACS11MS
Data Sheet
Radiation Hardened Triple 3-Input AND
Gate
The Radiation Hardened ACS11MS is a Triple 3-Input AND
Gate. When all three inputs to one of the gates are at a
HIGH level, the corresponding Y output will be HIGH. A LOW
level on any input will cause the output for that gate to be
LOW. All inputs are buffered and the outputs are designed
for balanced propagation delay and transition times.
The ACS11MS is fabricated on a CMOS Silicon on Sapphire
(SOS) process, which provides an immunity to Single Event
Latch-up and the capability of highly reliable performance in
any radiation environment. These devices offer significant
power reduction and faster performance when compared to
ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS11MS are
contained in SMD 5962-98622. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
November 1998
File Number
4543
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD (Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels . . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 12ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MKT. NUMBER
5962F9862201VCC
ACS11DMSR-03
ACS11D/SAMPLE-03
ACS11D/SAMPLE-03
5962F9862201VXC
ACS11KMSR-03
ACS11K/SAMPLE-03
5962F9862201V9A
TEMP. RANGE (oC)
PACKAGE
DESIGNATOR
-55 to 125
14 Ld SBDIP
CDIP2-T14
25
14 Ld SBDIP
CDIP2-T14
-55 to 125
14 Ld Flatpack
CDFP4-F14
ACS11K/SAMPLE-03
25
14 Ld Flatpack
CDFP4-F14
ACS11HMSR-03
25
Die
N/A
Pinouts
ACS11MS
(SBDIP)
TOP VIEW
ACS11MS
(FLATPACK)
TOP VIEW
A1 1
14 VCC
B1 2
13 C1
A2 3
12 Y1
B2 4
11 C3
C2 5
10 B3
Y2 6
9 A3
GND 7
8 Y3
1
A1
1
14
VCC
B1
2
13
C1
A2
3
12
Y1
B2
4
11
C3
C2
5
10
B3
Y2
6
9
A3
GND
7
8
Y3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACS11MS
Die Characteristics
PASSIVATION:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils 1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
SPECIAL INSTRUCTIONS:
Bond VCC First
METALLIZATION: AI
ADDITIONAL INFORMATION:
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
Worst Case Current Density: <2.0 x 105 A/cm2
Transistor Count: 97
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS11MS
B1
(2)
A1
(1)
VCC
(14)
C1
(13)
A2 (3)
(12) Y1
B2 (4)
(11) C3
NC
NC
C2 (5)
(10) B3
(6)
Y2
(7)
GND
(8)
Y3
(9)
A3
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