HCTS244T Data Sheet July 1999 Radiation Hardened Octal Buffer/Line Driver, Three-State Intersil‘s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS244T is a Radiation Hardened NonInverting Octal Buffer/Line Driver, Three-State, with two active-low output enables. Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HCTS244T are contained in SMD 5962-95744. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil‘s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp PART NUMBER • QML Class T, Per MIL-PRF-38535 • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • 3 Micron Radiation Hardened CMOS SOS • Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current Levels Ii ≤ 5mA at VOL, VOH Pinouts HCTS244DTR (SBDIP), CDIP2-T20 TOP VIEW TEMP. RANGE (oC) 5962R9574401TRC HCTS244DTR -55 to 125 5962R9574401TXC HCTS244KTR -55 to 125 4618.1 Features Ordering Information ORDERING NUMBER File Number OE 1 1 A0 1 2 19 2 OE Y3 2 3 18 1 Y0 A1 1 4 17 2 A3 Y2 2 5 16 1 Y1 A2 1 6 15 2 A2 Y1 2 7 14 1 Y2 A3 1 8 13 2 A1 Y0 2 9 12 1 Y3 10 11 2 A0 GND NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. 20 VCC HCTS244KTR (FLATPACK), CDFP4-F20 TOP VIEW 1 20 A0 1 2 19 2 OE Y3 2 3 18 1 Y0 A1 1 4 17 2 A3 Y2 2 5 16 1 Y1 A2 1 6 15 2 A2 Y1 2 7 14 1 Y2 A3 1 8 13 2 A1 Y0 2 9 12 1 Y3 10 11 2 A0 GND 1 VCC OE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation. HCTS244T Functional Diagram 1Y0 18 N P 1Y1 16 N P 1Y2 14 N P 1Y3 12 N 2Y0 9 P P N 2Y1 7 P N 2Y2 5 P N 2Y3 3 P N 19 2OE 1 1OE 2 1A0 4 1A1 6 1A2 8 1A3 11 2A0 13 2A1 15 2A2 TRUTH TABLE INPUTS H L X Z 2 = = = = OUTPUT 1OE, 2OE A Y L L L L H H H X Z High Voltage Level. Low Voltage Level. Immaterial. High Impedance. 17 2A3 HCTS244T Die Characteristics DIE DIMENSIONS: PASSIVATION: (2743µm x 2692µm x 533µm ±51µm) Type: Silox (SiO2) 108 x 106 x 21mils ±2mil Thickness: 13.0kÅ ±2.6kÅ METALLIZATION: WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 Type: Al Si Thickness: 11.0kÅ ±1kÅ TRANSISTOR COUNT: SUBSTRATE POTENTIAL: 264 Unbiased Silicon on Sapphire PROCESS: BACKSIDE FINISH: CMOS SOS Sapphire Metallization Mask Layout HCTS244T 2Y3 (3) 1A0 (2) 1OE (1) VCC (20) 2OE (19) (18) 1Y0 1A1 (4) (17) 2A3 2Y2 (5) (16) 1Y1 1A2 (6) (15) 2A2 2Y1 (7) (14) 1Y2 (8) 1A3 (9) 2Y0 (10) GND (11) 2A0 (12) 1Y3 (13) 2A1 NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS244 is TA14402A. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3