HCTS373T Data Sheet July 1999 Radiation Hardened Octal Transparent Latch, Three-State Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS373T is a Radiation Hardened Octal Transparent Three-State Latch with an active-low output enable. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. • QML Class T, Per MIL-PRF-38535 • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • 3 Micron Radiation Hardened CMOS SOS • Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current Levels Ii ≤ 5mA at VOL, VOH Pinouts HCTS373T (SBDIP), CDIP2-T20 TOP VIEW Intersil’s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp Ordering Information PART NUMBER TEMP. RANGE (oC) 5962R9574701TRC HCTS373DTR -55 to 125 5962R9574701TXC HCTS373KTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. OE 1 Q0 2 19 Q7 D0 3 18 D7 20 VCC D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 LE HCTS373T (FLATPACK), CDFP4-F20 TOP VIEW OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 LE GND 1 4628.1 Features Detailed Electrical Specifications for the HCTS373T are contained in SMD 5962-95747. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp ORDERING NUMBER File Number CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation. HCTS373T Functional Diagram 1 OF 8 (3, 4, 7, 8, 13, 14, 17, 18) D LATCH OE D Q Q (2, 5, 6, 9, 12, 15, 16, 19) LE COMMON CONTROLS LE (11) OE (1) TRUTH TABLE OE LE D Q L H H H L H L L L L I L L L h H H X X Z H = High Level, L = Low Level. X = Immaterial, Z = High Impedance. I = Low voltage level prior to the high-to-low latch enable transition. h = High voltage level prior to the high-to-low latch enable transition. 2 HCTS373T Die Characteristics DIE DIMENSIONS: PASSIVATION: (2743µm x 2692µm x 533µm ±51µm) Type: Silox (SiO2) 108 x 106 x 21mils ±2mil Thickness: 13kÅ ±2.6kÅ METALLIZATION: WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 Type: Al Si Thickness: 11kÅ ±1kÅ TRANSISTOR COUNT: SUBSTRATE POTENTIAL: 376 Unbiased (Silicon on Sapphire) PROCESS: BACKSIDE FINISH: CMOS SOS Sapphire Metallization Mask Layout HCTS373T D0 (3) Q0 (2) OE (1) VCC (20) Q7 (19) (18) D7 D1 (4) (17) D6 Q1 (5) (16) Q6 Q2 (6) (15) Q5 D2 (7) (14) D5 (8) D3 (9) Q3 (10) GND (11) LE (12) Q4 (13) D4 NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS373 is TA14403A. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3