[AK1599V] AK1599V RF Transmitter for Satellite Communication 1. General Description AK1599V is a RF transmitter integrating Quadrature Modulator, RF Amplifier, fractional / integer synthesizer and VCO which support RF output frequency from 1600MHz to 2200MHz. AK1599V achieves very low power consumption for Satellite Communication. 2. Feartures Transmitter Integrated Local signal generator Integrated Quadrature Modulator Maximum output power: -13dBm minimum Integrated Gain control amplifier Gain range: 12dB typical Supply Voltage/ Operating Temperature Supply Voltage Analog: 5V Digital Interface: 5V / 3.3V (when internal 3.3V regulator is used) Operating Temperature -40 to 85 C 015006835-E-00 2015/5 -1- [AK1599V] 3. Table of Contents 1. 2. 3. 4. General Description ............................................................................................................................ 1 Feartures ............................................................................................................................................. 1 Table of Contents ................................................................................................................................ 2 Block Diagram and Functions ............................................................................................................. 3 4.1. Block Diagram ................................................................................................................................. 3 4.2. Functions ......................................................................................................................................... 3 5. Pin Configurations and Functions ....................................................................................................... 4 5.1. Pin Configurations ........................................................................................................................... 4 5.2. Functions ......................................................................................................................................... 4 6. Absolute Maximum Ratings ................................................................................................................ 7 7. Recommended Operating Conditions................................................................................................. 8 8. Electrical Characteristics ..................................................................................................................... 9 8.1. Analog Specification ........................................................................................................................ 9 8.2. Digital Specification ....................................................................................................................... 12 9. Functional Descriptions ..................................................................................................................... 14 9.1. Operating Mode ............................................................................................................................. 14 9.2. PLL................................................................................................................................................. 14 9.3. Lock Detection ............................................................................................................................... 15 9.4. Frequency Settings ........................................................................................................................ 17 9.5. Fast lock up mode ......................................................................................................................... 18 9.6. VCO ............................................................................................................................................... 18 9.7. Loop Filter ...................................................................................................................................... 19 9.8. Quadrature Modulator ................................................................................................................... 19 9.9. SPI & Register ............................................................................................................................... 19 10. Register Map ................................................................................................................................. 20 11. Power up Sequence ...................................................................................................................... 27 12. Recommended External Circuits................................................................................................... 31 13. LSI Interface Schematic ................................................................................................................ 35 14. Package ......................................................................................................................................... 37 14.1. Outline Dimensions ................................................................................................................ 37 14.2. Marking................................................................................................................................... 38 15. Appendix ........................................................................................................................................ 39 Integrated Phase Noise in fractional / integer mode ............................................................................ 39 16. Revision History............................................................................................................................. 40 IMPORTANT NOTICE .......................................................................................................................... 41 015006835-E-00 2015/5 -2- [AK1599V] 4. Block Diagram and Functions 4.1. Block Diagram VDD*: CPBUFVDD, PVDD, MODVDD, MODVDD, BALVDD, TXVDD, LOVDD, OAVDD, SVDD, VCOVDD, CPVDD Fig.1 Block Diagram 4.2. Functions Table1. Block Functions Block Quadrature Modulator N divider ΔΣ Modulator R divider Phase Frequency Detector (PFD) Charge Pump VCO 1.8V Regulator 3.3V Regulator Function Up-convert baseband I/Q input signal to RF signal. Frequency divider which divides the signal of VCO and pass it to phase frequency detector. Control the modulus of N divider and realize fractional dividing. Frequency divider which divides the signal of reference clock and pass it to phase frequency detector. Detect a phase difference between the divided VCO signal and comparison frequency, and then drive the charge pump. Output the electric charge according to the phase difference detected by PFD. The voltage controlled oscillator. Create 1.8V for internal digital block. Create 3.3V for digital interface. 015006835-E-00 2015/5 -3- [AK1599V] 5. Pin Configurations and Functions 5.1. Pin Configurations Top View Fig.2 Pin Configuration 5.2. Functions Table2. Pin Functions Pin Pin Name No. 1 GND 2 GND 3 CPBUFVDD 4 REFIN 5 VREF1 I/O Type G G P AI AO Pin Description Charge Pump Pre-Buffer Power Supply. Reference Input signal. Connecting a capacitor and a resistor in series to the ground plane in order to stabilize internal 1.8V regulator for digital 015006835-E-00 2015/5 -4- [AK1599V] Pin No. Pin Name I/O Type 6 7 8 9 10 11 12 13 14 15 16 17 PVDD IFSEL TEST1 TEST2 BBQP BBQN GND GND GND MODVDD MODVDD GND P DI DI DI AI AI G G G P P G 18 RFOUT AO 19 20 21 22 23 24 25 26 27 28 29 BALVDD GND GND TXVDD GND GND GND BBIN BBIP GND LOVDD P G G P G G G AI AI G P 30 LOP AIO 31 LON AIO 32 OAVDD P 33 SVDD P/AO 34 35 36 37 38 39 DATA CLK TXON LD LE DATAO DI DI DI DO DI DO 40 PDN DI 41 VCNT AI 42 VREF2 AO Pin Description block. Synthesizer Power Supply. Enable/Disable internal 3.3V regulator for digital interface. Connect to the ground plane. Connect to the ground plane. Baseband Differential Q Signal input. Baseband Differential Q Signal input. Quadrature Modulator Power Supply. Quadrature Modulator Power Supply. RF signal output. Connecting matching network after a decoupling capacitor. Balun Power Supply. TX IREF Power Supply. Baseband Differential I Signal input. Baseband Differential I Signal input. Local Power Supply. Local differential Input / Output. Open this pin if not used. Local differential Input / Output. Open this pin if not used. Local Output Amplifier Power Supply. External Power Supply / Internal 3.3V regulator for digital interface (selected by IFSEL pin). Serial Data Input. Serial Clock Input. TX Power Control. Lock Detection Output Interface. Load Enable. Output pin for read back data. Power Control. A logic low on this pin power down the device. Control Input to VCO. Connecting a capacitor to the ground plane in order to remove noise of internal 1.8V regulator for digital block. 015006835-E-00 2015/5 -5- [AK1599V] Pin No. 43 44 45 GND VCOVDD GND I/O Type G P G 46 CPBIAS AI 47 48 CPOUT CPVDD AO P Pin Name Pin Description VCO Power Supply. Connecting a resistor to the ground plane in order to create reference current for Charge Pump. Charge Pump Output. Charge Pump Power Supply. Exposed PAD on Back side of the package should be connected to GND P : Power Supply AI : Analog Input DI : Digital Input G : Ground AO : Analog Output DO : Digital Output AIO : Analog I/O 015006835-E-00 2015/5 -6- [AK1599V] 6. Absolute Maximum Ratings Table3. Absolute Maximum Ratings Parameter Symbol VDD1 Power Supply Voltage VDD2 VDD3 GND Level VSS Maximum BB Input Level Maximum Lo Input Level Input Voltage Input Current Storage Temperature Maximum Junction Temperature Note1 Note2 Note3 Note4 Note5 Note6 Note7 Note8 Note9 BBPOW LOPOW VAIN VDIN1 IIN Tstg Min. -0.3 -0.3 -0.3 Max. 5.5 5.5 5.5 Unit V V V 0 0 V VSS-0.3 VSS-0.3 -10 -55 10 12 VDD3+0.3 VDD1+0.3 10 150 dBm dBm V V mA C 150 C Tjmax Remarks Note1, Note2 Note1, Note3 Note1, Note4 Voltage Reference Level, Note5 Note6 Note7 Note1, Note8 Note1, Note9 0V reference for all voltages Applied to [SVDD] pin. Applied to [BALVDD], [TXVDD], [MODVDD], [OAVDD] and [LOVDD] pins. Applied to [CPVDD], [CPBUFVDD], [PVDD] and [VCOVDD] pins. Applied to [GND] pin. Applied to [BBIP], [BBIN], [BBQP] and [BBQN] pins. Applied to [LOP] and [LON] pins. Applied to [VCNT], [IFSEL] and [REFIN] pins. Applied to [CLK], [DATA], [LE], [PDN] and [TXON] pins. Table4. Thermal Resistance Package Type 48-pin QFN θJA 26.7 θJC 18.1 Unit °C/W θJA: Thermal Resistance between junction and ambience θJC: Thermal Resistance between junction and surface of package Exceeding these maximum ratings may result in damage to AK1599V. Normal Operation is not guarantee at these extremes. 015006835-E-00 2015/5 -7- [AK1599V] 7. Recommended Operating Conditions The specifications are applicable within operating range (supply voltage / operating temperature) specified below. Table5. Recommended Operating Conditions Parameter Min. Typ. Max. Unit Operating Temperature Supply Voltage VDD1 VDD2 VDD3 VDD1 - VDD2 Note1 Note2 -40 4.75 4.75 4.75 -0.1 5 5 5 85 C 5.25 5.25 5.25 0.1 V V V V Conditions SVDD (Note1, Note2) TXVDD, BALVDD, MODVDD, LOVDD, OAVDD CPVDD, CPBUFVDD, PVDD, VCOVDD (Note2) This specification is applicable when SVDD is externally applied. Don’t apply voltage to SVDD in internal 3.3V Regulator Mode. VDD1 - VDD2 is the specification when SVDD is externally applied. 015006835-E-00 2015/5 -8- [AK1599V] 8. Electrical Characteristics 8.1. Analog Specification Typical specifications: VDD1 = 5V, VDD2 = 5V, VDD3 = 5V, Baseband frequency 960 kHz Baseband Continuous Wave (BBCW) Input = 0.5 (Vpp, differential). I/Q Input Bias Level = 0.5V Operating Temperature = 25C. Resistor connected to CPBIAS pin is 27k. Min/Max specifications are at “6.1 Recommended Operating Range”. Operating Mode = State5. Unless otherwise noted. Table6. Electrical Characteristics Parameter Min. Typ. Power Consumption RF Frequency Range Internal LO Frequency Internal VCO Frequency LO Input Level LOP / LON Return Loss 1.3 Max. Unit 1.7 W 1600 2200 MHz 1700 2100 MHz 3400 4200 MHz -5 +5 dBm -10 PDN pin = TXON pin = “H”, Ref = 40MHz, R divider = 1, PFD = 40MHz, DIV[1:0] bits = LOLV[1:0] bits = “00”, Pomax(TXGAIN[6:0] bits = ”1111111”), MODE[1:0] bits = “00” dB dBm LO = 3.8GHz LOLV[1:0] bits = ”11” LOLV[1:0] bits = “10” LOLV[1:0] bits = “01” LOLV[1:0] bits = “00” -6 dBm Pomax(TXGAIN[6:0] bits = ”1111111”) BB CW Input = 0.5(Vpp, differential) -0.5 dB 0 -2 -5 -11 LO Output Level Conditions Transmitter RF Output Power -13 RF Output Power over temperature Output P1dB 0 4 dBm OIP3 10 14 dBm Offset < 256kHz -55 dBc 256kHz to 960kHz -62 dBc 960kHz to 10MHz -76 dBc 10MHz to 50MHz -76 dBc Spurs 015006835-E-00 -40C to 25C or 25C to 85C Pomax(TXGAIN[6:0] bits = ”1111111”) Pomax(TXGAIN[6:0] bits = ”1111111”) (Baseband Frequency = 5MHz, 6MHz) Pomax(TXGAIN[6:0] bits = ”1111111”) BB CW Input = 0.5(Vpp, differential) LO ≤ 1.9GHz, Only Integer Mode, Int ≤ 95, Frac = 0, Mod = 1, (Note1) Baseband Frequency < 100MHz Offset frequency is double side from carrier 2015/5 -9- [AK1599V] Parameter Min. Max. Unit Carrier Suppression -40 dBc Sideband Rejection -40 dBc 2nd Harmonics -45 dBc 3rd Harmonics -45 dBc Output Return Loss Gain Control Gain Range Gain Control Step Typ. -15 dB 12 dB 0.5 dB 10 k Vpp MHz V Conditions Pomax(TXGAIN[6:0] bits = ”1111111”) BB CW Input = 0.5(Vpp, differential) Pomax(TXGAIN[6:0] bits = ”1111111”) BB CW Input = 0.5(Vpp, differential) Pomax(TXGAIN[6:0] bits = ”1111111”) BB CW Input = 0.5(Vpp, differential) 2nd Harmonics(Pout - P(flo + 2fbb)) Pomax(TXGAIN[6:0] bits = ”1111111”) BB CW Input = 0.5(Vpp, differential) 3rd Harmonics(Pout - P(flo + 3fbb)) 50 matched by recommended circuit shown on “11. Typical Evaluation Board Schematic” Base Band Inputs Input impedance Input Range 1dB down BW I/Q Input Bias Level 2 100 0.5 Power Down/Up Response Time IQ differential IQ differential, Continuous Wave Modulator and Amplifier can be ON/OFF by TXON pin. In case of Power Up, this is ±1dB settling time against final value. In case of Power down, this is the time before output power becomes under -60dBm. 3 10 s 0.18 0.23 degree rms LO ≤ 1.9GHz, Only Integer Mode, 2.5 kHz to 4 MHz integration bandwidth Int ≤ 95, Frac = 0, Mod = 1, (Note1) 0.21 0.25 degree rms LO ≤ 2.1GHz, Only Integer Mode, 2.5 kHz to 4 MHz integration bandwidth Int ≤ 105, Frac = 0, Mod = 1, (Note1) 0.7 10 2 300 Vpp MHz 1.2 40 MHz PLL Integrated Phase Noise (Integer Mode) REFIN Input Sensitivity Input Frequency PFD Phase Detector Frequency 015006835-E-00 2015/5 - 10 - [AK1599V] Parameter Min. Charge Pump Minimum Charge Pump Current Maximum Charge Pump Current Icp TRI-STATE Leak Current CP Output Range VCO Operating Frequency Range Typ. Max. Unit 300 A 2400 A 1 nA 0.5 VDD3 -0.5 V 3400 4200 MHz dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz -76 -101 VCO Phase Noise -122 -143 1.7 2.2 Ta = 25C VCO 10kHz offset, 3.6GHz 100kHz offset, 3.6GHz 1MHz offset, 3.6GHz 10MHz offset, 3.6GHz ms Jump from unlocked state to LO = 1.9GHz ±2.5Hz settling time, (Note1) ms Jump from 1.7G to 2.1GHz, 2.1G to 1.7GHz ±2.5Hz settling time, (Note1) PLL switching time 1.4 Conditions IDD IDD1 2 IDD2 260 IDD3 280 mA 324 mA mA PDN pin = “L” PDN pin = TXON pin = “H”, Ref = 40MHz, R divider = 1, PFD = 40MHz, DIV[1:0] bits = LOLV[1:0] bits = “00”, Pomax(TXGAIN[6:0] bits = ”1111111”), MODE[1:0] bits = “00” PDN pin = TXON pin = “H”, Ref = 40MHz, R divider = 1, PFD = 40MHz, DIV[1:0] bits = LOLV[1:0] bits = “00”, Pomax(TXGAIN[6:0] bits = ”1111111”), MODE[1:0] bits = “01” Note1 Ref = 40MHz, PFD = 40MHz, R divider = 1 Loop Filter: C1 = 100pF, C2 = 8.2nF, C3 = 100pF, R2 = 1.2k, R3 = 1k, CP1 = 900A 015006835-E-00 2015/5 - 11 - [AK1599V] 8.2. Digital Specification Table7. Digital DC Characteristics Parameter Symbol Condition Vih1 High Level Vih2 Input Voltage Vih3 Note4 Vil1 Low Level Input Vil2 Voltage Vil3 Note4 Iih1 Vih=VDD1=5.25V High Level Input Current Iih2 Vih=VDD3=5.25V Vil=0V, Iil1 VDD1=5.25V Low Level Input Current Vil=0V, Iil2 VDD3=5.25V Voh1 Ioh = -500A High Level Note4 Output Voltage Voh2 Ioh = -500A Low Level Vol Iol = 500A Output Voltage Note1 Note2 Note3 Note4 Min. 0.8VDD1 0.8VDD3 2.4 Typ. Max. -1 -1 0.2VDD1 0.2VDD3 0.6 1 1 Unit V V V V V V A A Remarks Note1 Note2 Note1 Note1 Note2 Note1 Note1 Note2 -1 1 A Note1 -1 1 A Note2 VDD1-0.4 V Note3 2.8 V Note3 V Note3 0.4 Applied to [CLK], [DATA], [LE], [PDN] and [TXON] pins. Applied to [IFSEL] pin. Applied to [LD] and [DATAO] pins. Internal 3.3V Regulator Mode 015006835-E-00 2015/5 - 12 - [AK1599V] 2. Serial Interface Timing <Write-In Timing> Tcsu Tle Tlesu LE (Input) Tch Tcl CLK (Input) Tsu DATA (Input) D19 Thd D0 D18 A3 A2 A1 A0 Fig.3 Serial Interface Timing (Write-In) <Read-Back Timing> Tcsu Tlesu Tle LE (Input) Tch Extra 1 CLK is needed after D0 bit is read back Tcl CLK (Input) Tsu DATA (Input) D19 Thd D18 DATAO (output) D0 A3 Set arbitrary address number to be read back A2 A1 A0 tDD Set Address0x06 to read back D19 D18 D17 D1 D0 Fig.4 Serial Interface Timing (Read-Back) tpdn VIH PDN VIL Fig.5 Power Down Pin Timing Table8. Digital AC Characteristics Parameter Clock L level hold time Clock H level hold time Clock setup time Data setup time Data hold time LE setup time LE pulse width Symbol Tcl Tch Tcsu Tsu Thd Tlesu Tle CLK to DATAO output delay time tDD PDN pin “L” level hold time tpdn Condition Min. 25 25 10 10 10 10 25 15pF Load 1 Typ. Max. Unit ns ns ns ns ns ns ns 20 ns Remarks s Be sure to input CLK when LE pin = “L” otherwise AK1599V is going to malfunction. 015006835-E-00 2015/5 - 13 - [AK1599V] 9. Functional Descriptions 9.1. Operating Mode (a) Operating mode controlled by PDN pin, TXON pin and MODE[1:0] bits Table9. Operating Mode Pin Pin Mode PDN TXON State 0 State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 Registers MODE MODE [1] [0] X X 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 TX Block OFF OFF OFF OFF OFF ON ON ON ON Operation of each block Synthesizer VCO LOP, Block Block LON pin OFF OFF OFF ON ON OFF ON ON Output ON OFF Input OFF OFF Input ON ON OFF ON ON Output ON OFF Input OFF OFF Input State0: Standby mode. Current Consumption becomes minimum. Register setting is available. (Note) State1: VCO and Synthesizer operate. State2: VCO and Synthesizer operate and output its signal from LOP, LON pins. State3: Only Synthesizer operates. PLL can be operated by using external VCO. State4: Standby mode. Current Consumption becomes minimum. Register setting is available. (Note) State5: TX block operates in addition to State1. State6: TX block operates in addition to State2. State7: TX block operates in addition to State3. State8: TX block operates. Input local signal from LOP, LON pins. (Note) After powering on AK1599V, the initial registers values are not defined. It is required to write the data in all addresses. (b) Digital interface voltage option selected by IFSEL pin Regarding SVDD which is power supply for digital interface, either external power supply (5V) or internal 3.3V regulator can be selected. Table10. Function of IFSEL pin IFSEL “L” (should be connected to GND) “H” (should be connected to PVDD) SVDD External Power Supply (5V) Internal 3.3V regulator 9.2. PLL The Phase Locked Loop consists of a Fractional / Integer Frequency synthesizer. The PLL covers LO frequency range from 1700MHz to 2100MHz. It also has an integrated voltage controlled oscillator (VCO) which achieves good phase noise performance. 015006835-E-00 2015/5 - 14 - [AK1599V] 9.3. Lock Detection Lock detection output can be selected by LD bit in Address0x04. When LD bit = “1”, LD pin outputs a phase comparison result which is from phase detector directly (This is called “analog lock detection”). When LD bit = “0”, the output is the lock detection signal according to the on-chip logic (This is called “digital lock detection”). The digital lock detection can be done as following: LD pin stays unlocked state (which outputs “L”) when frequency setup is made. In the digital lock detection, LD pin signal rises to “H” (which means the locked state) after a phase error smaller than a cycle of [REFIN] clock (T) is detected for N times consecutively. After a phase error larger than T is detected for N times consecutively when LD pin = “H”, LD pin signal drops to “L” (which means the unlocked state). The counter value N can be set by LDCNTSEL bit in Address0x04. The N is different between “unlocked to locked” and “locked to unlocked”. Table11. Lock Detection Precision LDCNTSEL bit unlocked to locked “0” N = 15 “1” N = 31 locked to unlocked N=3 N=7 The lock detection signal is shown below: Reference clock Phase Comparison signal T/2 Divided VCO signal Phase detector signal This is ignored because it cannot be sampled. Valid ignore ignore d ignore Valid The LD pin outputs HIGH when a phase error which is smaller than T/2 is detected for N times consecutively. LD signal Case of “R = 1” (Note) Reference clock Phase Comparison signal T Divided VCO signal Phase Detector signal This is ignored because it cannot be sampled. Valid This is ignored because it cannot be sampled. LD signal ignore Valid The LD pin outputs HIGH when a phase error which is smaller than T is detected for N times consecutively. Case of “R > 1” (Note) (Note) R is registers in Address0x03 Fig.6 Digital Lock Detection Operations 015006835-E-00 2015/5 - 15 - [AK1599V] Unlock to Lock Unlock(LD=LOW) Flag=0 No Phase Error < T Yes Flag=Flag+1 No Flag>N Yes Lock(LD=HIGH) Fig.7 Unlock to Lock Lock to Unlock Lock(LD=HIGH) Flag=0 No Phase Error > T Yes Flag=Flag+1 No Flag>N Yes Unlock(LD=LOW) Fig.8 Lock to Unlock 015006835-E-00 2015/5 - 16 - [AK1599V] 9.4. Frequency Settings <Synthesizer settings> The following formula is used to calculate the frequency setting for the AK1599V. Setting Frequency = Ref Frequency * (INT + FRAC / MOD) Ref Frequency : Phase detector frequency INT : Setting value of Integral divider (Refer to Address0x01: INT[11:0] bits) FRAC : Setting value of numerator (Refer to Address0x02: FRAC[11:0] bits) MOD : Setting value of denominator (Refer to Address0x03: MOD[11:0] bits) Set INT[11:0] bits within a range from 35 to 4091. Set FRAC[11:0] bits in accordance with following range : 0 ≤ FRAC ≤ (MOD-1). Set MOD[11:0] bits within a range from 2 to 4095. ○ Calculation example In order to achieve setting frequency = 3602MHz with Ref Frequency = 40MHz, set following values. RFOUT Carrier frequency is the half of synthesizer setting frequency. INT FRAC MOD = = = 90 1 20 Synthesizer setting Frequency = 40MHz * (90 + 1 / 20) = 3602MHz RFOUT carrier frequency = 3602MHz / 2 = 1801MHz Frequency Settings are done by setting Address0x01, 0x02 and 0x03. The settings of Address0x02 and 0x03 are reflected simultaneously with setting Address0x01. Synthesizer block should be powered on before Address0x01 is set. Frequency settings, VCO calibration and Fast Lock Counter start its operation simultaneously with setting Address0x01. In order to set frequency correctly, be sure to set Address0x01 after setting PDN pin = ”H” and MODE[1:0] bits in Address 0x04 = “00” or “01”. 015006835-E-00 2015/5 - 17 - [AK1599V] 9.5. Fast lock up mode The fast lock up mode becomes effective by setting FASTEN bit of address 0x04 = ”1”. ○Fast lock up mode After setting Address0x01 when FASTEN bit = “1”, Fast Lock Up mode starts after VCO calibration. The Fast Lock Up mode is enabled only when the time period set by the timer according to the counter value defined by FAST [3:0] bits in Address0x04. The charge pump current is set to the value specified by CP2 bit. After the specified time period elapses, the Fast Lock Up mode is finished and switched to the normal operation, and the charge pump current returns to CP1 bit setting. Fast Lock Up time specified by the timer Operation mode Charge pump current Normal Calibration Fast Lock Up Normal CP1 Hi-Z CP2 CP1 Frequency setting (Setting Address0x01) Fig.9 Fast Lock up Mode Timing Chart ○Timer period FAST[3:0] bits in Address0x04 is used to set the time period for the fast lock mode. The following formula is used to calculate the time period Time period = (511 + FAST[3:0] × 512) / PFD frequency 9.6. VCO <Calibration> The calibration starts by setting Address0x01 when MODE[1:0] bits in Address 0x04 = “00” or “01” and PDN pin = ”H”. During the calibration, VCO VTUNE is disconnected from the output of the loop filter and connected to an internal reference voltage. In addition, the charge pump output is disabled during calibration. The internal reference voltage must be stable so that the calibration is done correctly. Therefore, after setting PDN pin = “H”, it is necessary to wait 500s at least before setting Address0x01. CALTM[3:0] bits determines the calibration time. The larger CALTM[3:0] bits are set, the higher calibration precision becomes, but the calibration time becomes long. The value calculated by the following formula is recommended to achieve enough calibration precision. However, CALTM[3:0] bits should be set between 1 and 11. 0 and over 12 are prohibited. CALTM[3:0] ≥ log2 (PFD frequency / 20000) The calibration time can be estimated as following calculation. Calibration time = 1 / PFD frequency × {(6 + 2 ^ {CALTM [3:0]}) × 8 + 3} 015006835-E-00 2015/5 - 18 - [AK1599V] 9.7. Loop Filter Fig. 10 shows loop filter topology used to evaluate AK1599V. Phase Detector Loop Filter up R3 CPOUT C1 down R2 C3 Timer C2 VCO VCNT Fig.10 Loop Filter 9.8. Quadrature Modulator AK1599V consists of Quadrature Modulator, RF amplifier, and Programmable attenuator. A polarity of Quadrature Modulator is as follows. Recommended DC bias Voltage to Baseband I/Q Input is 0.5V±0.025V. Fig.11 Block diagram of internal Quadrature Modulator 9.9. SPI & Register AK1599V contains Serial Peripheral Interface (SPI) which provides write and read access to internal registers that are used to configure the device. 015006835-E-00 2015/5 - 19 - [AK1599V] 10. Register Map Register Settings Name D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 VCO VCO DIV [1] [0] [1] Freq1 CP1 CP1 CP1 [2] [1] [0] Freq2 Freq3 Function1 R [7] R [6] R [5] R [4] CAL CAL CAL CAL TM TM TM TM [3] [2] [1] [0] DIV [0] INT [11] INT [10] D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Addres s INT [9] INT [8] INT [7] INT [6] INT [5] INT [4] INT [3] INT [2] INT [1] INT [0] 0x01 CP2 CP2 CP2 FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC [2] [1] [0] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] R [3] R [2] LD CNT SEL Function2 R [1] R [0] LD MTLD MOD MOD MOD MOD MOD MOD MOD MOD MOD MOD MOD MOD [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] MO DE [1] 0x04 TXGA TXGA TXGA TXGA TXGA TXGA TXGA IN[6] IN[5] IN[4] IN[3] IN[2] IN[1] IN[0] 0x05 REA DAD D[5] INITI AL1 [5] INITIAL1 REA DAD D[4] INITI AL1 [4] REA DAD D[3] INITI AL1 [3] INITIAL2 Note of writing into registers 1. The settings of Address0x02 and 0x03 are reflected to internal circuits simultaneously with setting Address0x01. 2. It is possible to set Address0x04, 0x05, 0x06, 0x07 and 0x0D separately. 3. After powering up AK1599V, the initial registers value is not defined. It is required to write the data in all addresses. 2015/5 - 20 - 0x03 MO LOLV LOLV DE [1] [0] [0] FAST FAST FAST FAST FAST CP CP EN [3] [2] [1] [0] HIZ POLA Read Back 015006835-E-00 0x02 REA DAD D[2] INITI AL1 [2] REA DAD D[1] INITI AL1 [1] INITI AL2 [1] REA DAD D[0] INITI AL1 [0] INITI AL2 [0] 0x06 0x07 0x0D [AK1599V] < Address0x01: Freq1 > D[16:15] VCO[1:0]: Set VCO Write “2” to VCO[1:0] to set VCO. VCO[1:0] VCO oscillating frequency 0 Prohibited 1 Prohibited 2 3.1GHz to 4.4GHZ 3 3.1GHz to 4.4GHZ D[14:13] DIV[1:0]: Local Divider Write “0” to DIV[1:0] to set Local Divider. DIV[1:0] Division Ratio 0 2 divide 1 2 divide 2 Prohibited 3 Prohibited D[11:0] INT[11:0]: N divider Set the number integral part of divide for synthesizer. The allowed range is from 35 to 4091. INT[11:0] 0 1 34 35 36 4089 4090 4091 4092 4093 4094 4095 Division Ratio Prohibited Prohibited Prohibited 35 36 4089 4090 4091 Prohibited Prohibited Prohibited Prohibited 015006835-E-00 2015/5 - 21 - [AK1599V] < Address0x02: Freq2 > D[18:16] CP1[2:0]: Settings of the charge pump current for normal mode D[14:12] CP2[2:0]: Settings of the charge pump current for fast lock up mode It is possible to set two types of charge pump current, CP1 and CP2. CP1 is the charge pump current setting for the normal mode. CP2 is the charge pump current setting for the fast lock up mode. Charge pump current is as follows. CP1[2:0], CP2[2:0] 0 1 2 3 4 5 6 7 Charge pump current [ typ. μA ] 300 600 900 1200 1500 1800 2100 2400 R = 27k R: Resistor value which is connected to CPBIAS pin D[11:0] FRAC[11:0]: Fractional Numerator determination Set the Numerator of Fractional divider. The allowed range is from 0 to MOD[11:0]. When FRAC is set to 0, ΔΣ modulator is inactivated and synthesizer operates as Integer-N synthesizer. 015006835-E-00 2015/5 - 22 - [AK1599V] < Address0x03: Freq3 > D[19:12] R[7:0]: 8bit Reference divider Maximum PFD frequency is 40MHz. R[7:0] 0 1 2 3 4 253 254 255 Division Ratio Prohibited 1 2 3 4 253 254 255 D[11:0] MOD[11:0]: Fractional Denominator determination Set the denominator of Fractional divider. The allowed range is from 2 to 4095. MOD[11:0] 0 1 2 3 4089 4090 4091 4092 4093 4094 4095 Division Ratio Prohibited Prohibited 2 3 4089 4090 4091 4092 4093 4094 4095 015006835-E-00 2015/5 - 23 - [AK1599V] < Address0x04: function1 > D[19:16] CALTM[3:0]: Set the calibration precision of VCO CALTM[3:0] bits determines the calibration precision of VCO and time. The larger CALTM[3:0] bits are set, the higher calibration precision becomes, but the calibration time becomes long as trade-off. The value calculated by the following formula is recommended to achieve enough calibration precision. However, CALTM[3:0] bits should be set between 1 and 11. 0 and Over 12 are prohibited. CALTM[3:0] ≥ log2 (PFD frequency / 20000) The calibration time can be estimated as following calculation; Calibration time = 1 / PFD frequency × {(6 + 2 ^ {CALTM[3:0]}) × 8 + 3} D[14] LDCNTSEL: Lock Detection Precision Set the counter value for digital lock detection. LDCNTSEL 0 1 Function 15 times Count 3 times Count 31 times Count 7 times Count unlocked to locked locked to unlocked unlocked to locked locked to unlocked D[13] LD: Lock detection function Set the lock detection function. Refer to "8.2.1.Lock Detection" for details. 0: Digital lock detection 1: Analog lock detection D[12] MTLD: Local signal mute. Select disable or enable to mute during unlocked state. 0: Disable to mute local signal during unlocked state 1: Enable to mute local signal during unlocked state Be sure to set MTLD bit = 0 when LD bit = 1, so that Lock detection is Analog mode. D[11] FASTEN: Fast lock up mode setting Set enable / disable fast lock up mode. 0: Disable fast lock up mode 1: Enable fast lock up mode Refer to "8.2.3. Fast lock up mode" for details. 015006835-E-00 2015/5 - 24 - [AK1599V] D[10:7] FAST[3:0]: Fast lock timer setting Set the count number of fast lock timer. Count Number = 511+ FAST[3:0] × 512 FAST[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Count Number 511 1023 1535 2047 2559 3071 3583 4095 4607 5119 5631 6143 6655 7167 7679 8191 D[6] CPHIZ: Charge Pump Hi-Z Set the charge pump state to Hi-Z. 0: Normal 1: Hi-Z (Prohibited) Be sure to set CPHIZ bit = “0”. D[5] CPPOLA: Charge pump output polarity Set the charge pump output polarity. 0: Negative (Prohibited) 1: Positive Be sure to set CPPOLA bit = “1”. D[3:2] MODE[1:0]: Local operation mode Set the operation of Synthesizer, VCO, LOP and LON pins. MODE[1:0] Local Operating MODE 0 Internal Synthesizer and VCO are activated. Internal Synthesizer and VCO are activated and the local 1 signal is output from LOP and LON pins. Internal VCO is inactivated. External VCO can be used with 2 internal synthesizer. Internal Synthesizer and VCO are inactivated. External local 3 signal can be used. Synthesizer setting frequency is output from LOP and LON pins when MODE[1:0] bits = “1”. Refer to “8.2.2 Frequency Settings” for details. The double carrier frequency of RFOUT should be input from LOP and LON pins when MODE[1:0] bits = “3”. 015006835-E-00 2015/5 - 25 - [AK1599V] D[1:0] LOLV[1:0]: Local output Power When MODE[1:0] bits = “1”, set the power of the local signal output from LOP and LON pins. LOLV[1:0] LOP, LON output power [dBm] 0 -11 1 -5 2 -2 3 0 < Address0x05: function2 > D[6:0] TXGAIN[6:0]: Switching attenuator gain of TX block. It is possible to set gain by 0.5dB step. TXGAIN[6:0] 1111111 1111110 1111101 1111100 : 1101000 1100111 1100110 : 0000000 Attenuation [dB] 0 -0.5 -1 -1.5 : -11.5 -12 Prohibited : Prohibited < Address0x06: Read Back > D[5:0] READADD[5:0]: Read Back Set address of register whose data will be read back and output from DATAO pin. Regarding the output timing, refer to” 7.3 Digital Specification”. Set following address and data whenever read back is done. <Address0x0D: INITIAL2> 00000h < Address0x07: INITIAL1 > D[5:0] INITIAL1[5:0]: This register must be set right after power-up < Address0x0D: INITIAL2 > D[1:0] INITIAL2[1:0]: This register must be set right after power-up 015006835-E-00 2015/5 - 26 - [AK1599V] 11. Power up Sequence ■ Recommended Power up Sequence PDN pin resets digital block except registers and powers down analog block. On the other hand, AKM recommends user to set all registers before powering up analog block because registers don’t have reset. LOP/LON don’t output any undesired signal in the recommended power up sequence. However, DATAO pin may output undesired signal for a period of 20CLK from CLK starts because initial value of Flip-Flop for ReadBack is undefined. RFOUT pin doesn’t output undesired signal by setting TXON pin = “L”. Fig.12 Recommended Power up Sequence (Internal 3.3V Regulator Mode) 015006835-E-00 2015/5 - 27 - [AK1599V] Power up Sequence should be done as follows. [1] Power up VDD/IFSEL [2] 10ms after VDD is powered up, set all registers as following order. (Note1) <Address0x02:Freq2> Arbitrary Data <Address0x03:Freq3> Arbitrary Data <Address0x01:Freq1> Arbitrary Data <Address0x04:Function1> Arbitrary Data <Address0x05:Function2> Arbitrary Data <Address0x07:INITIAL1> 00001h <Address0x0D:INITIAL2> 00000h <Address0x0D:INITIAL2> 00003h <Address0x0D:INITIAL2> 00000h [3] Power up PDN [4] 500s after PDN is powered up, set the register as follows. (Note2) <Address0x01:Freq1> Arbitrary Data [5] 5ms after Address0x01 is set, power up TXON. (Note3) (Note1) 10ms is waiting time for internal regulator to become stable (Note2) 500s is waiting time for synthesizer analog block to start up and become stable (Note3) 5ms is waiting time for local frequency to become stable 015006835-E-00 2015/5 - 28 - [AK1599V] ■ Power up Sequence of VDD/IFSEL and PDN pin simultaneous launch (Internal 3.3V Regulator Mode) PDN pin resets digital block except registers and powers down analog block. First of the sequence, be sure to power down analog block by setting MODE[1:0] in Address0x04 = ”11”. LOP, LON and LD pins may output undesired signal before setting MODE[1:0] = ”11” because initial value of registers is undefined. DATAO pin may output undesired signal for a period of 20CLK from CLK starts. RFOUT pin doesn’t output undesired signal by setting TXON pin = “L”. Fig.13 Power up Sequence of VDD/IFSEL and PDN pin simultaneous launch (Internal 3.3V Regulator Mode) 015006835-E-00 2015/5 - 29 - [AK1599V] Power up Sequence of VDD / IFSEL and PDN pin simultaneous launch should be done as follows. [1] Power up VDD / IFSEL and PDN [2] 10ms after VDD is powered up, set all registers as following order. (Note4) <Address0x04:Function1> MODE [1:0] = 11b, the other data is arbitrary <Address0x02:Freq2> Arbitrary Data <Address0x03:Freq3> Arbitrary Data <Address0x01:Freq1> Arbitrary Data <Address0x04:Function1> Arbitrary Data <Address0x05:Function2> Arbitrary Data <Address0x07:INITIAL1> 00001h <Address0x0D:INITIAL2> 00000h <Address0x0D:INITIAL2> 00003h <Address0x0D:INITIAL2> 00000h Wait for 500s after “<Address0x04:Function1> Arbitrary Data” is set (Note5) <Address0x01:Freq1> Arbitrary Data [3] 5ms after Address0x01 is set, power up TXON. (Note6) (Note4) 10ms is waiting time for internal regulator to become stable (Note5) 500s is waiting time for synthesizer analog block to start up and become stable (Note6) 5ms is waiting time for local frequency to become stable 015006835-E-00 2015/5 - 30 - [AK1599V] 12. Recommended External Circuits 1) Power supply stabilizing capacitors Connecting capacitors between VDD and VSS pins to eliminate ripple and noise included in power supply. For maximum effect, the capacitors should be placed at a shortest distance between the pins. 15 and 16 C1=100pF MODVDD C1 C2 C3 19 C2=10nF C3=10F (Electrolytic cap) BALVDD C1 C2 C1 C2 C1 C2 22 TXVDD 29 LOVDD 3 CPBUFVDD C3 C1 6 PVDD C1 C2 C1 C2 C1 C2 C1 C2 32 OAVDD 44 VCOVDD 48 CPVDD LSI 015006835-E-00 2015/5 - 31 - [AK1599V] 2) SVDD External Power Supply: IFSEL pin is connected to the ground plane C1=100pF 33 C2=10nF SVDD C1 C3 C2 C3=10F (Electrolytic cap) LSI Internal Regulator: IFSEL pin is connected to PVDD 33 C=100nF SVDD C LSI 3) REFIN 4 C REFIN C=100pF LSI 4) VREF1 5 R R=100Ω VREF1 C1 C2 C1=100pF C2=220nF LSI 5) BBQP, BBQN C4 10 BBQP 0.5V R R=51Ω C1=100pF C2=10nF C1 C2 C3 C3=10F(Electrolytic cap) C4=33nF R 11 C4 BBQN LSI 015006835-E-00 2015/5 - 32 - [AK1599V] 6) BBIP, BBIN C4 27 BBIP R=51Ω 0.5V R C1=100pF C2=10nF C1 C2 C3 C3=10F(Electrolytic cap) C4=33nF R 26 C4 BBIN LSI 7) RFOUT C1 18 L2 RFOUT C2 C3 Example) RFOUT=1.9GHz C1=100pF C2=2pF C3=Open L2=0Ωshort LSI 8) LOP, LON C 30 LOP L OAVDD C=100pF L=270nH L 31 C LON LSI 015006835-E-00 2015/5 - 33 - [AK1599V] 9) VREF2 42 C=470nF VREF2 C LSI 8) CPBIAS 46 R=27kΩ CPBIAS R LSI 9) CPOUT, VCNT R3 47 CPOUT C1 R2 C3 C2 41 VCNT LSI Example) Ref=40MHz, PFD=40MHz, Rdiv=1, CP1=900µA C1=100pF R2=1.2kΩ C2=8.2nF R3=1kΩ C3=100pF 015006835-E-00 2015/5 - 34 - [AK1599V] 13. LSI Interface Schematic No. 40 36 35 34 38 7 Pin name PDN TXON CLK DATA LE IFSEL I/O I I I I I I 37 39 LD DATAO O O 41 4 VCNT REFIN I I Function R0 () 300 300 300 300 300 300 Digital input pin R0 Digital output pin 100 300 Analog input pin R0 015006835-E-00 2015/5 - 35 - [AK1599V] No. 46 42 33 5 Pin name CPBIAS VREF2 SVDD VREF1 I/O IO IO IO IO 47 CPOUT O Analog output pin 30 31 LOP LON IO IO RF open collector output pin 10 11 26 27 BBQP BBQN BBIN BBIP AI AI AI AI Analog input pin 18 RFOUT AO RF analog output pin R0 () 300 Analog I/O pin 300 300 300 015006835-E-00 Function R0 2015/5 - 36 - [AK1599V] 14. Package 14.1. Outline Dimensions Exposed PAD on Back side of the package should be connected to GND 015006835-E-00 2015/5 - 37 - [AK1599V] 14.2. Marking a. b. c. d. e. Style Number of pins A1 pin marking Product number Date code Y WW L : QFN : 48 :● : 1599V : YMML (4 digits) : Lower one digit of calendar year (2015->5, 2016->6…) : Week : LOT identification, given to each product lot (A, B, C…) -> LOT ID is given in alphabetical order 1599V YWWL (d) (e) ●(c) Fig.14 Marking 015006835-E-00 2015/5 - 38 - [AK1599V] 15. Appendix Integrated Phase Noise in fractional / integer mode This graph is example data of one sample. <Synthesizer setting example> Measured at 25ºC, VDD2 = VDD3 = 5V Reference input frequency = 40MHz, 0dBm, R divider = 1, PFD frequency = 40MHz, int = 85 to 105, frac = 0 to 19, mod = 20 Loop Filter: C1 = 100pF, C2 = 8.2nF, C3 = 100pF, R2 = 1.2k, R3 = 1k CP1 = 600µA in fractional mode and CP1 = 900µA in integer mode. Fig. 15 Integrated Phase Noise in fractional / integer mode vs. LO frequency 015006835-E-00 2015/5 - 39 - [AK1599V] 16. Revision History Date (Y/M/D) Revision 2015/5/13 00 Reason Page Contents 015006835-E-00 2015/5 - 40 - [AK1599V] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. 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