[AK1542A] AK1542A 20 to 600MHz Integer-N Frequency Synthesizer 1. Overview Consisting a highly accurate charge pump that supports current adjustment in 9 steps, a reference divider, a programmable divider and a dual-modulus prescaler (P/P+1), the AK1542A provides high performance, low consumption current and small footprint for a wide range of frequency conversions . This synthesizer also has two general-purpose output pins which allow it to be used to control the RF front end. An ideal Phase Locked Loop (PLL) can be achieved by combining the AK1542A with the external loop filter and VCO (Voltage Controlled Oscillator). Access to the registers is controlled via a 3-wire serial interface. The operating supply voltage is from 2.7 to 5.5V; and the supply voltage for the charge pump and that for the serial interface can be driven separately. 2. Features Operating frequency: Programmable charge pump current: 20 to 600MHz 158 to 2528A typical The charge pump current can be changed in 9 steps; and the current range can be adjusted by the external resistance. Two current settings can be specified with the register and switched over from one to another using the timer. Supply Voltage: 2.7 to 5.5 V (PVDD pin) Separate power supply for the charge pump: PVDD to 5.5V (CPVDD pin) On-chip power-saving features On-chip lock detection feature of PLL: Direct output to the PFD (Phase frequency detector) or digital filtering output can be selected. General-purpose output: It has two general-purpose output ports to control peripheral parts. Very low consumption current: 2.2mA typical Package: 24pin QFN (0.5mm pitch, 4mm4mm0.75mm) Operating temperature: -40C to 85C MS1399-E-02 2014/4 -1- [AK1542A] Table of Contents 1. Overview ___________________________________________________________________________ 1 2. Features ___________________________________________________________________________ 1 3. Block Diagram _______________________________________________________________________ 3 4. Pin Functional Description ____________________________________________________________ 4 5. Absolute Maximum Ratings ___________________________________________________________ 6 6. Recommended Operating Range _______________________________________________________ 6 7. Electrical Characteristics ______________________________________________________________ 7 8. Block Functional Descriptions ________________________________________________________ 11 9. Register Map _______________________________________________________________________ 18 10. Register Function Description ________________________________________________________ 20 11. IC Interface Schematic _______________________________________________________________ 27 12. Recommended Schematic for Off-Chip Component _______________________________________ 29 13. Power-up Sequence _________________________________________________________________ 31 14. Typical Evaluation Board Schematic ___________________________________________________ 33 15. Block Diagram by Power Supply_______________________________________________________ 34 16. Outer Dimensions___________________________________________________________________ 35 17. Marking ___________________________________________________________________________ 36 In this specification (draft version), the following notations are used for specific signal and register names: [Name]: Pin name <Name>: Register group name (Address name) {Name}: Register bit name MS1399-E-02 2014/4 -2- [AK1542A] CPVSS CPVDD PVDD PVSS VREF DVSS 3. Block Diagram LDO BIAS R COUNTER 14 bit REFIN CP CHARGE PUMP PHASE FREQENCY DETECTOR CLK CPZ REGISTER 24 bit DATA LE LOCK DETECT SWALLOW COUNTER 6 bit FAST COUNTER PROGRAMABLE COUNTER 13 bit SWIN N DIVIDER GPO2 GPO1 8/9,16/17,32/33 PDN2 - PDN1 RFINN LD TEST3 PRESCALER TEST2 + TEST1 RFINP Fig. 1 Block Diagram MS1399-E-02 2014/4 -3- [AK1542A] 4. Pin Functional Description Table 1 Pin Functions No. Name 1 CPVDD P Power supply for charge pump 2 TEST3 DI Test pin 3, This pin must be connected to ground. 3 TEST1 DI Test pin 1, This pin must be connected to ground. 4 LE DI Load enable Schmidt trigger input 5 DATA DI Serial data input Schmidt trigger input 6 CLK DI Serial clock Schmidt trigger input 7 LD DO Lock detect 8 PDN2 DI Power down pin for PLL Schmidt trigger input 9 PDN1 DI Power down signal for LDO Schmidt trigger input 10 REFIN AI Reference input 11 TEST2 DI Test pin 2, This pin must be connected to ground. 12 GPO1 DO General-purpose output pin 1 “Low” 13 GPO2 DO General-purpose output pin 2 “Low” 14 DVSS G Digital ground pin 15 VREF AO Connect to LDO reference voltage capacitor 16 RFINN AI Prescaler input 17 RFINP AI Prescaler input 18 PVDD P Power supply for peripherals 19 BIAS AIO Resistance pin for setting charge pump current 20 PVSS G Ground pin for peripherals 21 CP AO Charge pump output 22 CPZ AIO Connect to the loop filter capacitor Notes 1) & 2) 23 SWIN AI Connect to resistance pin for fast Lock Up Notes 1) & 2) 24 CPVSS G Ground pin for charge pump power supply Note 1) I/O Pin Functions Power down Remarks Internal pull-down, Schmidt trigger input Internal pull-down, Schmidt trigger input “Low” Internal pull-down, Schmidt trigger input “Low” “Hi-Z” For detailed functional descriptions, see the section “Charge Pump and Loop Filter” in “8. Block Functional Descriptions”. MS1399-E-02 2014/4 -4- [AK1542A] Note 2) The input voltage from the [CPZ] pin is used in the internal circuit. The [CPZ] pin must not be open even when the fast Lock Up feature is unused. For the output destination from the [CPZ] pin, see “P.12 Fig.5 Loop Filter Schematic”. The [SWIN] pin could be open when the fast Lock Up feature is not used. Note 3) Power down refers to the state where [PDN1]=[PDN2]=”Low” after power-on. Note 4) TEST1 to 3 must be connected to ground. BIAS G: Ground pin PVSS P: Power supply pin CP DO: Digital output pin DI: Digital input pin CPZ AIO: Analog I/O pin SWIN AO: Analog output pin CPVSS AI: Analog input pin 24 23 22 21 20 19 CPVDD 1 18 PVDD TEST3 2 17 RFINP TEST1 3 LE 4 DATA 5 14 DVSS CLK 6 13 GPO2 16 RFINN TOP 10 11 12 TEST2 GPO1 9 15 VREF REFIN 8 PDN1 LD 7 PDN2 VIEW Fig. 2 Package Pin Layout MS1399-E-02 2014/4 -5- [AK1542A] 5. Absolute Maximum Ratings Table 2 Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Remarks VDD1 -0.3 6.5 V Note 1), Applied to [PVDD] pin VDD2 -0.3 6.5 V Note 1), Applied to [CPVDD] pin VSS1 0 0 V Voltage ground level, applied to [PVSS] pin VSS2 0 0 V Voltage ground level, applied to [CPVSS] pin VSS3 0 0 V Voltage ground level, applied to [DVSS] pin VAIN1 VSS1-0.3 VDD1+0.3 V Notes 1) & 2) VAIN2 VSS2-0.3 VDD2+0.3 V Notes 1) & 3) Digital Input Voltage VDIN VSS3-0.3 VDD1+0.3 V Notes 1) & 4) Input Current IIN -10 10 mA Storage Temperature Tstg -55 125 °C Supply Voltage Ground Level Analog Input Voltage Note 1) 0V reference for all voltages. Note 2) Applied to [REFIN], [RFINN] and [RFINP] pins. Note 3) Applied to [CPZ] and [SWIN] pins. Note 4) Applied to [CLK], [DATA], [LE], [PDN1], [PDN2], [TEST1], [TEST2] and [TEST3] pins. Exceeding these maximum ratings may result in damage to the AK1542A. Normal operation is not guaranteed at these extremes. 6. Recommended Operating Range Table 3 Recommended Operating Range Parameter Operating Temperature Symbol Min. Ta -40 VDD1 2.7 VDD2 VDD1 Typ. Max. Unit Remarks 85 C 3.3 5.5 V Applied to [PVDD] pin 5.0 5.5 V Applied to [CPVDD] pin Supply Voltage Note 1) VDD1 and VDD2 can be driven individually within the recommended operating range. The specifications are applicable within the recommended operating range (supply voltage /operating temperature). MS1399-E-02 2014/4 -6- [AK1542A] 7. Electrical Characteristics 1. Digital DC Characteristics Table 4 Digital DC Characteristics Parameter Symbol Conditions Min. High level input voltage Vih Low level input voltage Vil High level input current 1 Iih1 Vih = VDD1=5.5V -1 High level input current 2 Iih2 Vih = VDD1=5.5V 27 Low level input current Iil Vil = 0V, VDD1=5.5V -1 High level output voltage Voh Ioh = -500µA Low level output voltage Vol Iol = 500µA Typ. Max. Note 1) 0.2VDD1 V Note 1) 1 µA Note 2) 110 µA Note 3) 1 µA Note 1) V Note 4) V Note 4) VDD1-0.4 0.4 Note 1) Applied to [CLK], [DATA], [LE], [PDN1], [PDN2], [TEST1], [TEST2] and [TEST3] pins. Note 2) Applied to [CLK], [DATA], [LE] , [PDN1]and [PDN2] pins. Note 3) Applied to [TEST1], [TEST2] and [TEST3] pins. Note 4) Applied to [LD], [GPO1] and [GPO2] pins. MS1399-E-02 Remarks V 0.8VDD1 55 Unit 2014/4 -7- [AK1542A] 2. Serial Interface Timing <Write-In Timing> Tlesu Tle Tcsu LE (Input) Tch Tcl CLK (Input) Tsu DATA (Input) D19 Thd D0 D18 A3 A2 A1 A0 D19 Fig. 3 Serial Interface Timing Table 5 Serial Interface Timing Parameter Symbol Min. Typ. Max. Unit Clock L level hold time Tcl 40 ns Clock H level hold time Tch 40 ns Clock setup time Tcsu 20 ns Data setup time Tsu 20 ns Data hold time Thd 20 ns LE Setup Time Tlesu 20 ns LE Pulse Width Tle 40 ns Remarks Note 1) While [LE] pin is setting at “Low”, 24 iteration clocks have to be set with [CLK] pin. If 25 or larger clocks are set, the last 24 clocks synchronized data are valid. MS1399-E-02 2014/4 -8- [AK1542A] 3. Analog Circuit Characteristics The resistance of 27kΩ is connected to the [BIAS] pin, VDD1=2.7 to 5.5V, VDD2=VDD1 to 5.5V, –40°C≤Ta≤85°C Parameter Min. Typ. Max. Unit Remarks RF Characteristics Input Sensitivity Input Frequency -15 +5 -5 +5 20 600 Input frequency ≥ 100MHz dBm 20MH ≤ Input frequency < 100MHz MHz REFIN Characteristics Input Sensitivity 0.4 2 Vpp Input Frequency 5 40 MHz 75 MHz 3 MHz Maximum Allowable Prescaler Output Frequency Phase Detector Phase Detector Frequency Charge Pump Charge Pump Maximum Value 2528 µA Charge Pump Minimum Value 158 µA Icp TRI-STATE Leak Current 1 nA 0.7 ≤ Vcpo ≤ VDD2-0.7 Vcpo : Voltage at [CP] pin Mismatch between Source and Sink Currents Note 1) 10 % Vcpo = VDD2/2, Ta=25°C Icp vs. Vcpo 15 % 0.5 ≤ Vcpo ≤ VDD2-0.5, Ta=25°C 50 µs Note 2) Others VREF Rise Time Consumption Current IDD1 10 µA 2.7 mA [PDN1]=“Low”, [PDN2]=”Low" [PDN1]=”High”,[PDN2]=”High” IDD2 1.8 IDD for [PVDD] [PDN1]=”High”,[PDN2]=”High” IDD3 Note 3) 0.4 0.9 mA IDD for [CPVDD] [PDN1]=”High”,[PDN2]=”Low” IDD4 0.5 1 mA IDD for [PVDD] Note 1) Mismatch between Source and Sink Currents: [(|Isink|-|Isource|)/{(|Isink|+|Isource|)/2}] × 100 [%] Note 2) See “Fig. 4 Charge Pump Characteristics - Voltage vs. Current”: Icp vs. Vcpo: [{1/2×(|I1|-|I2|)}/{1/2×(|I1|+|I2|)}]×100 [%] MS1399-E-02 2014/4 -9- [AK1542A] Note 3) IDD3 doesn’t include the current depending on Phase Detector Frequency. IDD3 is the current the Charge Pump circuit consumes constantly. Note 4) In the case of [PDN1]=”High” and [PDN2]=”High”, the total current consumption = IDD2 + IDD3. Note 5) The shipment test is done with the exposed pad at the center of backside connected to VSS. Resistance Connected to the BIAS Pin for Setting Charge Pump Output Current Parameter BIAS resistance Min. Typ. Max. Unit 22 27 33 kΩ Remarks Icp I1 I2 I2 I1 Isink Isource 0.5 CPVDD/2 CPVDD-0.5 Vcpo Fig. 4 Charge Pump Characteristics - Voltage (Vcpo) vs. Current (Icp) MS1399-E-02 2014/4 - 10 - [AK1542A] 8. Block Functional Descriptions 1. Frequency Setup The following formula is used to calculate the frequency setting for AK1542A. Frequency setting (external VCO output frequency) = FPFD × N N : Dividing number N = [ (P × B) + A ] FPFD : Phase detector frequency FPFD = [REFIN] pin input frequency / R counter dividing number P : Prescaler Value (See<Address2>:{Pre[1:0]}) B : B (Programmable) counter value (See <Address1>:{B[12:0]}) A : A (Swallow) counter value (See <Address1>:{A[5:0]}) Calculation examples When the [REFIN] pin input frequency is 10MHz, the phase detector frequency FPFD =5kHz and the frequency setting = 460.1MHz; [The AK1542A Settings] R=10000000/5000 = 2000 (<Address3> : {R[13:0]}=2000dec) P=32 (<Address2>:{Pre[1:0]} =10bin) B=2875 (<Address1>:{B[12:0]} =2875dec) A=20 (<Address1>:{A[5:0]} =20dec) Frequency setting = 5000 × [ (32×2875) + 20] = 460.1MHz Lower limit for setting consecutive dividing numbers In the AK1542A, it is impossible to set consecutive dividing numbers below the lower limit. The lower limit is calculated by the following formula; 2 Nmin=P -P For example, in the case of P=16, it can be set 240 and over as consecutive dividing numbers. MS1399-E-02 2014/4 - 11 - [AK1542A] 2. Charge Pump and Loop Filter In AK1542A, the fast Lock Up could be achieved by changing a charge pump current and enabling the loop filter. This is called Fast Lock Up mode. For details, see ”3. Fast Lock Up Mode” on page 13. The loop filter is external and connected to [CP], [SWIN] and [CPZ] pins. The [CPZ] pin should be connected to the R2 and C2, which are intermediate nodes, even if the Fast Lock Up is not used. Therefore, R2 must be connected to the [CP] pin, while C2 must be connected to the ground. Phase Detector Loop Filter up R3 CP VCO C1 down R2' R2 C3 Timer SWIN C2 CPZ Fig. 5 Loop Filter Schematic MS1399-E-02 2014/4 - 12 - [AK1542A] 3. Fast Lock Up Mode Setting D[16]={FASTEN} in <Address4> to 1 enables the Fast Lock Up mode for AK1542A. Changing a frequency setting (The frequency is changed at the rising edge of [LE] when <Address1> and <Address2> are accessed.) or [PDN2] pin is set from ”Low” to ”High” with {FASTEN}=1 enables the Fast Lock Up mode. The loop filter switch turns ON during the timer period specified by the counter value in D[12:0] = {FAST[12:0]} in <Address4>, and the charge pump for the Fast Lock Up mode (Charge Pump 2) set by D[9:6] = {CP2[3:0]} in <Address2> is enabled. After the timer period elapsed, the loop filter switch turns OFF, the charge pump for normal operation (Charge Pump 1) set by D[3:0] = {CP1[3:0]} in <Address2> is enabled and thus normal operation returns. The register D[12:0] = {FAST[12:0]} in <Address4> is used to set the timer period for this mode. The following formula is used to calculate the time period: Phase detector frequency cycle × counter value set in {FAST[12:0]} The charge pump current could be adjusted with 9 steps for both normal operation (Charge Pump 1) and the Fast Lock Up operation (Charge Pump 2). The absolute value of the charge pump current is determined by the Resistor value connected to the [BIAS] pin. The following formula shows the relationship between the resistance value, the register setting and the electric current value. Charge pump minimum current (Icp_min) [A] = 8.55 / Resistance connected to the [BIAS] pin (Ω) Charge pump current [A] = Icp_min [A] × (CP1 or CP2 setting + 1) The allowed range value for the resistance connected to the [BIAS] pin is from 22 to 33 [kΩ]. For details of current settings, see ”Register Functional Description”. Fast lock up time specified by the timer Operation mode Charge pump Lop filter switch Normal Fast Lock Up Mode Normal Charge Pump 1 Charge Pump 2 Charge Pump 1 OFF ON OFF The frequency is changed or [PDN2] pin is set to ”High” when D[16]={FASTEN} in <Address4> is set to”1”. Fig. 6 Timing Chart for Fast Lock Up Mode MS1399-E-02 2014/4 - 13 - [AK1542A] 4. Lock Detect (LD) Signal In AK1542A, the lock detect output can be selected by D[13] = {LD} in <Address4>. When D[13] is set to “1", the phase detector outputs provide a phase detection as an analog level (comparison result). This is called “analog lock detect”. When D[13] is set to “0”, the lock detect signal is output according to the internal logic. This is called “digital lock detect”. 4.1 Analog Lock Detect In analog lock detect, the phase detector output comes from the LD pin. Reference clock PFD clock VCO divide clock Phase detector output LD output Fig. 7 Analog Lock Detect Operation MS1399-E-02 2014/4 - 14 - [AK1542A] 4.2 Digital Lock Detect In the digital lock detect, the [LD] pin outputs is ”Low” every time when the frequency is set. And the [LD] pin outputs “High” (which means the locked state) when a phase error smaller than T is detected for N times consecutively. If the phase error larger than T is detected for N times consecutively when the [LD] pin outputs “High”, the [LD] pin outputs “Low”(which means the unlocked state). The threshold counts for lock detection N could be set by D[18:17]={LDCNTSEL[1:0]} in <Address4>. {LDCNTSEL[1:0]} settings and corresponding counts (N) are as follows: 00: N = 7 01: N = 15 10: N = 31 11: N = 63 The lock detect signal is shown below: Reference clock PFD clock VCO divide clock Phase detector output Invalid Invalid Valid Invalid Valid When “Invalid” is detected consecutively for N times, LD outputs “High” LD output Fig. 8 Digital Lock Detect Operations MS1399-E-02 2014/4 - 15 - [AK1542A] Unlock(LD=”Low” ) Flag=0 No Phase Error < T Yes Flag=Flag+1 No Flag>N Yes Lock(LD=”High”) Fig. 9 Transition Flow Chart: Unlock State to Lock State Lock(LD=”High”) Address2 write Flag=0 No Phase Error > T Yes Flag=Flag+1 No Flag>N Yes Unlock(LD=”Low”) Fig. 10 Transition Flow Chart: Lock State to Unlock State MS1399-E-02 2014/4 - 16 - [AK1542A] 5. Reference Input The reference input could be set to a dividing number in the range of 4 to 16383 using {R[13:0]}, which is a 14-bit address of D[13:0] in <Address3>. A dividing number from 0 to 3 could not be set. 6. Prescaler and Swallow Counter The dual modular prescaler (P/P+1) and the swallow counter are used to provide a large dividing ratio. The prescaler is set by {PRE[1:0]}, which is a 2-bit address of D[15:14] in <Address3>. {PRE[1:0]}=”00”: P=8, dividing ratio = 8/9 {PRE[1:0]}=”01”: P=16, dividing ratio = 16/17 {PRE[1:0]}=”10”: P=32, dividing ratio = 32/33 {PRE[1:0]}=”11”: Prohibited 7. Power Save Mode AK1542A can be operated in the power-down or power-save mode as necessary by using the external control pins [PDN1] and [PDN2]. Power On See “13. Power-up Sequence”. It is necessary to bring [PDN1] to “High” first, then [PDN2]. Bringing [PDN1] and [PDN2] to “High” simultaneously is prohibited. Normal Operation Pin name State PDN1 PDN2 “Low” “Low” Power down “Low” “High” Prohibited “High” “Low” Power save Mode “High” “High” Normal Operation Note 1) and Note 2) Note 1) Register setup can be made 50µs after [PDN1] is set to “High”. The charge pump is in the Hi-Z state. Note 2) Register settings are maintained when [PDN2] is set to “Low” during normal operation. MS1399-E-02 2014/4 - 17 - [AK1542A] 9. Register Map Name Data Address A/B 0 0 0 1 CP 0 0 1 0 0 0 1 1 Function 0 1 0 0 GPO 0 1 0 1 D19 to D0 Ref/Pres A/B D19 D18 D17 0 B [12] B [11] D16 D15 D14 D13 D12 D11 D10 D9 B [10] B [9] B [8] B [7] B [6] B [5] D8 D7 D6 D5 D4 D3 D2 D1 D0 Address B [4] B [3] B [2] B [1] B [0] A [5] A [4] A [3] A [2] A [1] A [0] 0x01 CP2 [2] CP2 [1] CP2 [0] 0 0 CP1 [3] CP1 [2] CP1 [1] CP1 [0] 0x02 R [8] R [7] R [6] R [5] R [4] R [3] R [2] R [1] R [0] 0x03 CP 0 0 0 0 0 0 0 0 0 0 CP2 [3] Ref/Pres 0 0 0 0 PRE [1] PRE [0] R [13] R [12] R [11] R [10] R [9] Function 0 LDCNT SEL[1] LDCNT SEL[0] FAST EN CP HiZ CP POLA LD GPO 0 0 0 0 0 0 0 FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 0 0 MS1399-E-02 0 0 0 0 0 0 0 0 GPO 2 GPO 1 0x04 0x05 2014/4 - 18 - [AK1542A] Notes for writing into registers (1) The data at addresses 0x02 and 0x03 are committed to all related circuits when address 0x01 is written, which means that the data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at the same time. (2) Addresses 0x04 and 0x05 could be written individually from other addresses. (3) The initial register values are not defined. Therefore, even after [PDN1] is turned ON, each bit value remains undefined. In order to set all register values, it is required to write the data in all addresses of the register. ○ Examples of writing into registers (Ex. 1) Power-On ⇒Writing these three-word data is required. (1) Write a charge pump current value to address 0x02. The data at address 0x02 is not committed to all related circuits at this time. Instead, it is stored in the on-chip buffer. (2) Write a division number for the prescaler and a reference counter value to address 0x03. The data at the address 0x03 is not committed to all related circuits at this time. Instead, it is stored in the on-chip buffer. (3) Write values for A counter and B counter at the address 0x01. The data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at this time. (Ex. 2) Changing frequency settings (1) Write values for A counter and B counter at the address 0x01. The data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at a time. The last data written into addresses 0x02 and 0x03 are committed. (Ex. 3) Changing charge pump current ⇒Writing these two-word data is required. (1) Write a charge pump current value at the address 0x02. The data in address 0x02 is not committed to all related circuits at this time. Instead, it is stored in the on-chip buffer. (2) Write values for A counter and B counter at the address 0x01. The data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at a time. The last data written into address 0x03 is committed. (Ex. 4) Changing reference dividing number ⇒Writing these two-word data is required. (1) Write a division number for the prescaler and a reference counter value at the address 0x03. The data at the address 0x03 is not committed to all related circuits at this time. Instead, it is stored in the on-chip buffer. (2) Write values for A counter and B counter at the address 0x01. The data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at a time. The last data written into address 0x03 is committed. MS1399-E-02 2014/4 - 19 - [AK1542A] 10. Register Function Description < Address1 : A/B > D19 D[18:6] D[5:0] Address 0 B[12:0] A[5:0] 0001 B[12:0]: B (Programmable) counters value D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Function Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Dec Prohibited 0 0 0 0 0 0 0 0 0 0 0 1 0 2 Dec Prohibited 0 0 0 0 0 0 0 0 0 0 0 1 1 3 Dec DATA 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 Dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 Dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 Dec A[5:0]: A (Swallow) counter value D5 D4 D3 D2 D1 D0 Function 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Dec 0 0 0 0 1 0 2 Dec 0 0 0 0 1 1 3 Dec Remarks DATA 1 1 1 1 0 1 61 Dec 1 1 1 1 1 0 62 Dec 1 1 1 1 1 1 63 Dec MS1399-E-02 2014/4 - 20 - [AK1542A] * Requirements for A[5:0] and B[12:0] The data at A[5:0] and B[12:0] must meet the following requirements: B[12:0] ≥ 3, B[12:0] ≥ A[5:0] See “1. Frequency Setup” on Page 11 for details of the relationship between a frequency division number and the data at A[5:0] and B[12:0]. < Address2 : CP > D19 D18 D17 D16 D15 D14 D13 D12 D[11:10] D[9:6] D[5:4] D[3:0] Address 0 0 0 0 0 0 0 0 0 CP2[3:0] 0 CP1[3:0] 0010 CP1[3:0] : Charge pump current for normal operation CP2[3:0] : Charge pump current for Fast Lock Up mode In AK1542A, two types of charge pump current CP1 and CP2 could be set. CP1 is the charge pump current setting for normal operation. CP2 is the charge pump current setting for Fast Lock Up mode. The following formula shows the relationship between the resistance value, the register setting and the electric current value. Setting 0~7; Charge pump minimum current (Icp_min) [A] = 8.55 / Resistance connected to the [BIAS] pin (Ω) Charge pump current [A] = Icp_min [A] × (CP1 or CP2 + 1) Setting 8; Charge pump current [A] = Icp_min [A] × 0.5 CP1[3:0] Charge pump currents [µA] CP2[3:0] 22kΩ 27kΩ 33kΩ 000 388 316 259 001 776 632 518 010 1164 948 777 011 1552 1264 1036 100 1940 1580 1295 101 2328 1896 1554 110 2716 2212 1813 111 3104 2528 2072 1XXX 194 158 129 MS1399-E-02 2014/4 - 21 - [AK1542A] < Address3 : Ref/Pres > D19 D18 D17 D16 D[15:14] D[13:0] Address 0 0 0 0 PRE[1:0] R[13:0] 0011 PRE[1:0] : Prescaler division ratio (8/9, 16/17, 32/33) The following settings can be chosen for the prescaler division. D15 D14 Function 0 0 8/9 (P=8) 0 1 16/17 (P=16) 1 0 32/33 (P=32) 1 1 Prohibited Remarks R[13:0]: Reference clock division number The following settings can be chosen for the reference clock division. The allowed range is 4 (1/4 division) to 16383 (1/16383 division). 0 to 3 cannot be set. D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Prohibited 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/1 division Prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1/2 division Prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1/3 division Prohibited 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1/4 division 1/16381 division 1/16382 division 1/16383 division DATA 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MS1399-E-02 2014/4 - 22 - [AK1542A] < Address4 : Function > D19 D18 D17 D16 D15 D14 D13 D[12:0] Address 0 LDCNT SEL[1] LDCNT SEL[0] FAST EN CP HiZ CP POLA LD FAST[12:0] 0100 LDCNTSEL[1:0] : Counter value for lock detect The counter value for digital lock detect can be set. D18 D17 Function 0 0 Counter value = 7 0 1 Counter value = 15 1 0 Counter value = 31 1 1 Counter value = 63 Remarks FASTEN : The Fast Lock Up mode enable/disable setting The Fast Lock Up mode can be enabled or disabled. D16 Function Remarks 0 The data in CP2[3:0] and FAST[12:0] are disabled. 1 The data in CP2[3:0] and FAST[12:0] are enabled. CPHIZ: TRI-STATE output setting for charge pumps 1 and 2 D15 Function Remarks 0 Charge pump is activated. Use this setting for normal operation. 1 TRI-STATE Note 1) Note 1) The charge pump output is turned OFF and put in the Hi-Z state. MS1399-E-02 2014/4 - 23 - [AK1542A] CPPOLA: Selects positive or negative output polarity for CP1 and CP2. D14 Function 0 Positive 1 Negative Remarks High VCO frequency Positive Negative Low Low Charge pump output voltage High Fig. 11 Charge Pump Output Polarity LD: Selects analog or digital for Lock Detect. D13 Function 0 Digital lock detect mode 1 Analog lock detect mode Remarks For detailed functional descriptions, see the section “Lock Detect (LD) Signal” in “8. Block Functional Description”. MS1399-E-02 2014/4 - 24 - [AK1542A] FAST[12:0] : FAST counter value A decimal number from 1 to 8191 can be set. This value determines the time period during which the CP2 is ON for the Fast Lock Up mode. After the time period calculated by [phase detector frequency cycle × {FAST[12:0]} setting], the CP2 is turned OFF. 0 could not be set. D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Dec 0 0 0 0 0 0 0 0 0 0 0 1 0 2 Dec DATA 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 Dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 Dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 Dec MS1399-E-02 2014/4 - 25 - [AK1542A] < Address5 : GPO > D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPO2 GPO1 0101 GPO2: The state of the GPO2 pin This value controls the General-Purpose output pin GPO2. The voltage applied to the PVDD pin determines the “High” level output. D1 Function Remarks 0 “Low” output from the GPO2 pin 1 “High” output from the GPO2 pin GPO1: The state of the GPO1 pin This value controls the General-Purpose output pin GPO1. The voltage applied to the PVDD pin determines the “High” level output. D0 Function Remarks 0 “Low” output from the GPO1 pin 1 “High” output from the GPO1 pin MS1399-E-02 2014/4 - 26 - [AK1542A] 11. IC Interface Schematic No. Name I/O R0(Ω) 4 LE I 300 5 DATA I 300 6 CLK I 300 8 PDN2 I 300 9 PDN1 I 300 2 TEST3 I 300 3 TEST1 I 300 11 TEST2 I 300 Cur(µA) Function Digital input pins R0 Digital input pins Pull-Down R0 100k 7 LD O 12 GPO1 O 13 GPO2 O 10 REFIN I Digital output pin 300 Analog input pin R0 15 VREF IO 300 19 BIAS IO 300 22 CPZ IO 300 Analog I/O pin R0 MS1399-E-02 2014/4 - 27 - [AK1542A] No. Name I/O 23 SWIN I Analog input pin 21 CP O Analog output pin 16 RFINN I 12k 20 17 RFINP I 12k 20 R0(Ω) Cur(µA) Function Analog input pin(RF signal input) R0 MS1399-E-02 2014/4 - 28 - [AK1542A] 12. Recommended Schematic for Off-Chip Component 1. PVDD, CPVDD LSI PVDD 0.01F 100pF 10F CPVDD 0.01F 100pF 10F 2. VREF LSI VREF 220nF±10% VREF2 3. TEST [1,2,3] LSI TEST1,2,3 MS1399-E-02 2014/4 - 29 - [AK1542A] 4. REFIN LSI REFIN 100pF±10% 5. RFINP, RFINN LSI VCO Output RFINP 51Ω 100pF±10% RFINN 100pF±10% 6. BIAS LSI BIAS 22kΩ~33kΩ MS1399-E-02 2014/4 - 30 - [AK1542A] 13. Power-up Sequence 1. Power-up Sequence (Recommended) PVDD,CPVDD T> 0 PDN1 50s On-chip LDO 1.8V 0V (1.8V) Refin Don’t care Registers can be written input Internal resiter values are set Write the data in all Write to the register addresses of the register PDN2(PLL) HiZ CP Output Fig. 12 Recommended Power Sequence Note 1) The initial register values are not defined. Therefore, even after [PDN1] is set to “High”, each bit value remains undefined. In order to set all register values, it is required to write the data in all addresses of the register. MS1399-E-02 2014/4 - 31 - [AK1542A] 2. Power-up Sequence PVDD,CPVDD PDN1 50s 1.8V On-chip LDO 0V (1.8V) Refin must be input before setting [PDN2] to “High” Refin Write to register Don’t care input H or L Registers can be written After more than 50s from the [PDN1] is set to “High” Here [PDN1] is set to “High” after or at the same time as power-up. PDN2(PLL) HiZ CP Output(*1) *1 CP output is not defined before writing the data in all addresses of the register. After writing them, CP output can be controlled by register. Fig. 13 Power Sequence MS1399-E-02 2014/4 - 32 - [AK1542A] 14. Typical Evaluation Board Schematic RFOUT AK1542A Loop Filter 100pF REFIN CP 18 100pF R3 VCO C1 R2' R2 C3 18 18 VREF 220nF SWIN C2 CPZ BIAS 27k RFINP 100pF 51 RFINN 100pF Fig. 14 Typical Evaluation Board Schematic Note 1) The [CPZ] pin should be connected to the R2 and C2, which are intermediate nodes, even if the Fast Lock Up is not used. Therefore, R2 must be connected to the [CP] pin, while C2 must be connected to the ground. Note 2) In Fast Lock Up mode, R2 and R2’ are connected in parallel by internal switching. For calculation of loop band width and phase margin at Fast Lock Up mode, the resistance should be considered as parallel of R2 and R2’. Note 3) It is recommended that the exposed pad at the center of the backside should be connected to the ground. Note 4) Test pins (TEST1 to 3) should be connected to the ground. MS1399-E-02 2014/4 - 33 - [AK1542A] CPVSS CPVDD PVDD PVSS VREF DVSS 15. Block Diagram by Power Supply LDO BIAS R COUNTER 14 bit REFIN CP CHARGE PUMP PHASE FREQENCY DETECTOR CLK CPZ REGISTER 24 bit DATA LE FAST COUNTER LOCK DETECT SWALLOW COUNTER 6 bit PROGRAMABLE COUNTER 13 bit SWIN N DIVIDER CPVDD GPO2 PVDD GPO1 8/9, 16/17, 32/33 PDN2 - PDN1 RFINN LD TEST3 PRESCALER TEST2 + TEST1 RFINP Fig. 15 Power Supply Block Diagram MS1399-E-02 2014/4 - 34 - [AK1542A] 16. Outer Dimensions 4.00±0.07 2.40 18 12 19 7 24 B 1 6 C0.30 2.00 0.05 M S A B 0.22±0.05 0.75MAX 0.12~0.18 0.17~0.27 0.00~0.05 0.05 S 0.70 0.5 0.05MAX S Part A 0.40±0.07 2.40 A 2.00 4.00±0.07 13 Detailed chart in part A Fig. 16 Package Outer Dimensions Note) It is recommended to connect the exposed pad at the center of the backside to the ground, although it will not make any impact on the electrical characteristics if it is open. MS1399-E-02 2014/4 - 35 - [AK1542A] 17. Marking (a) Style : QFN (b) Number of pins : 24 (c) 1 pin marking: : ○ (d) Product number : 1542A (e) Date code : YWWL (4 digits) Y : Lower 1 digit of calendar year (Year 2012 → 2, 2013 → 3 ...) WW : Week L : Lot identification, given to each product lot which is made in a week LOT ID is given in alphabetical order (A, B, C…). 1542A YWWL (d) (e) (c) Fig. 17 Marking MS1399-E-02 2014/4 - 36 - [AK1542A] IMPORTANT NOTICE 0. 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MS1399-E-02 2014/4 - 37 - Related Parts Part# Discription Comments Mixer AK1220 100MHz~900MHz High Linearity Down Conversion Mixer IIP3:+22dBm AK1222 100MHz~900MHz Low Power Down Conversion Mixer IDD:2.9mA AK1224 100MHz~900MHz NF:8.5dB, IIP3:+18dBm AK1228 10MHz~2GHz Up/Down Conversion Mixer 3V Supply, NF:8.5dB AK1221 0.7GHz~3.5GHz IIP3:+25dBm AK1223 3GHz~8.5GHz High Linearity Down Conversion Mixer Low Noise, High Liniarity Down Conversion Mixer High Linearity Down Conversion Mixer IIP3:+13dB, NF:15dB PLL Synthesizer AK1541 20MHz~600MHz Low Power Fractional-N Synthesizer IDD:4.6mA AK1542A 20MHz~600MHz Low Power Integer-N Synthesizer IDD:2.2mA AK1543 400MHz~1.3GHz Low Power Fractional-N Synthesizer IDD:5.1mA AK1544 400MHz~1.3GHz Low Power Integer-N Synthesizer IDD:2.8mA AK1590 60MHz~1GHz Fractional-N Synthesizer IDD:2.5mA AK1545 0.5GHz~3.5GHz Integer-N Synthesizer 16-TSSOP AK1546 0.5GHz~3GHz Low Phase Noise Integer-N Synthesizer Normalized C/N:-226dBc/Hz AK1547 0.5GHz~4GHz Integer-N Synthesizer 5V Supply AK1548 1GHz~8GHz Low Phase Noise Integer-N Synthesizer Normalized C/N:-226dBc/Hz 100~300MHz Analog Signal Control IF VGA w/ RSSI Dynamic Range:30dB IFVGA AK1291 integrated VCO AK1572 690MHz~4GHz Down Conversion Mixer with Frac.-N PLL and VCO IIP3:24dBm, -111dBc/Hz@100kHz AK1575 690MHz~4GHz Up Conversion Mixer with Frac.-N PLL and VCO IIP3:24dBm, -111dBc/Hz@100kHz IF Reciever (2nd Mixer + IF BPF + FM Detector) AK2364 Built-in programmable AGC+BPF, FM detector IC IFBPF:10kHz ~ 4.5kHz AK2365A Built-in programmable AGC+BPF, IFIC IFBPF:7.5kHz ~ 2kHz Analog BB for PMR/LMR AK2345C CTCSS Filter, Encoder, Decoder 24-VSOP AK2360/ AK2360A Inverted frequency(3.376kHz/3.020kHz) scrambler 8-SON AK2363 MSK Modem/DTMF Receiver 24-QFN AK2346B 0.3-2.55/3.0kHz Analog audio filter, Emphasis, Compandor, scrambler, MSK Modem 24-VSOP 0.3-2.55/3.0kHz Analog audio filter Emphasis, Compandor, scrambler, CTCSS filter 24-VSOP AK2346A AK2347B AK2347A 24-QFN 24-QFN Function IC AK2330 8-bit 8ch Electronic Volume VREF can be selected for each channel AK2331 8-bit 4ch Electronic Volume VREF can be selected for each channel Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document, please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 2014/10