AK8185A

AK8185A
Low - Jitter Clock Generator with
Integrated VCO
AK8185A
-Preliminary- Features -
- Description -
Low Phase Noise PLL
RMS jitter 0.4ps typ. (12kHz to 20MHz)
On chip VCO
4x Output Available
Pin-Selectable
LVPECL, LVDS, or 2-LVCMOS
LVCMOS Bypass Output Available
AK8185A is a Low – Jitter Clock Generator with
sub pico-second jitter performance.
Also Low power consumption is the advantage
for advanced optimized application.
- Application Ethernet
SONET
Fibre Channel
SAN
Cost-Effective High-Frequency Crystal Oscillator
Replacement
3.3V for Core
Operating Temperature Range: -40 to +85℃
Pin Package: 5mm x 5mm
32-pin Leadless QFN (Pb-free)
- Block Diagram Vcc_IN
Vcc_PLL1 Vcc_PLL2
Vcc_VCO
Vcc_VDD
Vcc_OUT
Input Frequency Range:
21.875MHz-28.47MHz
XIN
LVCMOS
Phase
Frequency
Detector
XO /
LVCMOS
Charge
Pump
+15
+3
Loop
Filter
Output Frequency Range:
43.75MHz-683.264MHz
LVPECL
LVCMOS
LVDS
+1
.
.
.
LVPECL
LVCMOS
LVDS
+20
VCO
+4
+4
+5
+6
LVPECL
LVCMOS
LVDS
+24
+25
Prescaler
Divider
Feedback
Divider
LVPECL
LVCMOS
LVDS
+8
Output
Divider
RSTN
PR[1...0]
Output
Driver
OD[2...0]
OS[1...0]
Fig. 1
draft-E-02
Dec. 2012
-1-
AK8185A
- Pin Assignments -
PR1
PR0
26
25
27 VCC_OUT
28 OUTN3
OUTP3
29
30 VCC_OUT
31 OUTN2
32
OUTP2
(Top view)
VCC_OUT 1
OUTN1
2
OUTP1
3
24
NC
23 OSC_OUT
AK8185A
VCC_OUT 4
22
GND1
21
XIN
OUTN0
5
OUTP0
6
19 REG_CAP1
CE
7
18 VCC_PLL1
NC
8
17 REG_CAP2
20 VCC_IN
14
15
OD1
OD2
VCC_PLL2 16
13
OD0
11
OS0
12
10
OS1
RSTN
9
VCC_VCO
Thermal Pad
(must be soldered to ground)
Fig. 2
draft-E-02
Dec. 2012
-2-
AK8185A
- Pin Descriptions Pin No.
Pin Name
Pin
Type
Description
1
VCC_OUT
PWR
3.3V Power Supply for output buffers
2
OUTN1
OUT
Differential output pair or two single-ended outputs
3
OUTP1
OUT
Differential output pair or two single-ended outputs
4
VCC_OUT
PWR
3.3V Power Supply for output buffers
5
OUTN0
OUT
Differential output pair or two single-ended outputs
6
OUTP0
OUT
Differential output pair or two single-ended outputs
7
CE
IN
8
NC
Chip enable control pin
No Connection
9
VCC_VCO
PWR
10
OS1
IN
Output type select control pin
3.3V Power Supply for internal VCO
11
OS0
IN
Output type select control pin
12
RSTN
IN
Device reset (active low)
13
OD0
IN
Output divider control pins
14
OD1
IN
Output divider control pins
Output divider control pins
15
OD2
IN
16
VCC_PLL2
PWR
3.3V Power Supply for PLL circuitry
17
REG_CAP2
OUT
Capacitor for internal regulator (connect to a 10-μF Y5V capacitor
to GND)
18
VCC_PLL1
PWR
3.3V Power Supply for PLL circuitry
19
REG_CAP1
OUT
Capacitor for internal regulator (connect to a 10-μF Y5V capacitor
to GND)
20
VCC_IN
PWR
3.3V Power Supply for input buffers
21
XIN
IN
22
GND1
Ground
23
OSC_OUT
OUT
24
NC
25
PR0
Parallel resonant crystal or LVCMOS inputs
Additional ground for device
Bypass LVCMOS output
No Connection
IN
Prescaler and Feedback divider control pins
Prescaler and Feedback divider control pins
26
PR1
IN
27
VCC_OUT
PWR
3.3V Power Supply for output buffers
28
OUTN3
OUT
Differential output pair or two single-ended outputs
29
OUTP3
OUT
Differential output pair or two single-ended outputs
30
VCC_OUT
PWR
3.3V Power Supply for output buffers
31
OUTN2
OUT
Differential output pair or two single-ended outputs
32
OUTP2
OUT
Differential output pair or two single-ended outputs
EPAD
GND
Ground
Thermal Pad (Must be soldered to Ground)
draft-E-02
Dec. 2012
-3-
AK8185A
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted (1)
Parameter
Value
Supply voltage range
Unit
-0.3 to 4.3V
V
(Vｃｃ_out, Vcc_PLL1 ,Vcc_PLL2, Vcc_VCO , Vcc_IN )
Input voltage range
GND-0.3 to VCC+0.3
V
Input current range
-10 to +10
mA
Storage temperature
-55to 125
C
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Output supply voltage
Vｃｃ_out
3.0
3.3
3.6
V
PLL supply voltage
Vcc_PLL1
3.0
3.3
3.6
V
PLL supply voltage
Vcc_PLL2
3.0
3.3
3.6
V
On-chip VCO supply voltage
Vcc_VCO
3.0
3.3
3.6
V
Input supply voltage
Vcc_IN
3.0
3.3
3.6
V
Ambient temperature
Ta
-40
85
C
draft-E-02
Dec. 2012
-4-
AK8185A
Electrical Characteristics
All specifications at VDD=VDD_LVDS=VCP= 3.3V5%,
Parameter
Ta: -40 to +85℃, unless otherwise noted
Conditions
MIN
TYP
MAX
Unit
Control Pin LVCMOS Input Characteristics
Input high voltage (VIH)
0.6Vcc
V
Input low voltage (VIL)
0.4Vcc
V
Input high current (IIH)
200
uA
Input low current (IIL)
-200
uA
LVCMOS Output Characteristics
Bypass output frequency
21.875
28.47
MHz
Output frequency
43.75
250
MHz
Output high voltage
Vcc-0.5
V
Output low voltage
0.3
RMS phase jitter
250MHZ (10kHz to 20MHz)
Output rise/fall slew rate
20% ⇔ 80%
0.4
ps, RMS
2.4
Output duty cycle
45
Skew between outputs
55
10
%
ps
LVPECL Output Characteristics
Output frequency
43.75
683.264
MHz
Output high voltage
Vcc-1.18
Vcc-0.73
V
Output low voltage
Vcc-2
Vcc-1.55
V
Differential output voltage
0.6
RMS phase jitter
625MHZ (10kHz to 20MHz)
Output rise/fall slew rate
20% ⇔ 80%
Output duty cycle
1.23
0.4
45
Skew between outputs
V
ps, RMS
175
ps
55
%
10
ps
LVDS Output Characteristics
Output frequency
43.75
683.264
MHz
Differential output voltage
0.247
0.454
V
50
mV
1.375
V
50
mV
Magnitude change
Common-mode voltage
1.125
Magnitude change
RMS phase jitter
625MHZ (10kHz to 20MHz)
Output rise/fall time
20% ⇔ 80%
Output duty cycle
0.4
45
Skew between outputs
10
draft-E-02
ps, RMS
255
ps
55
%
ps
Dec. 2012
-5-
AK8185A
Typical Output Phase Noise Characteristics
All specifications at VDD=VDD_LVDS=VCP= 3.3V5%,
Parameter
Conditions
Ta: -40 to +85℃, unless otherwise noted
MIN
TYP
MAX
Unit
250MHz LVCMOS Input Characteristics
Phase Noise @ 100Hz offset
-85
dBc/Hz
@ 1kHz offset
-113
dBc/Hz
@ 10kHz offset
-123
dBc/Hz
@ 100kHz offset
-125
dBc/Hz
@ 1MHz offset
-136
dBc/Hz
@ 10MHz offset
-154
dBc/Hz
@ 20MHz offset
-154
dBc/Hz
384
ps, RMS
-77
dBc/Hz
@ 1kHz offset
-105
dBc/Hz
@ 10kHz offset
-114
dBc/Hz
@ 100kHz offset
-117
dBc/Hz
@ 1MHz offset
-128
dBc/Hz
@ 10MHz offset
-150
dBc/Hz
@ 20MHz offset
-151
dBc/Hz
387
ps, RMS
-77
dBc/Hz
@ 1kHz offset
-105
dBc/Hz
@ 10kHz offset
-114
dBc/Hz
@ 100kHz offset
-117
dBc/Hz
@ 1MHz offset
-127
dBc/Hz
@ 10MHz offset
-150
dBc/Hz
@ 20MHz offset
-152
dBc/Hz
395
ps, RMS
RMS Phase Jitter
10kHz to 20MHz
625MHz LVPECL Output Characteristics
Phase Noise @ 100Hz offset
RMS Phase Jitter
10kHz to 20MHz
625MHz LVDS Output Characteristics
Phase Noise @ 100Hz offset
RMS Phase Jitter
10kHz to 20MHz
draft-E-02
Dec. 2012
-6-
AK8185A
Crystal Characteristics
Parameter
MIN
Frequency
TYP
21.875
Equivalent series resistance
On-chip load capacitance
8
Drive level
0.1
Maximum shunt capacitance
draft-E-02
MAX
Unit
28.47
MHz
50
Ω
10
pF
1
mW
7
pF
Dec. 2012
-7-
AK8185A
Device Configuration Common Configuration Output Divider
20 24 24 25 24 24 20 24 VCO Frequency
[MHz] 2000 1782 1800 1866.24 1800 1912.5 2000 1800 25 25 24 15 24 24 20 25 25 25 25 1866.24 1875 1912.5 1875 1800 1912.5 2000 1866.24 1875 1866.24 1875 Input [MHz] Prescaler Divider Feedback Divider 25 24.75 25 24.8832 25 26.5625 25 25 4 3 3 3 3 3 4 3 24.8832 25 26.5625 25 25 26.5625 25 24.8832 25 24.8832 25 3 3 3 5 3 3 4 3 3 3 3 8 8 8 8 6 6 4 4 Output Frequency [MHz] 62.5 74.25 75 77.76 100 106.25 125 150 GigE HDTV SATA SONET PCI Express Fiber Channel GigE SATA 4 4 4 2 3 3 2 2 2 1 1 155.52 156.25 159.375 187.5 200 212.5 250 311.04 312.5 622.08 625 SONET 10 GigE 10‐G Fiber Channel
12 GigE PCI Express 4‐G Fiber Channel GigE SONET XGMII SONET 10 GigE Application draft-E-02
Dec. 2012
-8-
AK8185A
Generic Configuration
Input Frequency
Range
[MHz]
Prescaler
Divider
Output
Divider
Output Frequency
[MHz]
21.875 to 25.62 4 20 1750 to 2050 54.6875 to 64.05 1750 to 2050
8 6 21.875 to 25.62 4 20
21.875 to 25.62 4 20
1750 to 2050
4 109.375 to 128.1 21.875 to 25.62 4 20
1750 to 2050
3 145.84 to 170.8 21.875 to 25.62 4 20
1750 to 2050
2 218.75 to 256.2 21.875 to 25.62 23.33 to 27.33 4 3 20
25 1750 to 2050
1 437.5 to 512.4 1750 to 2050
8 72.906 to 85.408 23.33 to 27.33 3 25
1750 to 2050
6 97.21 to 113.875 23.33 to 27.33 3 25
1750 to 2050
4 145.821 to 170.816 23.33 to 27.33 3 25
1750 to 2050
3 194.42 to 227.75 23.33 to 27.33 3 25
1750 to 2050
2 291.624 to 341.632 23.33 to 27.33 3 1750 to 2050
1 583.248 to 683.264 23.33 to 27.33 5 25
15 1750 to 2050
8 43.75 to 51.25 23.33 to 27.33 5 15
1750 to 2050
6 58.33 to 68.33 23.33 to 27.33 5
15
1750 to 2050
4 87.5 to 102.5 23.33 to 27.33 5
15
1750 to 2050
3 116.66 to 136.66 23.33 to 27.33 5
15
1750 to 2050
2 175 to 205 23.33 to 27.33 24.305 to 28.47 5
3 15
24 1750 to 2050
1 350 to 410 1750 to 2050
8 72.915 to 85.41 24.305 to 28.47 3 24
1750 to 2050
6 97.22 to 113.88 24.305 to 28.47 24.305 to 28.47 3 1750 to 2050
4 145.83 to 170.82 3 24
24 1750 to 2050
3 194.44 to 227.76 24.305 to 28.47 3 24
1750 to 2050
2 291.66 to 341.64 24.305 to 28.47 3 24
1750 to 2050
1 583.32 to 683.28 Feedback VCO Frequency
Divider
[MHz]
72.92 to 85.4 Programmable Prescaler and Feedback Divider Settings
Control Inputs
Prescaler
Divider
Feedback
Divider
PFD Frequency
PR1 PR0 Minimum Maximum 0 0 3 24 28.47 0 1 5
15
24.305 23.33 27.33 1 0 3
25
23.33 27.33 1 1 4
20
21.875 25.62 draft-E-02
Dec. 2012
-9-
AK8185A
Programmable Output Divider Settings
Control Inputs Output Divider
OD2 OD1 OD0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 0 4 1 1 0 Reserved 1 0 1 6 1 1 0 Reserved 1 1 1 8 Programmable Output Type
Control Inputs Output Type OS1 OS0 0 0 LVCMOS, OSC_OUT Off
0 1 LVDS, OSC_OUT Off 1 0 LVPECL, OSC_OUT Off 1 1 LVPECL, OSC_OUT On Output Enable
Control Inputs Operating Condition
Output 0 Power Down Hi‐Z 1 Normal Active CE Reset
Control Inputs Operating Condition
_____
RSTN 0 0 1 1 Output Device Reset Hi‐Z PLL Recalibration Hi‐Z Normal Active draft-E-02
Dec. 2012
- 10 -
AK8185A
Package Information
 Mechanical data
 RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
draft-E-02
Dec. 2012
- 11 -
AK8185A
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
 AKM assumes no liability for infringement of any patent, intellectual property, or other rights in
the application or use of any information contained herein.
 Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export
pertaining to customs and tariffs, currency exchange, or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of
the device or system containing it, and which must therefore meet very high standards of
performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other
fields, in which its failure to function or perform may reasonably be expected to result in loss
of life or in significant injury or damage to person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of,
or otherwise places the product with a third party, to notify such third party in advance of the
above content and conditions, and the buyer or distributor agrees to assume any and all
responsibility and liability for and hold AKM harmless from any and all claims arising from the
use of said product in the absence of such notification.
draft-E-02
Dec. 2012
- 12 -