TI CDCLVD2104

CDCLVD2104
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SCAS903A – JUNE 2010 – REVISED AUGUST 2010
Dual 1:4 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD2104
FEATURES
1
•
•
•
•
•
•
•
•
•
•
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Dual 1:4 Differential Buffer
Low Additive Jitter <300 fs, RMS in
10 kHz to 20 MHz
Low Within Bank Output Skew of 35ps (Max)
Universal Inputs Accept LVDS, LVPECL,
LVCMOS
One Input Dedicated for Four Output Buffers
8 LVDS Outputs, ANSI EIA/TIA-644A Standard
Compatible
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 5mm × 5mm 28-Pin QFN (RHD)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
•
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•
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DESCRIPTION
The CDCLVD2104 clock buffer distributes two clock
inputs (IN0, IN1) to a total of 8 pairs of differential
LVDS clock outputs (OUT0, OUT7). Each buffer block
consists of one input and 4 LVDS outputs. The inputs
can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2104 is specifically designed for driving
50-Ω transmission lines. If the input is in single ended
mode, the appropriate bias voltage (VAC_REF) should
be applied to the unused negative input pin.
Using the control pin (EN), outputs can be either
disabled or enabled. If the EN pin is left open two
buffers with all outputs are enabled, if switched to a
logical "0" both buffers with all outputs are disabled
(static logical “0”), if switched to a logical "1", one
buffer with four outputs is disabled and another buffer
with four outputs is enabled. The part supports a fail
safe function. It incorporates an input hysteresis,
which prevents random oscillation of the outputs in
absence of an input signal.
The device operates in 2.5V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD2104 is packaged in
small 28-pin, 5-mm × 5-mm QFN package.
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
Wireless Communications
General Purpose Clocking
200 MHz
PHY
DAC4
Clock
Generator
EN
CDCLVD2104
100 MHz
PHY
ADC4
Figure 1. Application Example
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CDCLVD2104
SCAS903A – JUNE 2010 – REVISED AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
VCC
VAC_REF0
VCC
VCC
Reference
Generator
VAC_REF1
INP0
OUTP [0..3]
LVDS
INN0
OUTN [0..3]
INP1
OUTP [4..7]
LVDS
INN1
OUTN [4..7]
VCC
200 kW
EN
200 kW
GND
GND
Figure 2. CDCLVD2104 Block Diagram
OUTP4
2
OUTN3
OUTP3
OUTN2
OUTP2
OUTN1
OUTP1
VCC
TOP VIEW
21
20
19
18
17
16
15
22
5mm x 5mm
28 pin QFN
14
GND
13
OUTN0
OUTN4
23
OUTP5
24
12
OUTP0
OUTN5
25
11
VAC_REF0
OUTP6
26
10
INN0
OUTN6
27
9
INP0
VCC
28
8
VCC
1
2
3
4
5
6
7
GND
OUTP7
OUTN7
EN
INP1
INN1
VAC_REF 1
Thermal Pad
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PIN FUNCTIONS
PIN
NAME
TYPE
DESCRIPTION
NO.
VCC
8,15,28
Power
2.5V supplies for the device
GND
1,14
Ground
Device ground
INP0, INN0
9,10
Input
Differential input pair or single ended input
INP1, INN1
5,6
Input
Differential redundant input pair or single ended input
OUTP0, OUTN0
12,13
Output
Differential LVDS output pair no. 0
OUTP1, OUTN1
16,17
Output
Differential LVDS output pair no. 1
OUTP2, OUTN2
18,19
Output
Differential LVDS output pair no. 2
OUTP3, OUTN3
20,21
Output
Differential LVDS output pair no. 3
OUTP4, OUTN4
22,23
Output
Differential LVDS output pair no. 4
OUTP5, OUTN5
24,25
Output
Differential LVDS output pair no. 5
OUTP6, OUTN6
26,27
Output
Differential LVDS output pair no. 6
OUTP7, OUTN7
2,3
Output
Differential LVDS output pair no. 7
VAC_REF0
11
Output
Bias voltage output for capacitive coupled inputs. If used, it is recommended to
use a 0.1µF to GND on this pin.
VAC_REF1
7
Output
Bias voltage output for capacitive coupled inputs. If used, it is recommended to
use a 0.1µF to GND on this pin.
EN
4
Input with an internal
200kΩ pull-up and
pull-down
Thermal Pad
INP0/INN0 is the input
INP1/INN1 is the input
Control pin – enables or disables the outputs, (See Table 1)
See thermal management recommendations
Table 1. Output Control Table
EN
CLOCK OUTPUTS
0
All outputs disabled (static "0")
OPEN
All outputs enabled
1
OUT0, OUT3 enabled and OUT4, OUT7 disabled (static "0")
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE / UNIT
VCC
Supply voltage range
VI
Input voltage range
–0.2 to (VCC + 0.2) V
VO
Output voltage range
–0.2 to (VCC + 0.2) V
IOSD
Driver short circuit current
ESD
Electrostatic discharge (HBM, 1.5 kΩ, 100 pF)
(1)
(2)
–0.3 to 2.8 V
See Note
(2)
>3000 V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
The outputs can handle permanent short.
RECOMMENDED OPERATING CONDITIONS
VCC
Device supply voltage
TA
Ambient temperature
MIN
TYP
MAX
2.375
2.5
2.625
V
85
°C
-40
UNITS
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THERMAL INFORMATION
CDCLVD2104
THERMAL METRIC (1)
QFN
UNITS
28 PINS
qJA
Junction-to-ambient thermal resistance
34
qJC(top)
Junction-to-case(top) thermal resistance
27
qJB
Junction-to-board thermal resistance
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
8
qJC(bottom)
Junction-to-case(bottom) thermal resistance
4
(1)
9
°C/W
0.4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN CONTROL INPUT CHARACTERISTICS
VdI3
3-State
VdIH
Input high voltage
Open
VdIL
Input low voltage
IdIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IdIL
Input low current
VCC = 2.625 V, VIL = 0 V
Rpull(EN)
Input pull-up/ pull-down resistor
0.5×VCC
V
0.7×VCC
V
0.2×VCC
V
30
mA
–30
mA
200
kΩ
2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS
fIN
Input frequency
Vth
Input threshold voltage
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IIL
Input low current
VCC = 2.625 V, VIL = 0 V
ΔV/ΔT
Input edge rate
20% – 80%
CIN
Input capacitance
External threshold voltage applied
to complementary input
200
MHz
1.5
V
Vth + 0.1
VCC
V
0
Vth – 0.1
V
10
mA
1.1
–10
1.5
mA
V/ns
2.5
pF
DIFFERENTIAL INPUT CHARACTERISTICS
fIN
Input frequency
Clock input
VIN,
Differential input voltage
peak-to-peak
VICM = 1.25 V
VICM
Input common-mode voltage range
VIN, DIFF, PP > 0.4V
IIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IIL
Input low current
VCC = 2.625 V, VIL = 0 V
ΔV/ΔT
Input edge rate
20% to 80%
CIN
Input capacitance
4
DIFF
800
MHz
0.3
1.6
VPP
1
VCC – 0.3
V
10
mA
–10
0.75
2.5
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mA
V/ns
pF
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
450
mV
–15
15
mV
1.1
1.375
–15
15
LVDS OUTPUT CHARACTERISTICS
|VOD|
Differential output voltage magnitude
ΔVOD
Change in differential output voltage
magnitude
VOC(SS)
Steady-state common mode output
voltage
ΔVOC(SS)
Steady-state common mode output
voltage
VIN, DIFF, PP = 0.6 V,RL = 100 Ω
Vring
Output overshoot and undershoot
Percentage of output amplitude
VOD
VOS
Output ac common mode
VIN, DIFF, PP = 0.6 V, RL = 100 Ω
IOS
Short-circuit output current
VOD = 0 V
tPD
Propagation delay
VIN, DIFF, PP = 0.3 V
tSK, PP
Part-to-part skew
tSK, O_WB
Within bank output skew
tSK,O_BB
Bank-to-bank output skew
both inputs are phase aligned
tSK,P
Pulse skew(with 50% duty cycle
input)
Crossing-point-to-crossing-point
distortion
tRJIT
Random additive jitter (with 50% duty
cycle input)
Edge speed 0.75V/ns
10 kHz – 20 MHz
tR/tF
Output rise/fall time
20% to 80%,100 Ω, 5 pF
300
ps
ICCSTAT
Static supply current
Outputs unterminated, f = 0 Hz
27
45
mA
ICC100
Supply current
All outputs, RL = 100 Ω,
f = 100 MHz
74
108
mA
ICC800
Supply current
All outputs, RL = 100 Ω,
f = 800 MHz
108
144
mA
1.25
1.35
V
VIN, DIFF, PP = 0.3 V,RL = 100 Ω
V
mV
10%
40
1.5
–50
70
mVPP
±24
mA
2.5
ns
600
ps
35
ps
100
ps
50
ps
0.3 ps, RMS
50
VAC_REF CHARACTERISTICS
VAC_REF
Reference output voltage
VCC = 2.5 V, Iload = 100 µA
1.1
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Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER
MIN
TYP
MAX
UNIT
phn100
Phase noise at 100 Hz offset
-132.9
dBc/Hz
phn1k
Phase noise at 1 kHz offset
-138.8
dBc/Hz
phn10k
Phase noise at 10 kHz offset
-147.4
dBc/Hz
phn100k
Phase noise at 100 kHz offset
-153.6
dBc/Hz
phn1M
Phase noise at 1 MHz offset
-155.2
dBc/Hz
phn10M
Phase noise at 10 MHz offset
-156.2
dBc/Hz
phn20M
Phase noise at 20 MHz offset
-156.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
171
fs, RMS
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER
phn100
Phase noise at 100 Hz offset
phn1k
Phase noise at 1 kHz offset
phn10k
Phase noise at 10 kHz offset
phn100k
MIN
TYP
MAX
UNIT
-80.2
dBc/Hz
-114.3
dBc/Hz
-138
dBc/Hz
Phase noise at 100 kHz offset
-143.9
dBc/Hz
phn1M
Phase noise at 1 MHz offset
-145.2
dBc/Hz
phn10M
Phase noise at 10 MHz offset
-146.5
dBc/Hz
phn20M
Phase noise at 20 MHz offset
-146.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
65
fs, RMS
6
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TYPICAL CHARACTERISTICS
INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES
vs
FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V)
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plot
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TYPICAL CHARACTERISTICS (continued)
Differential Output Voltage
vs
Frequency
VOD − Differential Output Voltage − mV
350
TA = 25oC
340
2.625V
330
320
2.5V
310
300
2.375V
290
280
270
260
250
0
100
200
300
400
500
600
700
800
Frequency − MHz
Figure 4.
8
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TEST CONFIGURATIONS
Oscilloscope
100 W
LVDS
Figure 5. LVDS Output DC Configuration During Device Test
Phase Noise
Analyzer
LVDS
50 W
Figure 6. LVDS Output AC Configuration During Device Test
Figure 7. DC Coupled LVCMOS Input During Device Test
VOH
OUTNx
VOD
OUTPx
VOL
80%
VOUT,DIFF,PP (= 2 x VOD)
20%
0V
tr
tf
Figure 8. Output Voltage and Rise/Fall Time
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INNx
INPx
tPLH0
tPHL0
tPLH1
tPHL1
OUTN0
OUTP0
OUTN1
OUTP1
tPLH2
tPHL2
OUTN2
OUTP2
OUTN7
tPHL7
tPLH7
OUTP7
A.
Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn
or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7).
B.
Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7).
C.
Both inputs (IN0 and IN1) are phase aligned.
Figure 9. Output Skew and Part-to-Part Skew
Vring
OUTNx
VOD
0 V Differential
OUTPx
Figure 10. Output Overshoot and Undershoot
10
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VOS
GND
Figure 11. Output AC Common Mode
APPLICATION INFORMATION
THERMAL MANAGEMENT
For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The Thermal Pad must be
soldered down to ensure adequate heat conduction to of the package. Figure 12 shows a recommended land
and via pattern.
Figure 12. Recommended PCB Layout
POWER-SUPPLY FILTERING
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply
pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply
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and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low dc resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
Board
Supply
Chip
Supply
Ferrite Bead
1 µF
10 µF
0.1 mF (x3)
Figure 13. Power-Supply Decoupling
LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage
different than the output common mode voltage of the CDCLVD2104, ac-coupling should be used. If the LVDS
receiver has internal 100 ohm termination, external termination must be omitted.
Unused outputs can be left open without connecting any trace to the output pins.
Z = 50 W
100 W
CDCLVD2104
LVDS
Z = 50 W
Figure 14. LVDS Output DC Termination
100 nF
Z = 50 W
100 W
CDCLVD2104
LVDS
Z = 50 W
100 nF
Figure 15. LVDS Output AC Termination With Receiver Internally Biased
12
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INPUT TERMINATION
The CDCLVD2104 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.
LVDS Driver can be connected to CDCLVD2104 inputs with dc or ac coupling as shown Figure 16 and
Figure 17, respectively.
Z = 50 W
100 W
LVDS
CDCLVD2104
Z = 50 W
Figure 16. LVDS Clock Driver Connected to CDCLVD2104 Input (AC Coupled)
100 nF
Z = 50 W
LVDS
CDCLVD2104
Z = 50 W
100 nF
50 W
50 W
VAC_REF
Figure 17. LVDS Clock Driver Connected to CDCLVD2104 Input (DC Coupled)
Figure 18 shows how to connect LVPECL inputs to the CDCLVD2104. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP.
75 W
100 nF
Z = 50 W
CDCLVD2104
LVPECL
Z = 50 W
75 W
150 W
150 W
100 nF
50 W
50 W
VAC_REF
Figure 18. LVPECL Clock Driver Connected to CDCLVD2104 Input
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Figure 19 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2104 directly. The series
resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs
to be limited to VIH ≤ VCC.
RS
LVCMOS
(2.5V)
Z = 50 W
CDCLVD2104
V
V
Vth = IH + IL
2
Figure 19. 2.5V LVCMOS Clock Driver Connected to CDCLVD2104 Input
If one of the input buffers is used, the other buffer should be disabled through the EN pin, and unused input pins
should be grounded by 1 kΩ resistors.
Spacer
REVISION HISTORY
Changes from Original (June 2010) to Revision A
•
14
Page
Changed the data sheet from Product Preview to Production ............................................................................................. 1
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PACKAGE OPTION ADDENDUM
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23-Sep-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CDCLVD2104RHDR
ACTIVE
VQFN
RHD
28
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
CDCLVD2104RHDT
ACTIVE
VQFN
RHD
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCLVD2104RHDR
VQFN
RHD
28
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
CDCLVD2104RHDT
VQFN
RHD
28
250
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCLVD2104RHDR
VQFN
RHD
28
3000
338.1
338.1
20.6
CDCLVD2104RHDT
VQFN
RHD
28
250
338.1
338.1
20.6
Pack Materials-Page 2
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