CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms in 10 kHz – 20 MHz Low Within Bank Output Skew of 45 ps (Max) Universal Inputs Accept LVDS, LVPECL, LVCMOS One Input Dedicated for Six Outputs Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible Clock Frequency up to 800 MHz 2.375–2.625 V Device Power Supply LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs Industrial Temperature Range –40°C to 85°C Packaged in 6 mm x 6 mm 40-pin QFN (RHA) ESD Protection Exceeds 3-kV HBM, 1-kV CDM The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal. The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package. spacer APPLICATIONS • • • • • Telecommunications/Networking Medical Imaging Test and Measurement Equipment Wireless Communications General Purpose Clocking 200 MHz Clock Generator EN DESCRIPTION The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS. PHY2 DAC6 CDCLVD2106 100 MHz PHY2 ADC6 Figure 1. Application Example 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated CDCLVD2106 SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. VCC VCC VCC VCC VCC VCC VAC_REF0 Reference Generator VAC_REF1 INP0 OUTP [0..5] LVDS INN0 OUTN [0..5] INP1 OUTP [6..11] LVDS INN1 OUTN [6..11] VCC 200 kW EN 200 kW GND GND 2 VCC 31 GND OUTN7 OUTP7 OUTN6 OUTP6 OUTN5 OUTP5 OUTN4 OUTP4 GND Figure 2. CDCLVD2106 Block Diagram 30 29 28 27 26 25 24 23 22 21 20 VCC 19 OUTN3 18 OUTP3 OUTP8 32 OUTN8 33 OUTP9 34 17 OUTN2 6mm x 6mm 40 pin QFN (RHA) OUTN9 35 16 OUTP2 OUTP10 36 15 OUTN1 OUTN10 37 14 OUTP1 OUTP11 38 13 OUTN0 OUTN11 39 12 OUTP0 VCC 40 11 VCC 5 6 7 8 9 VCC VAC_REF0 INN0 INP0 10 NC 4 VCC INP1 3 INN1 2 VAC_REF1 1 EN Thermal Pad (GND) Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 PIN FUNCTIONS PIN NAME NO. TYPE VCC 5, 6, 11, 20, 31, 40 Power 2.5V supplies for the device GND 21, 30 Ground Device ground INP0, INN0 9, 8 Input Differential input pair or single ended input INP1, INN1 2, 3 Input Differential redundant input pair or single ended input OUTP0, OUTN0 12, 13 Output Differential LVDS output pair no. 0 OUTP1, OUTN1 14, 15 Output Differential LVDS output pair no. 1 OUTP2, OUTN2 16, 17 Output Differential LVDS output pair no. 2 OUTP3, OUTN3 18, 19 Output Differential LVDS output pair no. 3 OUTP4, OUTN4 22, 23 Output Differential LVDS output pair no. 4 OUTP5, OUTN5 24, 25 Output Differential LVDS output pair no. 5 OUTP6, OUTN6 26, 27 Output Differential LVDS output pair no. 6 OUTP7, OUTN7 28, 29 Output Differential LVDS output pair no. 7 OUTP8,OUTN8 32, 33 Output Differential LVDS output pair no. 8 OUTP9,OUTN9 34, 35 Output Differential LVDS output pair no. 9 OUTP10,OUTN10 36, 37 Output Differential LVDS output pair no. 10 OUTP11,OUTN11 38, 39 Output Differential LVDS output pair no. 11 VAC_REF0 7 Output Bias voltage output for capacitive coupled inputs. If used, it is recommended to use a 0.1µF to GND on this pin. VAC_REF1 4 Output Bias voltage output for capacitive coupled inputs. If used, it is recommended to use a 0.1µF to GND on this pin. NC 10 EN DESCRIPTION INP0/INN0 is the input INP1/INN1 is the input No connect Input with internal Control pin – enables or disables the outputs (See Table 1). 200kΩ pull-up and pull-down 1 Thermal Pad Ground Device ground. Thermal pad must be soldered to ground. See thermal management recommendations. Table 1. Output Control Table EN CLOCK OUTPUTS 0 All outputs disabled (static "0") Open All outputs enabled 1 OUT0 to OUT5 enabled and OUT6 to OUT11 disabled (static "0") Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 3 CDCLVD2106 SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.3 to 2.8 V Input voltage range, VI –0.2 to (VCC + 0.2) V Output voltage range, VO –0.2 to (VCC + 0.2) V Supply voltage range, VCC See note (2) Driver short circuit current, IOSD Electrostatic discharge (HBM, 1.5 kΩ, 100 pF) (1) (2) >3000 V Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. The outputs can handle permanent short. RECOMMENDED OPERATING CONDITIONS Device supply voltage, VCC Ambient temperature, TA MIN TYP MAX 2.375 2.5 2.625 V 85 °C –40 UNIT THERMAL INFORMATION CDCLVD2106 THERMAL METRIC (1) RHA (40 PINS) qJA Junction-to-ambient thermal resistance 31.0 qJC(top) Junction-to-case(top) thermal resistance 28.7 qJB Junction-to-board thermal resistance 9.3 yJT Junction-to-top characterization parameter 0.4 yJB Junction-to-board characterization parameter 9.3 qJC(bottom) Junction-to-case(bottom) thermal resistance 3.1 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ELECTRICAL CHARACTERISTICS At VCC = 2.375V to 2.625V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN CONTROL INPUT CHARACTERISTICS VdI3 3 State VdIH Input high voltage Open VdIL Input low voltage IdIH Input high current VCC = 2.625 V, VIH = 2.625 V IdIL Input low current VCC = 2.625 V, VIL = 0 V Rpull(EN) Input pull-up/ pull-down resistor 0.5×VCC V 0.7×VCC V 0.2×VCC V 30 mA –30 mA 200 kΩ 2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS fIN Input frequency Vth Input threshold voltage VIH Input high voltage VIL Input low voltage IIH Input high current VCC = 2.625 V, VIH = 2.625 V IIL Input low current VCC = 2.625 V, VIL = 0 V ΔV/ΔT Input edge rate 20%–80% CIN Input capacitance 2.5 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated 4 External threshold voltage applied to complementary input Product Folder Link(s): CDCLVD2106 200 MHz 1.5 V Vth + 0.1 VCC V 0 Vth – 0.1 V 10 mA 1.1 –10 1.5 mA V/ns pF CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS (continued) At VCC = 2.375V to 2.625V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIFFERENTIAL INPUT CHARACTERISTICS fIN Input frequency Clock input 800 MHz Differential input voltage peak-to-peak VICM = 1.25 V 0.3 1.6 VPP VICM Input common mode voltage range VIN, DIFF, PP > 0.4 V 1.0 VCC – 0.3 V IIH Input high current VCC = 2.625 V, VIH = 2.625 V 10 mA IIL Input low current VCC = 2.625, VIL = 0 V ΔV/ΔT Input edge rate 20%–80% CIN Input capacitance VIN, DIFF –10 0.75 mA V/ns 2.5 pF LVDS OUTPUT CHARACTERISTICS |VOD| Differential output voltage magnitude ΔVOD Change in differential output voltage magnitude VOC(SS) Steady-state common mode output voltage ΔVOC(SS) Steady-state common mode output voltage VIN, DIFF, PP = 0.6V, RL = 100 Ω Vring Output overshoot and undershoot Percentage of output amplitude VOD VOS Output ac common mode VIN, DIFF, PP = 0.6V, RL = 100 Ω IOS Short-circuit output current VOD = 0 V tPD Propagation delay VIN, DIFF, PP = 0.3 V tSK, PP Part-to-part skew tSK.O_WB Within bank output skew tSK.O_BB Bank-to-bank output skew tSK,P Crossing-point-to-crossing-point Pulse skew(with 50% duty cycle input) distortion tRJIT Random additive jitter (with 50% duty cycle input) Edge speed = 0.75 V/ns, 10 kHz – 20 MHz tR/tF Output rise/fall time 20% to 80%, 100 Ω, 5 pF 300 ps ICCSTAT Static supply current Outputs unterminated, f = 0 Hz 27 45 mA ICC100 Supply current All outputs enabled; RL = 100 Ω, f = 100 MHz 97 133 mA ICC800 Supply current All outputs enabled; RL = 100 Ω, f = 800 MHz 137 177 mA 1.25 1.35 V VIN, DIFF, PP = 0.3V, RL = 100 Ω 250 450 –15 15 1.1 1.375 –15 15 mV mV V mV 10% 40 1.5 Both inputs are phase aligned –50 70 mVP-P ±24 mA 2.5 ns 600 ps 45 ps 75 ps 50 0.3 50 ps ps, RMS VAC_REF CHARACTERISTICS VAC_REF Reference output voltage VCC = 2.5 V, Iload = 100 µA 1.1 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 5 CDCLVD2106 SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com Typical Additive Phase Noise Characteristics for 100 MHz Clock PARAMETER MIN TYP MAX UNIT phn100 Phase noise at 100 Hz offset -132.9 dBc/Hz phn1k Phase noise at 1 kHz offset -138.8 dBc/Hz phn10k Phase noise at 10 kHz offset -147.4 dBc/Hz phn100k Phase noise at 100 kHz offset -153.6 dBc/Hz phn1M Phase noise at 1 MHz offset -155.2 dBc/Hz phn10M Phase noise at 10 MHz offset -156.2 dBc/Hz phn20M Phase noise at 20 MHz offset -156.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 171 fs, RMS Typical Additive Phase Noise Characteristics for 737.27 MHz Clock PARAMETER phn100 Phase noise at 100 Hz offset phn1k Phase noise at 1 kHz offset phn10k Phase noise at 10 kHz offset phn100k MIN TYP MAX UNIT -80.2 dBc/Hz -114.3 dBc/Hz -138 dBc/Hz Phase noise at 100 kHz offset -143.9 dBc/Hz phn1M Phase noise at 1 MHz offset -145.2 dBc/Hz phn10M Phase noise at 10 MHz offset -146.5 dBc/Hz phn20M Phase noise at 20 MHz offset -146.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 65 fs, RMS 6 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS Phase Noise - dBc/Hz INPUT- AND OUTPUT-CLOCK PHASE NOISES vs FREQUENCY FROM the CARRIER (TA = 25°C and VCC = 2.5V) Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs Figure 3. 100 MHz Input and Output Phase Noise Plots Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 7 CDCLVD2106 SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY VOD − Differential Output Voltage − mV 350 TA = 25oC 340 2.625V 330 320 2.5V 310 300 2.375V 290 280 270 260 250 0 100 200 300 400 500 600 700 800 Frequency − MHz Figure 4. Differential Output Voltage vs Frequency TEST CONFIGURATIONS LVDS Oscilloscope 100 W Figure 5. LVDS Output DC Configuration During Device Test Phase Noise Analyzer LVDS 50 W Figure 6. LVDS Output AC Configuration During Device Test 8 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) VIH Vth IN VIL IN Vth Figure 7. DC Coupled LVCMOS Input During Device Test VOH OUTNx VOD OUTPx VOL 80% VOUT,DIFF,PP (= 2 x VOD) 20% 0V tr tf Figure 8. Output Voltage and Rise/Fall Time Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 9 CDCLVD2106 SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) INNx INPx OUTN0 tPLH0 tPHL0 tPLH1 tPHL1 OUTP0 OUTN1 OUTP1 OUTN2 tPLH2 tPHL2 OUTP2 OUTN11 tPHL11 tPLH11 OUTP11 A. Output skew is calculated as the greater of the following: As of the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..11) B. Part to part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..11) C. Both inputs (IN0 and IN1) are phase aligned Figure 9. Output Skew and Part-to-Part Skew spacer spacer Vring OUTNx VOD 0 V Differential OUTPx Figure 10. Output Overshoot and Undershoot 10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) VOS GND Figure 11. Output AC Common Mode APPLICATION INFORMATION THERMAL MANAGEMENT For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure adequate heat conduction to of the package. Check the mechanical data at the end of the data sheet for land and via pattern examples. POWER SUPPLY FILTERING High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is very critical to the application. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It is recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with very low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation. Board Supply Chip Supply Ferrite Bead 1 µF 10µF 0.1 µF (x6) Figure 12. Power Supply Filtering Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 11 CDCLVD2106 SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com LVDS OUTPUT TERMINATION The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage different than the output common mode voltage of the CDCLVD2106, ac-coupling should be used. If the LVDS receiver has internal 100 Ω termination, external termination must be omitted. Unused outputs can be left open without connecting any trace to the output pins. Z = 50 W 100 W CDCLVD2106 LVDS Z = 50 W Figure 13. LVDS Output DC Termination 100 nF Z = 50 W 100 W CDCLVD2106 LVDS Z = 50 W 100 nF Figure 14. LVDS Output AC Termination with Receiver Internally Biased 12 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 INPUT TERMINATION The CDCLVD2106 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers. LVDS Driver can be connected to CDCLVD2106 inputs with dc or ac coupling as shown Figure 15 and Figure 16 respectively. Figure 17 shows how to connect LVPECL inputs to the CDCLVD2106. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP. Figure 18 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2106 directly. The series resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs to be limited to VIH ≤ VCC. Z = 50 W 100 W LVDS CDCLVD2106 Z = 50 W Figure 15. LVDS Clock Driver Connected to CDCLVD2106 Input (DC coupled) spacer 100 nF Z = 50 W CDCLVD2106 LVDS Z = 50 W 100 nF 50 W 50 W VAC_REF Figure 16. LVDS Clock Driver Connected to CDCLVD2106 Input (AC coupled) spacer 75 W 100 nF Z = 50 W CDCLVD2106 LVPECL 75 W Z = 50 W 100 nF 150 W 150 W 50 W 50 W VAC_REF Figure 17. LVPECL Clock Driver Connected to CDCLVD2106 Input Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 13 CDCLVD2106 SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com Rs LVCMOS (2.5V) Z = 50 W CDCLVD2106 Vth = VIH +VIL 2 Figure 18. 2.5V LVCMOS Clock Driver Connected to CDCLVD2106 Input If one of the input buffers is used, then the other buffer should be disabled using the control pin EN; and, unused input pins should be grounded by 1-kΩ resistors. Spacer REVISION HISTORY Changes from Original (September 2010) to Revision A Page • Changed tSK.O_BB Bank-to-bank output slew From: 170 ps (Max) To: 75 ps (Max) .............................................................. 5 • Deleted the Recommended PCB Layout illustration .......................................................................................................... 11 Changes from Revision A (November 2010) to Revision B • 14 Page Changed the device status From: Product Preview To: Production ..................................................................................... 1 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2106 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) CDCLVD2106RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCLVD2106RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CDCLVD2106RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 CDCLVD2106RHAT VQFN RHA 40 250 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVD2106RHAR VQFN RHA 40 2500 336.6 336.6 28.6 CDCLVD2106RHAT VQFN RHA 40 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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