[AKD2300] AKD2300 AK2300 Evaluation Board Board Function The AKD2300 is the evaluation board for the AK2300.The AKD2300 has on-board(internal) clock generate function. The evaluation can begin by setting the DIP Switches. External resistance and capacitors of the I/O amplifier can be changed. It provides easy the setting of the parameter of the desire. Board Layout 1.Power supply pins 4.Degital Interface 5.Analog Interface 6. Path selection Jumpers 2.The PLD setting Switches 3.The AK2300 setting Switches The AKD2300 has six following components. 1 : Power supply pins 2 : The PLD setting Switches 3 : The AK2300 setting Switches 4 : Digital Interface 5 : Analog Interface 6 : Path selection Jumpers of the AK2300 input data <KM103501> 1 2015/02 [AKD2300] Power supply pins Power supply pins is VDD,VSS,LVDD,LVDDX,VDDX_3.3V,VSSX. Please feed 1.7V～3.6V to the LVDD and LVDDX, and feed 2.6V～3.6V to the VDD. Supply 3.3V to VDDX_3.3V. However, set to become VDD≧LVDD. Connect VSS and VSSX with GND. Each power supply and GND can be connected by the JP1 and the JP2 and the JP3 and the JP4. These jumpers settings are shown below. When the digital noise influences on analog characteristics, please remove these jumpers to separate these power line. Jumper Name JP1 JP2 JP3 JP4 Function LVDD and LVDDX are connected. VDD and VDDX_3.3V are connected. VDD and LVDD are connected. VSS and VSSX are connected. The PLD Setting Switches The DSW2 and the DSW3 and the DSW4 are switches of the PLD settings. (DSW1 is unused) The functions of the switches are shown below. DSW2 Switch Name Function BCLK Selection This switch is selects internal BCLK frequency. FRQ2 FRQ1 FRQ0 <KM103501> FRQ2 0 0 0 0 1 1 1 FRQ1 0 0 1 1 0 0 1 FRQ0 0 1 0 1 0 1 ＊ Frequency 64kHz 128kHz 256kHz 512kHz 1024kHz 2048kH Don’t care 2 2015/02 [AKD2300] DSW3 Switch Name SYNC1 SYNC0 EXT/INT Function Frame sync signal selection (Available in INT mode only) Output a sync signal for external measurement systems to the TP8(RSYNC) and the TP9(TSYNC). Output Signal SYNC1 SYNC0 Refer to the Figure 1. 0 0 Refer to the Figure 1. 0 1 Refer to the Figure 1. 1 0 Refer to the Figure 1. 1 1 Set the method of supplying BCLK and FS. EXT： The external clock feed from digital interface. INT： On-board(internal) clock used. <Short Frame> BCLK FS 00 01 SYNC[1:0] 10 11 <Long Frame> BCLK FS 00 01 SYNC[1:0] 10 11 Figure 1 <KM103501> 3 2015/02 [AKD2300] DSW4 Switch Name PCM1 PCM0 Function PCM Interface setting1 This switch selects data format of PCM interface. PCM Interface PCM1 PCM0 A-Law (DIF0 = L) 0 0 μ-Law (DIF0 = H) 0 1 Linear (DIF0 = FS) 1 ＊ PCM Interface setting2 This switch selects FS type at the INT mode. SF/LF SF： Short Frame(Refer to the Figure 1) LF： Long Frame(Refer to the Figure 1) The AK2300 Setting Switches The SW1 and the SW2 and the DSW4-4 are switches of the AK2300 settings. The functions of the switches are shown below. SW1 Switch Name Function PCM Codec output settings This switch sets the output of PCM CODEC mute. MUTEN OFF： Normal operation ON： Mute SW2 Switch Name Function Power down mode settings This switch sets power-down mode of the AK2300. PDN <KM103501> OFF： Normal operation ON： Power down mode 4 2015/02 [AKD2300] DSW4-4 Switch Name DLY/JST Function PCM Interface settings3 This switch selects input and output timing of PCM data. DLY(DIF1 = L)： MSB of DX/DR are input/output by next rising edge of BCLK after the rising edge of FS. (Refer to the Figure 2) JST(DIF1 = H)： MSB of DX/DR are input/output by rising edge of FS. (Refer to the Figure 2) <JST> BCLK FS DX DR Don't care MSB LSB MSB LSB <DLY> BCLK FS DX DR Don't care MSB LSB MSB LSB Figure 2 <KM103501> 5 2015/02 [AKD2300] Digital Interface The AKD2300 has CN1 as a digital interface. Pin No 1 Signal Name DX 3 DR Function This pin outputs the DX data from the AK2300. This pin inputs the DR data to the AK2300. When the JP5 is used, As for DX data the loop backing is by DR data. This pin inputs external signal BCLK. * This pin inputs external signal FS. * This pin inputs external signal DIF0. * This pin inputs external signal DIF1. This pin inputs external signal MUTEN. This pin inputs external signal PDN. This pin is connected with VDD. 5 BCLK 7 FS 9 DIF0 11 DIF1 13 MUTEN 15 PDN 16 VDD 2/4/6/8 These pins are connected with VSS. VSS 10/12/14 *:Available in EXT mode only. Analog Interface The AKD2300 has BNC connector VFTN for transmission amplifier input and BNC connector VR for reception amplifier output. Insert resistance and capacitors of each amplifier in the socket pin. It provides easy the setting of the parameter of the desire. When shipped, it is set in the parameter of the application circuit of the AK2300 data sheets. ◆Analog input circuit ◆Analog output circuit GST SP2 VFTN SP4 SP5 SP3 VFTN VR - SP1 VR + Figure 3 <KM103501> 6 2015/02 [AKD2300] Path selection jumpers of the AK2300 input data The JP6 and the JP7 and the JP8 are selected input signal (MUTEN,PDN,DIF1) path of the AK2300. These jumpers settings are shown below. Jumper Name JP6 JP7 JP8 State Short Open Short Open Short Open Function The MUTEN pin inputs the SW1 setting. The MUTEN pin inputs the CN1 setting. The PDN pin inputs the SW2 setting. The PDN pin inputs the CN1 setting. The DIF1 pin inputs the DSW4(DLY-JST) setting. The DIF1 pin inputs the CN1 setting. Connection selection jumpers of the AK2300 Exposed Pad Jumper Name JP9 <KM103501> State Short Open Function Exposed Pad of the AK2300 and VSS are connected. Exposed Pad of the AK2300 is Opened. 7 2015/02 VSS VSSX 4 5 6 4 5 6 5 6 7 8 4 5 6 3 2 1 4 3 2 1 3 2 1 2 1 1 3 2 1 1 VSSX C15 22pF DSW1 FRQ_SEL DSW2 PCM I/F DSW4 DSW3 1M R4 Y1 1 2 1 10k 2 U4A 2 VDDX_3.3V RD1 1 3 CLK 44 43 34 36 33 8 12 13 5 6 7 FRQ_SEL2 FRQ_SEL1 FRQ_SEL0 RSV2 RSV1 RSV0 TC4069UBF U4B 4 VDDX_3.3V 14 18 19 20 21 22 1 1 1 2 0.1uF 0.1uF C18 2 1 C11 VDDX_3.3V JP4 I/O/GCK2 I/O/GCK1 I/O/GTS2 I/O/GTS1 I/O/GSR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O U2 VSSX SY NC1 SY NC0 INT_EXT PCM1 PCM0 LF_SF 4 3 2 7 6 5 7 6 5 4 3 2 1 C16 1 C17 0.1uF 2 22pF 2 4.096MHz 2 DLY _JST R1 10k VDDX_3.3V 1 RD2 1 10uF 2 C2 15 35 26 2 C19 2 TMS TDI TDO TCK I/O I/O I/O I/O I/O I/O I/O I/O/GCK3 I/O I/O I/O I/O I/O I/O I/O I/O I/O 0.1uF 1 2 XC9572XL-VQ44 VCC VCC VCCIO JP2 25 17 4 GND GND GND 10 9 24 11 29 28 23 27 39 40 41 1 2 3 42 32 31 30 37 38 16 1 TP8 MONI0 MONI1 MONI2 MONI3 I_BCLK I_FS I_DIF0 TP9 1 JP3 CN2 6 VDDX_3.3V HEADER PIN6 VSSX 1 2 3 4 5 TP5 TP4 10uF TP7 TP6 1 C3 T4 2 VDD VSS RSY NC TSY NC VSSX C1 10uF 2 T3 2 2 1 VSS JP5 JP1 1 VSS BNC2 1 LVDD VFTN T5 2 T2 TP3 TP1 2 2 1 VSS 13 1 19 2 8 6 4 9 15 17 SP4 VSS 1 C6 10uF 2 2 LVDDX 1 1 2 JP7 JP6 2 1 1 1 7 VSS 1 C13 2 0.1uF C14 0.1uF JP8 18 12 14 16 11 5 3 DLY _JST 1 TC74VCX244FT Y6 Y1 Y4 Y3 Y2 A5 Y7 Y8 SP2 2 1 VSS C12 0.1uF 2 VSS 2 SP3 2 1 2 SW2 R2 10k LVDDX 1 LVDD 12 DX 11 SW1 R3 10k DIF1 PDN TP10 MUTEN DX DIF0 FS BCLK DR VFTN GST TP11 8 9 4 TP13 AK2300 EXPAD PLLC VREF VSS VR VDD LVDD U1 TP12 DIF1 5 PDN 2 MUTEN 1 2 1 14 DIF0 13 FS BCLK 15 DR 16 VFTN 7 GST 6 VDD 3 C5 1 C8 0.1uF 1uF 2 VSS 10 VDD 1 C4 1 C7 1uF 2 0.1uF 2 SP5 2 1 LVDD LVDDX A6 1OE 2OE A1 A4 A3 A2 Y5 A7 A8 U3 2 20 VCC VDD 14 7 10 GND VDDX_3.3V 2 1 T1 2 8 1 <KM103501> 2 1 2 TP2 VSS JP9 I_MUTEN I_PDN I_DIF1 O_DX I_DIF0 I_FS I_BCLK I_DR 1 1 BNC1 EXPAD 16 15 14 13 12 11 10 9 VSS VR VSS CN1 HEADER PIN16 13 2 15 4 11 6 1 8 9 10 7 12 5 14 3 16 2 QN1-016050-202 1 2 3 4 5 6 7 8 SO1 C9 0.056uF(+-30%) MUTEN PDN VDD VR DIF1 GST VFTN VREF 1 EXPAD 2 0.1uF 1 C10 VREF PLLC VR SP1 2 VSSX VSS VDD EXPAD DR BCLK FS DIF0 LVDD DX VSS PLLC [AKD2300] Board Circuit The circuit chart of the AKD2300 is shown in the following. 2015/02 [AKD2300] Revision History Date (yy/mm/dd) 10/05/13 Manual Revision KM103500 Board Revision 0 Reason Page First edition - 15/02/23 KM103501 0 Add <KM103501> 9-10 9 Contents “Revision History” and “IMPORTANT NOTICE” are added. 2015/02 [AKD2300] IMPORTANT NOTICE 0. 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