[AK7757] AK7757 Audio DSP with 24bit 3ch ADC + 4ch DAC + MIC Amp GENERAL DESCRIPTION The AK7757 is a digital signal processor with an integrated 4ch DAC, a stereo ADC with input selector, a mono ADC and an integrated digital audio interface. The audio DSP has 1536 step/fs (at 48kHz sampling) parallel arithmetic operation performance. As the AK7757 is a RAM based DSP, it is programmable for user requirements to realize the audio effects process or the proprietary high-performance HF. It is housed in a 48pin LQFP which is a small package to save the PCB space. FEATURES DSP - Word length: 24bits (Data RAM: F24 floating point) - Processing Speed: 13.6 ns (9216step/fs; fs = 8kHz) - Multiplication: 20 x 20 → 36-bit Double precision arithmetic available - Divider 20 / 20 → 20-bit - ALU: 40-bit arithmetic operation (overflow margin 4bits) 24-bit floating point arithmetic and logic operation - Program RAM: 4096 x 36bits - Coefficient RAM: 4096 x 20bits - Data RAM: 2048 x 24bits (F24 floating point) - Delay RAM: 4096 x 20bits, 4096 x 20bits - Master Clock: 73.7MHz - JX pins (interrupt) 2ch ADC1 - Sampling Frequency: 8kHz~48kHz - 3in / 1out Input Selector (Diffrentialx1 single endx1 single end with MicAmpx1) - ADC S/N: 96dBA, S/ (N+D): 88dB 1ch ADC2 - Sampling Frequency: 8kHz~48kHz - ADC S/N: 89dBA, S/(N+D): 82dB 4ch DAC - Sampling Frequency: 8kHz~48kHz - DAC S/N: 107dBA, S/ (N+D): 92dB Microphone Interface - Differential or single-end input - Programmable Gain (+33dB ~ +15dB and 0dB, 3dB step) - Low Noise Microphone Bias Automatic Power Down (CODEC, DSP) μP I/F: SPI, I2C Power supply Analog (AVDD): 3.0V ~ 3.6V (typ.3.3V) Digital1 (DVDD): 3.0V ~ 3.6V (typ.3.3V) Digital2 (DVDD18): 1.7V ~ 1.9V (typ.1.8V) Operating temperature range: -40°C ~ 85°C Package: 48pin LQFP MS1489-E-02-PB - 1 - 2013/07 [AK7757] ■ Block Diagram AVDD MPRF DVDD18 AVSS DVDD VCOM 2 2 MICBIAS PMAD2 AINTP ADC2 AINTN JX1E AKM JX1 DSP Core JX2 MIC Power Supply JX2E DIN4 (Mono) AIN/INP INN AIN2RP /N LRCK1 LRCK2/JX1 SELDI3 2 BICK1 BICK2/JX2 ADC1 DIN3 AIN1L AIN2LP /N CLKO LRCKO BICKO PLL / PCM Interface PMAD1 AIN1R 2 2 PMMB DVSS XTO XTI 2 SELDI2 SDIN1 SDIN2/JX0 LFLT VDD DIN2 DOUT3 SELDO3 GP0 SELDI1 DOUT1 EXPDRN/SDOUT3/GPO SDOUT1 DIN1 SELDO1 WDT/CRC STO STO/RDY/SDOUTM SELDOM PMDAC2 JX0E JX0 JX3 AOUT2L AOUT2R DAC2 JX3E DOUT2 DOUT5 μP (I2C,SPI)/ Interface Line Out PMDAC1 AOUT1L DAC1 RDY/SDOUT2/JX3 RDY SELDO2 CSN / CAD1 SCLK/SCL SO / SDA DOUT4 SI / CAD0 AOUT1R Memory EEST I2CSEL IRSTN Figure 1. Block Diagram . MS1489-E-02-PB - 2 - 2013/07 [AK7757] ■ Ordering Guide -40 ∼ +85°C 48pin LQFP Evaluation Board for AK7757 AK7757VQ AKD7757 AVSS DVDD DVSS I2CSEL IRSTN BICK2 / JX2 LRCK2 / JX1 DVDD18 EXPDRN/ SDOUT3/GPO RDY / SDOUT2 / JX3 SDOUT1 34 33 32 31 30 29 28 27 26 25 AOUT2L 35 37 AVDD AOUT2R 36 ■ Pin Layout 24 BICKO 38 23 LRCKO AOUT1R 39 22 CLKO AOUT1L 40 21 SO / SDA AVDD 41 20 SI / CAD0 VCOM 42 19 SCL / SCLK AVSS 43 18 CSN / CAD1 MPRF 44 17 STO/RDY/SDOUTM MICBIAS 45 16 SDIN2 / JX0 AINTP 46 15 SDIN1 AINTN 47 14 BICK1 AIN1R 48 13 LRCK1 AK7757 48pin LQFP 12 XTO 11 XTI 10 DVSS 9 DVDD 8 LFLT 7 AIN2RP 6 AIN2RN 5 AIN2LP 4 AIN2LN 3 AIN / INP 2 INN AIN1L 1 (TOP VIEW ) pin Input Output I/O Power MS1489-E-02-PB 3 2013/07 [AK7757] CP0, CP1 DLRAM DRAM 1024w × 24-Bit 1024w × 24-Bit CRAM 4096w x 20-Bit Address Pointer DLP0, DLP1 DP0, DP1 4096w x 20-Bit 4096w x 20-Bit OFREG 32w x 13-Bit CBUS(20-Bit) DBUS(24-Bit) MPX20 µP I/F MPX20 X Control Y Serial I/F PRAM DEC 4096w x 36-Bit Multiply 20 x 20 → 36-Bit PC Stack: 5 level(max) 24-Bit TMP 36-Bit 12 x 24-Bit PTMP(LIFO) 6 x 24-Bit MUL DBUS SHIFT 40-Bit 40-Bit A B ALU 1 x 24-Bit DIN4 2 x 24-Bit DIN3 2 x 24-Bit DIN2 2 x 24-Bit DIN1 2 x 24-Bit DOUT5 (DAC) 2 x 24-Bit DOUT4 (DAC) 2 x 24-Bit DOUT3 2 x 24-Bit DOUT2 2 x 24-Bit DOUT1 40-Bit Overflow Margin: 4-Bit 40-Bit DR0 ∼ 3 40-Bit Over Flow Data Generator Division 20÷20→20 Peak Detector Figure 2. Main DSP Block Diagram of the AK7757 MS1489-E-02-PB 4 2013/07 [AK7757] PIN FUNCTION No. 1 2 4 5 6 7 Pin Name AIN1L INN AIN INP AIN2LN AIN2LP AIN2RN AIN2RP 8 LFLT O 9 10 DVDD DVSS - 11 XTI I 12 XTO O 13 LRCK1 I 14 BICK1 I 15 SDIN1 SDIN2 I I JX0 I STO O RDY O SDOUTM O CSN I CAD1 I SCLK I SCL I 3 16 17 18 19 MS1489-E-02-PB I/O I I I I I I I I Function ADC1 Lch Single-ended Input 1 Pin. Microphone Inverted Differential Input Pin Microphne Single-ended Input Pin Microphone Non-inverted Differential Input Pin ADC1 Lch Inverted Differential Input 2 Pin ADC1 Lch Non-inverted Differential Input 2 Pin ADC1 Rch Inverted Differential Input 2 Pin ADC1 Rch Non-inverted Differential Input 2 Pin R and C Components Connect Pin for PLL Refer to “7. LFLT Pin External Connection”. This pin outputs “L” during initial reset. Digital Power Supply Pin 3.0~3.6V Ground Pin 0V Crystal Oscillator Input Pin Connect a crystal oscillator between this pin and the XTO pin, or input an external clock to the XTI pin. Crystal Oscillator Output Pin When a crystal oscillator is used, connect it between XTI and XTO. When an external clock is used, leave this pin open. During initial reset, the output of this pin is not determinable. LR Channel Select Clock Pin 1 LR clock should be input to this pin in slave mode. Serial Bit Clock Input Pin 1 BITCLOCK (48fs or 64fs) should be input to this pin in slave mode. Serial Data Input 1 Pin Serial Data Input 2 Pin Conditional Jump Pin0 The conditional jump pin (JX0) is valid by setting control register (JX0E) to “1”. Status Output Pin This pin outputs “H” during initial reset. Data Write Ready Output Pin for Microprocessor Interface This pin outputs RDY. Serial Data Output Pin for Internal Monitoring μP I/F Chip Select N Pin (I2CSEL pin = “L”) When initial reset and μP I/F are not in use, leave the CSN pin High level. I2C-bus Address 1 Pin (I2CSEL pin = “H”) μP I/F Serial Data Clock Pin (I2CSEL pin = “L”) Set this pin to “H” when there are no clock inputs. I2C I/F Data Clock Pin (I2CSEL pin= “H”) 5 2013/07 [AK7757] SI 20 I CAD0 I SO O 21 SDA I/O 22 CLKO O 23 LRCKO O 24 BICKO O 25 SDOUT1 O RDY O SDOUT2 O JX3 I EXPDRN O 27 SDOUT3 O 28 GPO DVDD18 O - LRCK2 I JX1 I BICK2 I JX2 I 31 IRSTN I 32 I2CSEL I 33 34 35 36 DVSS DVDD AVSS AVDD - 37 AOUT2R O 38 AOUT2L O 39 AOUT1R O 40 AOUT1L O 26 29 30 MS1489-E-02-PB μP I/F Serial Data Input Pin (I2CSEL pin = “L”) Set this pin to “L” when not used. I2C-bus Address 0 Pin (I2CSEL pin = “H”) μP I/F Serial Data Output Pin This pin outputs “Hi-Z” during initial reset. I2C-bus I/F Serial Data In/Output Pin (I2CSEL pin= “H”) This pin outputs Hi-Z during initial reset. Clock Output Pin This pin outputs “L” during initial reset. LR Channel Select Output Pin This pin outputs “L” during initial reset in master mode. Serial Bit Clock Output Pin This pin outputs “L” during initial reset in master mode. Serial Data Output1 Pin This pin outputs “L” during initial reset. Data Write Ready Output Pin for Microprocessor Interface Set DOUT2IOE bit= “1” and JX3E bit = “0” when this pin is used as an output pin. A pull-down resistor should be connected. Serial Data Output2 Pin Set DOUT2IOE bit= “1” and JX3E bit = “0” when this pin is used as an output pin. A pull-down resistor should be connected. Conditional Jump Pin3 The conditional jump pin (JX3) is valid by setting control register (JX3E) to “1”. Power Down Signal Output Pin Serial Data Output3 Pin This pin outputs “L” during initial reset. General Purpose Output Pin for External Device Controlling Digital Power Supply Pin 1.7~1.9V LR Channel Select Clock Pin 2 LR clock should be input to this pin in slave mode. Conditional Jump Pin 1 The conditional jump pin (JX1) is valid by setting control register (JX1E) to “1”. Serial Bit Clock Input Pin 2 BITCLOCK should be input to this pin in slave mode. Conditional Jump Pin 2 The conditional jump pin (JX2) is valid by setting control register (JX2E) to “1”. Initial Reset N Pin Use to initialize the AK7757. Set this pin to “L” when power-up the AK7757. I2C BUS Select Pin I2CSEL pin = “L”: 4-wired Interface I2CSEL pin = “H”: I2CBus selected mode. SCL and SDA are active. I2CSEL should be connected to “L” (DVSS) or “H” (DVDD). Ground Pin 0V Digital Power Supply Pin 3.0~3.6V Ground Pin 0V Analog Power Supply Pin 3.0~3.6V DAC2 Rch Analog Output Pin This pin outputs “Hi-Z” during initial reset. DAC2 Lch Analog Output Pin This pin outputs “Hi-Z” during initial reset. DAC1 Rch Analog Output Pin This pin outputs “Hi-Z” during initial reset. DAC1 Lch Analog Output Pin This pin outputs “Hi-Z” during initial reset. 6 2013/07 [AK7757] 41 AVDD - Analog Power Supply Pin 3.0~3.6V Analog Common Voltage Output pin Connect 0.1μF and 2.2μF capacitors between this pin and the AVSS pin. No 42 VCOM O external circuits should be connected to this pin. This pin outputs “L” during initial reset. 43 AVSS Ground Pin 0V Output Pin for Ripple Filter of MICBIAS Circuit 44 MPRF I Connect a 1.0μF capacitor between this pin and AVSS. This pin outputs “H” during initial reset. Power Supply Pin for Microphone 45 MICBIAS O This pin outputs “Hi-Z” during initial reset. 46 AINTP I ADC2 Non-inverted Differential Input Pin 47 AINTN I ADC2 Inverted Differential Input Pin 48 AIN1R I ADC1 Rch Single-ended Input 1 Pin Note 1. All digital input pins must not be left floating. Note 2. DVDD or DVSS voltage must be input to the I2CSEL pin. Note 3. All analog input pins (INP/AIN, INN pins) must be supplied signal via AC-coupling capacitor. Note 4. Analog output pins (AOUT1/2 pins) must deliver signal via AC-coupling capacitor ■ Handling of Unused Pin Unused I/O pins must be connected appropriately Classification Pin Name MICBIAS, AINTP/N, AIN/INP, INN, AIN2LP/N, AIN1L/R, Analog AIN2RP/N, AOUT1L/R, AOUT2L/R, MPRF XTO, SDOUT1, STO/RDY/SDOUTM, EXPDRN/SDOUT3/GPO, CLKO, LRCKO, BICKO Digital LRCK1, BICK1, LRCK2/JX1, BICK2/JX2, SDIN1, XTI, JX0/SDIN2, RDY/SDOUT2/JX3 (When Input Setting) MS1489-E-02-PB 7 Setting Open Open Connect to DVSS 2013/07 [AK7757] ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=0V: Note 5) Parameter Symbol min max Unit Power Supplies: Analog AVDD 4.3 V −0.3 Digital 1 DVDD 4.3 V −0.3 Digital 2 DVDD18 2.5 V −0.3 Difference(AVSS, DVSS) ΔGND -0.3 0.3 V Input Current, Any Pin Except Supplies IIN mA ±10 Analog Input Voltage (Note 6) VINA (AVDD+0.3) or 4.3 V −0.3 Digital Input Voltage (Note 7) VIND1 (DVDD+0.3) or 4.3 V −0.3 Ambient Temperature (powered applied) Ta 85 −40 °C Storage Temperature Tstg 150 −65 °C Note 5. All voltages are with respect to ground. AVSS and DVSS must be in the same voltage. Note 6. AINTP/N, AIN/INP, INN, AIN2LP/N, AIN1L/R, AIN2RP/N pins Note 7. IRSTN, I2CSEL, SI/CAD0, SCL/SCLK, CSN/CAD1, BICK1, LRCK1, BICK2/JX2, LRCK2/JX1, SDIN1, SDIN2/JX0, and RDY/SDOUT2/JX3 pins Note 8. Pull-up resistors at SDA and SCL pins must be connected to the DVDD voltage or less. Do not turn off the power supplies when the SDA and SCL pins are pulled-up to DVDD. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=DVSS =0V: Note 5) Parameter Symbol min typ max Unit Power Supplies Analog AVDD 3.0 3.3 3.6 V (Note 9) Digital DVDD 3.0 3.3 3.6 V Digital DVDD18 1.7 1.8 1.9 V Difference1 AVDD – DVDD -0.3 0 +0.3 V Note 5. All voltages are with respect to ground. AVSS and DVSS must be in the same voltage. Note 9. The power supply sequence for AVDD, DVDD and DVDD18 is not critical but all power supplies must be On before start operating the AK7757. WARNING: Do not turn off the power supply of the AK7757 with the power supply of the surrounding device turned on. Pull-up of SDA and SCL pins must not exceed DVDD. (A diode exists for DVDD in the SDA and SCL pins.) AKM assumes no responsibility for the usage beyond the conditions in the datasheet. MS1489-E-02-PB 8 2013/07 [AK7757] ANALOG CHARACTERISTICS (CODEC) ■ ADC Characteristics 1. Microphone Amplifier (Ta= 25ºC; AVDD=DVDD=3.3V; DVDD18=1.8V; AVSS=DVSS=0V) Parameter min Input impedance 22.5 MGAIN[2:0]bits=0h MGAIN[2:0]bits=1h MGAIN[2:0]bits=2h MIC AMP MGAIN[2:0]bits=3h Gain MGAIN[2:0]bits=4h MGAIN[2:0]bits=5h MGAIN[2:0]bits=6h MGAIN[2:0]bits=7h typ 30 0 15 18 21 24 27 30 33 2. Microphone Bias (Ta= 25ºC; AVDD=DVDD=3.3V; DVDD18=1.8V; AVSS=DVSS=0V) Parameter min Output Load Current 0mA MIC Voltage BIAS Load Current 1mA Load Resistance Load Capacitance Note 10. The output voltage is proportional to AVDD. max typ 2.46 Unit kΩ dB dB dB dB dB dB dB dB max 2.32 2 30 Unit V V kΩ pF 3. ADC1 (Ta=25ºC; AVDD=DVDD=3.3V, DVDD18=1.8V, VSS=0V, BICK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~20kHz @fs=48kHz; with Differential Input; Unless otherwise specified.) Parameter min typ max Unit Resolution 24 Bits ADC Section Dynamic Characteristics 88 dB S/(N+D) (-1dBFS) 78 MGAIN[2:0]=0h(0dB) 80 dB MGAIN[2:0]=3h(+21dB) 70 96 dB Dynamic Range MGAIN[2:0]=0h(0dB) 86 (A-weighted) (Note 11) 86 dB MGAIN[2:0]=3h(+21dB) 76 96 dB S/N (A-weighted) MGAIN[2:0]=0h(0dB) 86 76 86 dB MGAIN[2:0]=3h(+21dB) Inter-Channel Isolation (fin=1kHz) (Note 12) 90 110 dB DC accuracy Channel Gain Mismatch 0.0 0.3 dB Analog Input Input Voltage (Differential) Vp-p ±2.00 ±2.20 ±2.40 Input Voltage (Single-ended) 2.00 2.20 2.40 Vp-p Input Impedance 22.5 30 kΩ Note 11. S/(N+D) when -60dB FS signal is applied. Note 12. Inter-channel isolation between AINR and AINL with –1dB FS signal input. MS1489-E-02-PB 9 2013/07 [AK7757] 2. ADC2 (Ta=25ºC; AVDD=DVDD=3.3V, DVDD18=1.8V, VSS=0V, BICK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~20kHz @fs=48kHz; with Differential Input, Unless otherwise specified.) Parameter min typ max Unit Resolution 24 Bits ADC Section Dynamic Characteristics S/(N+D) (-1dBFS) 82 dB 74 Dynamic Range (A-weighted) (Note 11) 89 dB 81 S/N (A-weighted) 89 dB 81 Analog Input Input Voltage (Differential) Vp-p ±2.00 ±2.20 ±2.40 Input Impedance 22.5 30 kΩ Note 11. S/(N+D) when -60dB FS signal is applied. MS1489-E-02-PB 10 2013/07 [AK7757] ■ DAC Characteristics (Ta=25ºC; AVDD=DVDD=3.3V; DVDD18=1.8V, VSS=0V, BICK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~20kHz @fs=48kHz; in Differential Input, Unless otherwise specified.) Parameter min typ max Unit Resolution 24 Bits DAC1 DAC2 Dynamic Characteristics S/(N+D) (0 dBFS) 0dBFS output mode 82 92 dB -20dBFS output mode 75 85 dB Dynamic Range 0dBFS output mode 100 107 dB (A-weighted) (Note 11) -20dBFS output mode 90 dB 80 (Note 15) S/N (A-weighted) 0dBFS output mode 100 107 dB -20dBFS output mode 80 (Note 15) 90 dB Inter-channel Isolation (f=1kHz) (Note 13) 90 110 dB DC accuracy Channel Gain Mismatch (Note 14) 0.0 0.7 dB Analog output Output Voltage 0dBFS output mode 2.0 2.2 2.4 Vp-p -20dBFS output mode 0.2 0.22 0.24 Vp-p Load Resistance 5 kΩ Load Capacitance 30 pF Note 11. S/(N+D) when -60dB FS signal is applied. Note 13. Indicates isolation between each DAC of Lch and Rch when -1dBFS signal is applied. Note 14. Channel gain mismatch between all output channels (DAC1L/R, DAC2L/R). Note 15. Ta=25ºC, AVDD=DVDD=3.0~3.6V MS1489-E-02-PB 11 2013/07 [AK7757] DC CHARACTERISTICS (Ta=Tmin~Tmax; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; AVSS=DVSS=0V) Parameter Symbol min typ High level input voltage (Note 16) VIH 80%DVDD Low level input voltage (Note 16) VIL SCL, SDA High level input voltage VIH 70%DVDD SCL, SDA Low level input voltage VIL VOH DVDD-0.4 High level output voltage: Iout=-100μA (Note 17) VOL Low level output voltage: Iout=100μA (Note 17) SDA Low level output voltage Iout=3mA VOL Input leak current (Note 18) Iin Input leak current XTI pin Iix 26 Note 16. SCL and SDA/SO pins are not included. Note 17. Except the SDA/SO pin. Note 18. Except the XTI pin. max 20%DVDD 30%DVDD 0.4 0.4 ±10 Unit V V V V V V V μA μA POWER CONSUMPTION (Ta=25ºC; AVDD=DVDD=3.3V; DVDD18=1.8V; AVSS=DVSS=0V, fin=1 kHz, 24-bit, fs=8 kHz (CKM mode = 0), DSPS=BITFS=PMOSC bits= “0” PMMB bit=“1”, DSP running with programmed connecting DIN2 with DOUT1 and DIN1 with DOUT3.) Parameter min typ max Unit Power Supplies: (Note 19) Power-Up (IRSTN pin = “H”) CODEC+DSP All Circuit Power-up AVDD+DVDD AVDD=DVDD=3.3V 50 mA DVDD18=1.8V DVDD18 50 mA Power Consumption 255 mW AVDD+DVDD AVDD=DVDD=3.6V 70 mA DVDD18=1.9V DVDD18 70 mA Reset (IRSTN pin = “L”), Power-down condition (Note 20) AVDD+DVDD (Referential) 1 μA DVDD18 (Referential) 6 μA Note 19. The current of DVDD changes depending on the system frequency and contents of the DSP program. Note 20. All digital input pins are fixed to DVDD or DVSS. MS1489-E-02-PB 12 2013/07 [AK7757] DIGITAL FILTER CHARACTERISTICS ■ ADC Block (ADC1/2) 1. fs=48kHz (Ta=-40ºC ~85ºC, AVDD=DVDD=3.0~3.6V, fs=48kHz, Note 21) Parameter Symbol min typ max Unit Passband (±0.1dB) (Note 22) 0 18.9 PB kHz (-0.2dB) kHz 20.0 (-3.0dB) kHz 23.0 Stopband SB kHz 28 Passband Ripple (Note 22) PR dB ±0.04 Stopband Attenuation (Note 23, Note 24) SA dB 68 Group Delay Distortion ΔGD 0 μs Group Delay (Ts=1/fs) GD 16 Ts Note 21. The passband and stopband frequencies are proportional to fs (system sampling rate). High-pass filter characteristics are not included. Note 22. The passband is from DC to 18.9kHz when fs=48kHz. Note 23. The stopband is 28kHz to 3.044MHz when fs=48kHz. Note 24. When fs = 48kHz, the analog modulator samples the input signal at 3.072MHz. There is no attenuation of an input signal in band (n x 3.072MHz ±28kHz; n=0, 1, 2, 3…) of integer times of the sampling frequency by the digital filter. ■ DAC1-4 (Ta=-40ºC ~85ºC; AVDD=DVDD=3.0~3.6V; fs=48kHz; DEM=OFF) Parameter Symbol min typ max Unit Passband (±0.05dB) (Note 25) PB 0 21.7 kHz (-6.0dB) 24 kHz Stopband (Note 25) SB 26.2 kHz Passband Ripple PR ±0.01 dB Stopband Attenuation SA 64 dB Group Delay (Ts=1/fs) (Note 26) GD 24 Ts Digital Filter + Analog Filter Amplitude Characteristics 20Hz~20.0kHz ±0.5 dB Note 25. The pass band and stop band frequencies are proportional to “fs” (system sampling rate), and represents PB=0.4535fs (@±0.05dB) and SB=0.5465fs, respectively. Note 26. The digital filter delay is calculated as the time from setting data into the input register until an analog signal is output. MS1489-E-02-PB 13 2013/07 [AK7757] SWITCHING CHARACTERISTICS ■ System Clock (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, VSS =0V) Parameter Symbol XTI CKM[2:0]=000, 001, 010 a) with a Crystal Oscillator: fXTI CKM[2:0]=000 fs=44.1kHz fs=48kHz fXTI CKM[2:0]=001 fs=44.1kHz fs=48kHz b) with an External Clock Duty Cycle fXTI CKM[2:0]=000, 010 fs=44.1kHz fs=48kHz fXTI CKM[2:0]=001 fs=44.1kHz fs-48kHz LRCK Frequency (Note 27) fs min typ max Unit - 11.2896 12.288 16.9344 18.432 - MHz - MHz 50 11.2896 12.288 16.9344 18.432 60 % MHz - 40 11.0 16.5 7.35 12.4 18.6 48 MHz kHz BICK Frequency High Level Width tBCLKH 64 ns Low Level Width tBCLKL 64 ns Frequency 0.23 3.072 3.1 MHz fBCLK Note 27. LRCK frequency and sampling rate (fs) should be the same. Note 28. When BICK is the source of the master clock, it should be synchronized to LRCK and have stable frequency. ■ Reset (Ta= Tmin~Tmax, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; AVSS=DVSS=0V) Parameter Symbol min typ Reset pulse width (Note 29) tRST 600 Note 29. Set the IRSTN pin to “H” after all power supplies are fed. MS1489-E-02-PB 14 max Unit ns 2013/07 [AK7757] ■ Digital Audio Interface (SDIN1-2, SDOUT1-3) 1) SDIN1/2, SDOUT1/2/3 (Ta= Tmin~Tmax, AVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, AVSS=DVSS=0V, CL=20pF) Parameter Symbol min typ max I2S and PCM Interface Input Timing Delay Time from BICK “↑” to LRCK (Note 30) tBLRD 20 Delay Time from LRCK to BICK “↑” (Note 30) tLRBD 20 Serial Data Input Latch Setup Time tBSIDS 80 Serial Data Input Latch Hold Time tBSIDH 80 Delay Time from LRCK to Serial Data Output (Note 31) tLRD 80 Delay Time from BICK “↓” or “↑”to LRCK Output tBSOD 80 2 I S and PCM Interface Output Timing SDOUT1/2 BICK Frequency fBICK 64 BICK Duty cycle 50 Delay Time from BICK “↓” to LRCK tMBL -20 40 Serial Data Input Latch Setup Time tBSIDS 80 Serial Data Input Latch Hold Time tBSIDH 80 Delay Time from LRCK to Serial Data Output (Note 31) tLRD 80 Delay Time from BICK “↓” or “↑”to LRCK Output tBSOD 80 Note 30. BICK edge must not occur at the same time as LRCK edge. Note 31. Except I2S. MS1489-E-02-PB 15 Unit ns ns ns ns ns ns fs % ns ns ns ns ns 2013/07 [AK7757] ■ μP Interface (SPI mode) (Ta= Tmin~Tmax; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V, AVSS=DVSS=0V; CL=20pF) Parameter Symbol min typ max μP Interface Timing (SPI mode) CSN Fall Time tWRF 30 CSN Rise Time tWRR 30 SCLK Fall Time tSF 30 SCLK Rise Time tSR 30 SCLK Frequency fSCLK 2.7 SCLK Low Level Width tSCLKL 180 SCLK High Level Width tSCLKH 180 CSN High Level Width tWRQH 500 From CSN “↑” to IRSTN “↑” tRST1 600 From IRSTN “↑” to CSN “↓” tIRRQ 100 From CSN “↓” to SCLK “↓” tWSC 500 From SCLK “↑” to CSN “↑” tSCW 800 SI Latch Setup Time tSIS 180 SI Latch Hold Time tSIH 180 AK7757 → μP Delay Time from SCLK “↓”to SO Output tSOS 180 Hold Time from SCLK “↑” to SO Output (Note 32) tSOH 180 Note 32. Except for, when writing to 8th bit of command code. Unit ns ns ns ns MHz ns ns ns ns μs ns ns ns ns ns ns ■ μP Interface (I2C BUS mode) (Ta= Tmin~Tmax; AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, AVSS=DVSS=0V; CL=20pF) Parameter Symbol min typ max Unit I2C Timing SCL clock frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 μs Start Condition Hold Time tHD:STA 0.6 μs (prior to first Clock pulse) Clock Low Time 1.3 tLOW μs Clock High Time 0.6 tHIGH μs Setup Time for Repeated Start Condition 0.6 tSU:STA μs SDA Hold Time from SCL Falling 0 0.9 tHD:DAT μs SDA Setup Time from SCL Rising 0.1 tSU:DAT μs Rise Time of Both SDA and SCL Lines 0.3 tR μs Fall Time of Both SDA and SCL Lines 0.3 tF μs Setup Time for Stop Condition 0.6 tSU:STO μs Pulse Width of Spike Noise Suppressed tSP 0 50 ns by Input Filter Capacitive load on bus Cb 400 pF 2 Note 33. I C-bus is a trademark of NXP B.V. MS1489-E-02-PB 16 2013/07 [AK7757] ■ Timing Diagram 1/fXTI 1/fXTI tXTI=1/fXTI XTI VIH VIL 1/fs ts=1/fs 1/fs LRCK VIH VIL 1/fBICK 1/fBICK tBICK=1/fBICK VIH BICK VIL tBICKH tBICKL Figure 3. System Clock IRSTN tRST VIL Figure 4. Reset Note 34. The IRSTN pin must be “L” when power-up/power-down the AK7757. MS1489-E-02-PB - 17 - 2013/07 [AK7757] VIH VIL LRCK tBLRD tLRBD VIH VIL BICK tBSIDS tBSIDH VIH VIL SDIN1/2 Figure 5. Audio Interface (Input Interface in Slave Mode) VIH VIL LRCK tLRD VIH VIL BICK tLRD tBSOD SDOUT1/2/3 tBSOD 50%VDD Figure 6. Audio Interface (Output Interface in Slave Mode) MS1489-E-02-PB - 18 - 2013/07 [AK7757] LRCK 50%DVDD tMBL tMBL BICK 50%DVDD tBSIDS tBSIDH VIH VIL SDIN1/2 Figure 7. Audio Interface (Input Interface in Master Mode) LRCK 50%DVDD tLRD BICK 50%DVDD tLRD tBSOD tBSOD 50%DVDD SDOUT1/2/3 Figure 8. Audio Interface (Output Interface in Master Mode) MS1489-E-02-PB - 19 - 2013/07 [AK7757] VIH CSN VIL tWRF tWRR tSF tSR VIH SCLK VIL tSCLKL tSCLKH 1/fSCLK 1/fSCLK VIH IRSTN VIL VIH CSN VIL tRST1 tIRRQ Figure 9. μP Interface 1 (SPI) VIH CSN tWRQH VIL VIH SI VIL tSIS tSIH VIH SCLK VIL tWSC tSCW tWSC tSCW Figure 10. μP Interface 2 (SPI) MS1489-E-02-PB - 20 - 2013/07 [AK7757] VIH SCLK VIL VIH SO VIL tSOH tSOS Figure 11. μP Interface 3 (SPI) VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 12. μP Interface (I2C Bus) MS1489-E-02-PB - 21 - 2013/07 [AK7757] PACKAGE 48pin LQFP(Unit: mm) 1.70Max 9.0 0.13 ± 0.13 7.0 36 1.40 ± 0.05 24 48 13 7.0 37 1 9.0 25 12 0.09 ∼ 0.20 0.5 0.22 ± 0.08 0.10 M 0° ∼ 10° S 0.10 S 0.30 ~ 0.75 ■ Materials and Lead Specification Package: Lead frame: Lead-finish: MS1489-E-02-PB Epoxy Copper Soldering (Pb free) plate - 22 - 2013/07 [AK7757] MARKING AK7757VQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7digits) 3) Marking Code: AK7757VQ REVISION HISTORY Date (Y/M/D) 13/01/24 13/05/17 13/07/10 Revision 00 01 02 MS1489-E-02-PB Reason First Edition Error Correction Specification Change Error Correction Page Contents 12 DC CHARACTERISTICS Note 16 was changed. ■ μP Interface (SPI mode) μP Interface Timing (SPI mode) SCLK Frequency: 2.1 → 2.7MHz (max) SCLK Low Level Width: 200 → 180ns (min) SCLK High Level Width: 200 → 180ns (min) SI Latch Setup Time: 200 → 180ns (min) SI Latch Hold Time: 200 → 180ns (min) AK7757 →μP Delay Time from SCLK “↓” to SO Output: 200→180ns(max) Hold Time from SCLK “↑” to SO Output: 200→180ns (min) PIN FUNCTION Pin No.37~40: “Differential Analog Output Pin” → “Analog Output Pin” 16 6 - 23 - 2013/07 [AK7757] Thank you for your access to AKM product information. More detail product information is available, please contact our sales office or authorized distributors. IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information cont ained in this document without notice. When you consider any use or application of AKM product stipulat ed in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors a s to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application exam ples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or c ompleteness of the information contained in this document nor grants any license to any intellectual propert y rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human l ife, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used fo r automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control c ombustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equ ipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by A KM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for co mplying with safety standards and for providing adequate designs and safeguards for your hardware, softwar e and systems which minimize risk and avoid situations in which a malfunction or failure of the Product c ould cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stoc kpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in th is document, you should comply with the applicable export control laws and regulations and follow the pro cedures required by such laws and regulations. The Products and related technology may not be used for o r incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applica ble domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatib ility of the Product. Please use the Product in compliance with all applicable laws and regulations that regu late the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AK M assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or e xtend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior writte n consent of AKM. MS1489-E-02-PB - 24 - 2013/07