VBUS052CD-FAH www.vishay.com Vishay Semiconductors 2-Line BUS-Port ESD-Protection - Flow Through Design FEATURES NC NC GND 6 5 4 • Compact LLP1713-7L package • Low package height < 0.6 mm • 2-line ESD-protection 7 1 21325 D+ 2 D- • Low leakage current IR < 0.1 μA • Low load capacitance CD = 0.8 pF 3 • Ideal for high speed data line like - HDMI, DisplayPort, eSATA - USB, 1394/firewire GND 21323 • ESD-protection acc. IEC 61000-4-2 ± 15 kV contact discharge ± 15 kV air discharge MARKING (example only) • Soldering can be checked by standard vision inspection. No X-ray necessary YXX 20719 • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) Dot = pin 1 marking Y = type code (see table below) XX = date code • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 ORDERING INFORMATION ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VBUS052CD-FAH-GS08 3000 15 000 DEVICE NAME VBUS052CD-FAH PACKAGE DATA DEVICE NAME PACKAGE NAME VBUS052CD-FAH LLP1713-7L TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS G 3.7 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals ABSOLUTE MAXIMUM RATINGS VBUS052CD-FAH PARAMETER Peak pulse current Peak pulse power ESD immunity Operating temperature Storage temperature Rev. 1.4, 16-Jul-15 TEST CONDITIONS SYMBOL VALUE UNIT Acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 3.5 A Acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP 63 W Contact discharge acc. IEC 61000-4-2; 10 pulses VESD ± 15 kV Air discharge acc. IEC 61000-4-2; 10 pulses VESD ± 15 kV Junction temperature TJ -40 to +125 °C TSTG -55 to +150 °C Document Number: 81881 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS052CD-FAH www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS VBUS052CD-FAH (pin 1 or 2 to pin 3, 4 or 7) (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of line which can be protected Nchannel - - 2 lines Max. reverse working voltage VRWM - - 5 V Reverse voltage at IR = 0.1 μA VR 5 - - V Reverse current at VRWM = 5 V IR - < 0.01 0.1 μA at IR = 1 mA VBR 6.9 7.9 8.7 V at IPP = 1 A VC - 10 12 V at IPP = IPPM = 3.5 A VC - 15 18 V at IF = 1 A VF - 1.9 2.4 V at IPP = IPPM = 3.5 A VF - 4 5 V at VR = 0 V; f = 1 MHz CD - 0.8 1 pF Protection paths Reverse stand-off voltage Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage Capacitance APPLICATION NOTE The VBUS052CD-FAH is a two-line ESD-protection device with the characteristic of a Z-diode with a high ESD immunity and a very low capacitance which makes it usable for high frequency applications like USB2.0 or HDMI. With the VBUS052CD-FAH two high speed data lines can be protected against transient voltage signals like ESD (Electro Static Discharge). Connected to the data line (pin 1 and pin 2) and to ground (pin 3) negative transients will be clamped close below the ground level while positive transients will be clamped close above the 5 V working range. The clamping behaviour of the VBUS052CD-FAH is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up to 5 V. Pin configuration: • Pin 3, 4 and 7 are internally shorted and have to be connected to ground • Pin 1 and 2 are the inputs for the data lines D+ and D• Pin 5 and 6 are not connected internally NC GND 6 5 4 USB/HDMI interface D+ 7 1 21325 D+ 2 D- Dmatched pair NC 6 3 5 GND 4 7 1 D+ 2 3 D - GND I/O port connector 21327 FLOW THROUGH DESIGN Modern digital transmission lines can be clocked up to 480 Mbit/s (USB2.0) or 1.65 Gbit/s (HDMI). At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected to the data lines - like ESD-protection devices - have to be connected with minimal changes in these trace dimensions and distances. With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the VBUS052CD-FAH is placed on top without any vias or loops. Rev. 1.4, 16-Jul-15 Document Number: 81881 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS052CD-FAH www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 100 120 % Rise time = 0.7 ns to 1 ns Discharge Current IESD 100 % 10 80 % IF (mA) 1 60 % 53 % 0.1 40 % Pin 3 to pin 1 or 2 27 % 0.01 20 % 0.001 0.5 0% -10 0 10 20 30 40 50 60 70 80 90 100 Time (ns) 20557 0.6 0.7 0.8 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 0.9 1 1.1 VF (V) 21478 Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF 9 8 µs to 100 % 100 % 8 7 80 % VR (V) 6 IPPM 60 % 20 µs to 50 % 40 % Pin 1 or 2 to pin 3 5 4 3 2 20 % 1 0% 0 10 20 30 0 0.01 40 Time (µs) 20548 Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 1.0 1 10 100 1000 10 000 IR (µA) Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 18 f = 1 MHz 0.9 Measured acc. IEC 61000-4-5 (8/20µs - wave form) 16 Pin 2 at 0 V 0.8 14 0.7 0.6 0.5 Pin 1 or 2 to pin 3 12 Pin 2 at 3 V VC (V) CD (pF) 0.1 21479 Pin 2 at 5 V 0.4 10 VC 8 6 0.3 0.2 4 0.1 2 Pin 3 to pin 1 or 2 0 0 0 21480 1 2 3 4 VR at Pin 1 (V) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.4, 16-Jul-15 0 5 21481 1 2 3 4 5 IPP (A) Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Document Number: 81881 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS052CD-FAH www.vishay.com Vishay Semiconductors 120 Acc. IEC 61000-4-2 + 8 kV contact discharge 100 80 VC-ESD (V) 60 40 20 0 - 20 - 40 - 10 0 10 20 30 40 50 60 70 80 90 21528 t (ns) Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 20 0 - 20 VC-ESD (V) - 40 - 60 Acc. IEC 61000-4-2 - 8 kV contact discharge - 80 - 100 - 120 - 140 - 160 - 180 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) 21529 Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) 200 Positive discharge 150 100 Acc. IEC 61000-4-2 contact discharge VC-ESD (V) 50 0 - 50 VC-ESD - 100 - 150 - 200 Negative discharge - 250 - 300 0 21530 5 10 15 20 VESD (kV) Fig. 9 - Typical Peak Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) Rev. 1.4, 16-Jul-15 Document Number: 81881 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS052CD-FAH www.vishay.com Vishay Semiconductors PACKAGE DIMENSIONS in millimeters (inches): LLP1713-7L 0.5 (0.020) bsc 0.4 (0.016) 0.25 (0.010) 0.19 (0.007) 0.28 (0.011) 0.22 (0.009) 1 (0.039) ref. 1.4 (0.055) 0.6 (0.024) 1.75 (0.069) 1.65 (0.065) 0.5 (0.020) 0.152 (0.006) ref. 0 (0.000) 0.05 (0.002) 1.3 (0.051) Pin 1 marking Foot print recommendation: 1 (0.039) 0.22 (0.009) 0.37 (0.015) 0.15 (0.006) Document no.:S8-V-3906.04-008 (4) Created - Date: 15. April 2008 Rev. 2 - Date: 09. Sep. 2008 0.25 (0.010) 0.4 (0.016) 0.5 (0.020) Solder resist mask Solder pad 21329 Rev. 1.4, 16-Jul-15 Document Number: 81881 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS052CD-FAH www.vishay.com Vishay Semiconductors Pin 1 - location LLP1713 Top view Rev. 1.4, 16-Jul-15 Pad layout - view from top seen at bottom side Document Number: 81881 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000