VISHAY VESD05A8A-HNH

VESD05A8A-HNH
www.vishay.com
Vishay Semiconductors
8-Line ESD-Protection Diode Array in LLP1713-9L
FEATURES
1
• Ultra compact LLP1713-9L package
8
9
2
7
3
6
4
5
• Low package profile < 0.6 mm
• 8-line ESD-protection
• Low leakage current IR < 1 μA
• Low load capacitance CD = 30 pF
20522
20521
• ESD-immunity acc. IEC 61000-4-2
± 25 kV contact discharge
± 30 kV air discharge
MARKING (example only)
• Working voltage range VRWM = 5 V
YXX
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
20719
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
Dot = pin 1 marking
Y = type code (see table below)
XX = date code
ORDERING INFORMATION
DEVICE NAME
VESD05A8A-HNH
ORDERING CODE
TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL)
MINIMUM ORDER QUANTITY
VESD05A8A-HNH-GS08
3000
15 000
PACKAGE DATA
DEVICE NAME
PACKAGE
NAME
TYPE
CODE
WEIGHT
MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VESD05A8A-HNH
LLP1713-9L
B
3.7 mg
UL 94 V-0
MSL level 1
(according J-STD-020)
260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS
RATING
Peak pulse current
Peak pulse power
ESD immunity
Operating temperature
Storage temperature
Rev. 1.5, 26-Jun-12
TEST CONDITIONS
SYMBOL
VALUE
UNIT
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9)
acc. IEC 61000-4-5; tP = 8/20 μs; single shot
IPPM
5
A
BiSy-mode: each input (pin 1 to pin 8) to any other input pin.
Pin 9 not connected. Acc. IEC 61000-4-5; tP = 8/20 μs/single shot
IPPM
2.5
A
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9)
acc. IEC 61000-4-5; tP = 8/20 μs; single shot
PPP
65
W
BiSy-mode: each input (pin 1 to pin 8) to any other input pin
Pin 9 not connected. Acc. IEC 61000-4-5; tP = 8/20 μs/single shot
PPP
33
W
Contact discharge acc. IEC61000-4-2; 10 pulses
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9)
VESD
± 25
kV
Air discharge acc. IEC61000-4-2; 10 pulses
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9)
VESD
± 30
kV
Contact discharge acc. IEC61000-4-2; 10 pulses
BiSy-mode: each input (pin 1 to pin 8) to any other input pin.
Pin 9 not connected.
VESD
± 12
kV
Air discharge acc. IEC61000-4-2; 10 pulses
BiSy-mode: each input (pin 1 to pin 8) to any other input pin.
Pin 9 not connected.
VESD
± 12
kV
TJ
- 40 to + 125
°C
TSTG
- 55 to + 150
°C
Junction temperature
Document Number: 81629
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8A-HNH
www.vishay.com
Vishay Semiconductors
BiAs-MODE (8-line bidirectional asymmetrical protection mode)
With the VESD05A8A-HNH up to 8 signal- or data-lines (L1 to L8) can be protected against voltage transients. With pin 9
connected to ground and pin 1 up to pin 8 connected to a signal- or data-line which has to be protected. As long as the voltage
level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the
protection diode between data line and ground offer a high isolation to the ground line. The protection device behaves like an
open switch.
As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode
becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The
clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance
(resistance and inductance) of the protection device.
Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of
the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level.
Due to the different clamping levels in forward and reverse direction the VESD05A8A-HNH clamping behaviour is bidirectional
and ssymmetrical (BiAs).

L1
L2
L3
L4
1
8
9
2
7
3
6
4
5
L8
L7
L6
L5
20524
ELECTRICAL CHARACTERISTICS (Between pin 1 to 8 and pin 9) 
(Tamb = 25 °C, unless otherwise specified)
TEST CONDITIONS/REMARKS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Number of lines which can be protected
Nchannel
-
-
8
lines
Max. reverse working voltage
VRWM
-
-
5
V
Reverse voltage
at IR = 1 μA
VR
5
-
-
V
Reverse current
at VR = VRWM = 5 V
IR
-
< 0.1
1
μA
PARAMETER
Protection paths
Reverse stand-off voltage
at IR = 1 mA
VBR
6
8
V
Reverse clamping voltage
at IPP = 5 A acc. IEC 61000-4-5
VC
-
13
V
Forward clamping voltage
at IF = 5 A acc. IEC 61000-4-5
VF
-
4.5
V
at VR = 0 V; f = 1 MHz
CD
-
30
35
pF
at VR = 2.5 V; f = 1 MHz
CD
-
18
23
pF
Reverse breakdown voltage
Capacitance
Rev. 1.5, 26-Jun-12
Document Number: 81629
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8A-HNH
www.vishay.com
Vishay Semiconductors
If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the VESD05A8A-HNH can also be used
in parallel in order to “multiply” the performance. If two diodes are switched in parallel you get
• double surge power = double peak pulse current (2 x IPPM)
• half of the line inductance = reduced clamping voltage
• half of the line resistance = reduced clamping voltage
• double line capacitance (2 x CD)
• double reverse leakage current (2 x IR)

L1
1
L4
8
9
L2
2
7
3
6
4
5
L3
20525
BiSy-MODE (7-line bidirectional symmetrical protection mode)
If a bipolar symmetrical protection device is needed the VESD05A8A-HNH can also be used as a seven-line protection device.
Therefore seven pins (example: pin 1, 2, 3, 4, 6, 7 and 8) has to be connected to the signalor data-line (L1 to L7) and pin 5 to
ground. Pin 9 must not be connected!
Positive and negative voltage transients will be clamped in the same way. The clamping current from one data line through the
VESD05A8A-HNH to the ground passes one diode in forward direction and the other one in reverse direction. The clamping
voltage (VC) is defined by the breakthrough voltage (VBR) level of one diode plus the forward voltage of the other diode plus the
voltage drop at the series impedances (resistances and inductances) of the protection device.
Due to the same clamping levels in positive and negative direction the VESD05A8A-HNH voltage clamping behaviour is also
bidirectional and symmetrical (BiSy).
L1
L2
L3
L4
1
8
9
2
7
3
6
4
5
L7
L6
L5
20526_1
ELECTRICAL CHARACTERISTICS (Between any of the pins 1 to 8; pin 9 not connected)
(Tamb = 25 °C, unless otherwise specified)
PARAMETER
Protection paths
Reverse stand-off voltage
TEST CONDITIONS/REMARKS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Number of lines which can be protected
Nchannel
-
-
7
lines
Max. reverse working voltage
VRWM
-
-
5.5
V
Reverse voltage
at IR = 1 μA
VR
5.5
-
-
V
Reverse current
at VR = VRWM = 5.5 V
IR
-
< 0.1
1
μA
at IR = 1 mA
VBR
6.5
8.7
V
at IPP = 2.5 A acc. IEC 61000-4-5
VC
-
13
V
at VR = 0 V; f = 1 MHz
CD
-
30
35
pF
at VR = 2.5 V; f = 1 MHz
CD
-
18
23
pF
Reverse breakdown voltage
Reverse clamping voltage
Capacitance
Rev. 1.5, 26-Jun-12
Document Number: 81629
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8A-HNH
www.vishay.com
Vishay Semiconductors
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
100
Pin 9 to
Pin 1, 2, 3, 4, 5, 6, 7 or 8
8 µs to 100 %
100 %
10
IF (mA)
80 %
IPPM
60 %
20 µs to 50 %
40 %
20 %
1
0.1
0.01
0%
0
10
20
30
Time (µs)
20548
0.001
0.5
40
0.8
0.9
1
VF (V)
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
8
120 %
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
Rise time = 0.7 ns to 1 ns
7
100 %
6
80 %
5
VR (V)
Discharge Current IESD
0.7
20559
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
60 %
53 %
4
3
40 %
2
27 %
20 %
1
0
0.01
0%
- 10 0 10 20 30 40 50 60 70 80 90 100
Fig. 2 - 8/20 µs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
1
14
f = 1 MHz
12
30
1000 10000
positive surge
8
VC (V)
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
15
100
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
10
BiAs-mode
20
10
IR (µA)
Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR
35
25
0.1
20560
Time (ns)
20557
CD (pF)
0.6
6
Measured
acc. IEC 61000-4-5
(8/20 µs - wave form)
4
VC
2
0
10
BiSy-mode
between 2 Pins (1 - 8)
Pin 9 not connetced
5
-2
negative surge
-4
0
-6
0
20558
1
2
3
4
5
6
VR (V)
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Rev. 1.5, 26-Jun-12
0
20561
1
2
3
4
5
6
IPP (A)
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
Document Number: 81629
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8A-HNH
www.vishay.com
Vishay Semiconductors
80
acc. IEC 61000-4-2
+ 8 kV
contact discharge
60
VC-ESD (V)
40
20
0
- 20
- 40
- 10 0
10 20 30 40 50 60 70 80 90
20562
t (ns)
Fig. 7 - Typical Clamping Performance at + 8 kV
Contact Discharge (acc. IEC 61000-4-2)
40
acc. IEC 61000-4-2
- 8 kV
contact discharge
VC-ESD (V)
20
0
- 20
- 40
- 60
- 80
- 10 0 10 20 30 40 50 60 70 80 90
20563
t (ns)
Fig. 8 - Typical Clamping Performance at - 8 kV
Contact Discharge (acc. IEC 61000-4-2)
250
acc. IEC 61000-4-2 contact discharge
200 Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
150
positive discharge
VC-ESD (V)
100
50
VC-ESD
0
- 50
- 100
negative discharge
- 150
- 200
0
20564
5
10
15
20
25
30
VESD (kV)
Fig. 9 - Typical Peak Clamping Voltage at ± ESD Contact Discharge
(acc. IEC 61000-4-2)
Rev. 1.5, 26-Jun-12
Document Number: 81629
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8A-HNH
www.vishay.com
Vishay Semiconductors
PACKAGE DIMENSIONS in millimeters (Inches): LLP1713-9L
1.05 (0.041)
0.3 (0.012)
exp. DAP
0.35 (0.014)
0.45 (0.018)
0.2 (0.008) x 45°
0.24 (0.009)
0.23 (0.009)
0.17 (0.007)
0.4 (0.016) bsc
1.2 (0.047) ref.
1.4 (0.055)
0.6 (0.024)
0.5 (0.020)
1.75 (0.069)
1.65 (0.065)
0.152 (0.006) ref.
0 (0.000)
0.05 (0.002)
1.3 (0.051)
Pin 1 marking
Foot print recommendation:
3 x 0.4 = 1.2 (0.047)
20386
Rev. 1.5, 26-Jun-12
0.4 (0.016)
1 (0.039)
0.2 (0.008)
Solder
resist mask
0.42 (0.017)
Document no.:S8-V-3906.04-001 (4)
Created - Date: 28. August 2006
Rev. 1 - Date: 27. May 2008
0.4 (0.016)
0.15 (0.006)
0.4 (0.016)
Solder pad
Document Number: 81629
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
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Revision: 02-Oct-12
1
Document Number: 91000