X24C45 ® 256 Bit, 16 x 16 Bit Data Sheet June 1, 2005 Serial AUTOSTORE™ NOVRAM FN8104.0 DESCRIPTION FEATURES • AUTOSTORE NOVRAM —Automatically performs a store operation upon loss of VCC • Single 5V supply • Ideal for use with single chip microcomputers —Minimum I/O interface —Serial port compatible (COPS™, 8051) —Easily interfaced to microcontroller ports • Software and hardware control of nonvolatile functions • Auto recall on power-up • TTL and CMOS compatible • Low power dissipation —Active current: 10mA —Standby current: 50µA • 8-lead PDIP and 8-lead SOIC packages • High reliability —Store cycles: 1,000,000 —data retention: 100 years The Intersil X24C45 is a serial 256-bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit-by-bit with a nonvolatile EEPROM array. The X24C45 is fabricated with Intersil’s Advanced CMOS Floating Gate technology. The Intersil NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to EEPROM) is completed in 5ms or less and a recall operation (EEPROM data to RAM) is completed in 2µs or less. The X24C45 also includes the AUTOSTORE feature, a user selectable feature that automatically performs a store operation when VCC falls below a preset threshold. Intersil NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from EEPROM and a minimum 1,000,000 store operations. Inherent data retention is specified to be greater than 100 years. IBLOCK DIAGRAM CE (1) DI (3) SK (2) Column Decode Instruction Register EC R Static RAM 256-Bit Row Decode AL L ST O R E Nonvolatile EEPROM Control Logic RECALL (6) AS (7) DO (4) 4-Bit Counter Instruction Decode 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X24C45 PIN CONFIGURATION PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/write operations. CE must remain HIGH following a Read or Write command until the data transfer is complete. CE LOW places the X24C45 in the low power standby mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an operation in order to reset the instruction register in preparation for the next command. Serial Clock (SK) DIP/SOIC CE 1 SK 2 DI 3 DO 4 X24C45 8 VCC 7 AS 6 RECALL 5 VSS PIN NAMES Symbol Description The Serial Clock input is used to clock all data into and out of the device. CE Chip Enable SK Serial Clock Data In (DI) DI Serial Data In Data In is the serial data input. Data Out (DO) Data Out is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction. DO Serial Data Out RECALL Recall Input AS AUTOSTORE Oput VCC +5V VSS Ground AUTOSTORE Output (AS) AS is an open drain output which, when asserted indicates VCC has fallen below the AUTOSTORE threshold (VASTH). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller or as an input to a low power reset circuit. RECALL RECALL LOW will initiate an internal transfer of data from EEPROM to the RAM array. 2 FN8104.0 June 1, 2005 X24C45 DEVICE OPERATION The X24C45 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation. Table 1. contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address bits (A) or don’t cares (X) and bits 2 through 0 are the operation codes. The X24C45 requires the instruction to be shifted in with the MSB first. After CE is HIGH, the X24C45 will not begin to interpret the data stream until a logic "1" has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X24C45 will begin any action. In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data. RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of EEPROM data into RAM. This software or hardware recall operation sets an internal "previous recall" latch. This latch is reset upon power-up and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon powerup, the previous recall latch is not set by this operation. WRDS and WREN Internally the X24C45 contains a "write enable" latch. This latch must be set for either writes to the RAM or store operations to the EEPROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and EEPROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up. STO The software STO instruction will initiate a transfer of data from RAM to EEPROM. In order to safeguard against unwanted store operations, the following conditions must be true: – STO instruction issued. – The internal "write enable" latch must be set (WREN instruction issued). – The "previous recall" latch must be set (either a software or hardware recall operation). Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations. Table 1. Instruction Set Instruction Format, I2 I1 I0 WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and Stores) STO (Figure 3) 1XXXX001 STORE RAM Data in EEPROM Operation ENAS 1XXXX010 Enable AUTOSTORE Feature WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and Stores) RCL (Figure 3) 1XXXX101 Recall EEPROM Data into RAM READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA 3 FN8104.0 June 1, 2005 X24C45 WRITE AUTOSTORE Feature The WRITE instruction contains the 4-bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. CE must go LOW before the next rising edge of SK. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM. The AUTOSTORE instruction (ENAS) sets the "AUTOSTORE enable" latch, allowing the X24C45 to automatically perform a store operation when VCC falls below the AUTOSTORE threshold (VASTH). If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. The X24C45 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. READ Power-Up Condition The READ instruction contains the 4-bit address of the word to be accessed. Unlike the other six instructions, I0 of the instruction word is a "don’t care". This provides two advantages. In a design that ties both DI and DO together, the absence of an eighth bit in the instruction allows the host time to convert an I/O line from an output to an input. Secondly, it allows for valid data output during the ninth SK clock cycle. Upon power-up the "write enable" and "AUTOSTORE enable" latches are in the reset state, disabling any store operation. D0, the first bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge of the eighth SK clock; whereas, all succeeding bits are clocked by the rising edge of SK (refer to Read Cycle Diagram). LOW POWER MODE When CE is LOW, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. 4 Notes: X = Don't Care A = Address WRITE PROTECTION Unknown Data Store The "previous recall" latch must be set after power-up. It may be set only by performing a software or hardware recall operation, which assures that data in all RAM locations is valid. SYSTEM CONSIDERATIONS Power-Up Recall The X24C45 performs a power-up recall that transfers the EEPROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the "previous recall" latch. During this powerup recall operation, all commands are ignored. Therefore, the host should delay any operations with the X24C45 a minimum of tPUR after VCC is stable. FN8104.0 June 1, 2005 X24C45 Figure 1. RAM Read CE SK 1 2 3 4 5 6 7 8 DI 1 A A A A 1 1 X* 10 9 11 12 22 23 24 HIGH Z DO D2 D1 D0 D3 D13 D14 D15 D0 *Bit 8 of Read Instructions is Don’t Care Figure 2. RAM Write CE SK 1 2 3 4 5 6 7 8 9 10 DI 1 A A A A 0 1 1 D0 D1 11 D2 21 22 23 24 D12 D13 D14 D15 Figure 3. Non-Data Operations CE SK 1 2 3 4 5 6 7 8 DI 1 X X X X I2 I1 I0 5 FN8104.0 June 1, 2005 X24C45 Figure 4. FX24C45 State Diagram Power On Power-Up Recall Power OFF RAM Read Enabled RAM Read RCL Command Or Recall AUTOSTORE Power-down RAM Read Or Write RAM Read & Write Enabled Store Enabled AUTOSTORE Enabled WREN Command 6 STO Or Wrds Cmd RAM Read Enabled WREN Command STO Or Wrds Cmd ENAS Command RAM Read RAM Read & Write Enabled RAM Read Or Write Store Enabled FN8104.0 June 1, 2005 X24C45 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to VSS .................................. -1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ 300°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial 0°C +70°C X24C45 5V ±10% Industrial -40°C +85°C Military -55°C +125°C D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Unit Test Conditions lCC1 VCC supply current (TTL inputs) 10 mA SK = 0.4V/2.4V Levels @ 1MHz, DO = open, All other inputs = VIH lCC2 VCC supply current (during AUTOSTORE) 2 mA All inputs = VIH, CE = VIL DO = open, VCC = 4.3V ISB1 VCC standby current (TTL inputs) 1 mA DO = Open, CE = VIL, All other inputs = VIH ISB2 VCC standby current (CMOS inputs) 50 µA DO = Open, CE = VSS, All other inputs = VCC – 0.3V ILI Input load current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VlL(1) VIH(1) Input LOW voltage -1 0.8 V Input HIGH voltage 2 VCC + 1 V 0.4 V IOL = 4.2mA V IOH = –2mA V IOL(AS) = 1mA VOL Output LOW voltage VOH Output HIGH voltage VOL(AS) 2.4 Output LOW voltage (AS) 0.4 ENDURANCE AND DATA RETENTION Parameter Min. Unit Endurance 100,000 Data changes per bit Store cycles 1,000,000 Store cycles Data retention 100 Years CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT(2) CIN(2) Parameter Max. Unit Test Conditions Output capacitance 8 pF VOUT = 0V Input capacitance 6 pF VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 7 FN8104.0 June 1, 2005 X24C45 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input pulse levels 5V 919Ω 0V to 3V Input rise and fall times 10ns Input and output timing levels 1.5V Output 497Ω 100pF A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read and Write Cycle Limits Symbol FSK(3) Parameter Min. SK frequency Max. Unit 1 MHz tSKH SK positive pulse width 400 ns tSKL SK negative pulse width 400 ns tDS Data setup time 400 ns tDH Data hold time 80 ns tPD1 SK to data bit 0 valid 375 ns tPD SK to data valid 375 ns 1 µs tZ Chip enable to output high Z tCES Chip enable setup 800 ns tCEH Chip enable hold 350 ns tCDS Chip deselect 800 ns POWER-UP TIMING Symbol tPUR Parameter (4) Power-up to read operation (4) Power-up to write or store operation tPUW Max. Unit 200 µs 5 ms Notes: (3) SK rise and fall times must be less than 50ns. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 8 FN8104.0 June 1, 2005 X24C45 Write Cycle 1/F SK SK CYCLE # tSKH SK tSKL x 1 2 n tCEH tCES tCDS CE tDS tDH DI Read Cycle SK CYCLE # 6 7 8 9 10 n SK VIH CE tPD DI I2 I1 DON’T CARE tPD1 High Z DO 9 tZ D0 D1 Dn High Z FN8104.0 June 1, 2005 X24C45 NONVOLATILE OPERATIONS Operation RECALL Software Instruction Write Enable Latch State Previous Recall Latch State Hardware recall 0 NOP(5) X X Software recall 1 RCL X X Software store 1 STO SET SET ARRAY RECALL LIMITS Symbol tRCC Parameter Min. Recall cycle time width(6) tRCP Recall pulse tRCZ Recall to output in high Z Max. Unit 2 µs 500 ns 500 ns Recall Timing tRCC tRCP RECALL tRCZ High Z DO SOFTWARE STORE CYCLE LIMITS Symbol tST Parameter Store time after clock 8 of STO command Min. Typ.(7) Max. Unit 2 5 ms Notes: (5) NOP designates when the X24C45 is not currently executing an instruction. (6) RECALL rise time must be <10µs. (7) Typical values are for TA = 25°C and nominal supply voltage. 10 FN8104.0 June 1, 2005 X24C45 AUTOSTORE CYCLE LIMITS Symbol Parameter Min. tASTO AUTOSTORE cycle time VASTH AUTOSTORE threshold voltage 4.0 VASEND AUTOSTORE cycle end voltage 3.5 Max. Unit 5 ms 4.3 V V AUTOSTORE Cycle Timing Diagrams VCC 5 Volts (V) 4 AUTOSTORE Cycle in Progress VASTH VASEND 3 2 tASTO 1 Store Time Time (ms) VCC VASTH 0V tPUR tASTO tPUR AS SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 11 FN8104.0 June 1, 2005 X24C45 Ordering Information X24C45 P T -V VCC Limits Blank = 5V ± 10% Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C M = Military = -55°C to +125°C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN8104.0 June 1, 2005