X96011 Datasheet

T
ODUC MENT
TE PR
E
CE
L
A
O
L
S
OB
REP
D
E
nt er at
D
or t C e
MEN
p
M
p
sc
O
u
C
S
al Sheet
.com/t
Data
NO RE r Technic
ntersil
.i
u
w
o
w
t
contac TERSIL or w
IN
1- 888-
Temperature Sensor with Look-Up Table
Memory and DAC
The X96011 is a highly integrated bias controller which
incorporates a digitally controlled Programmable Current
Generator and temperature compensation using one look-up
table. All functions of the device are controlled via a 2-wire
digital serial interface.
The temperature compensated Programmable Current
Generator varies the output current with temperature
according to the contents of the associated nonvolatile
look-up table. The look-up table may be programmed with
arbitrary data by the user, via the 2-wire serial port, and an
internal temperature sensor is used to control the output
current response.
Ordering Information
PART
NUMBER
PART
MARKING
TEMP
RANGE (°C)
PACKAGE
PKG.
DWG. #
X96011V14I
X9601 1V I
-40 to +100 14 Ld TSSOP
M14.173
X96011V14IZ
(Note)
X9601 1VIZ
-40 to +100 14 Ld TSSOP
(Pb-free)
M14.173
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
X96011
February 25, 2008
FN8215.2
Features
• Single Programmable Current Generator
- ±1.6mA Max.
- 8-bit (256 Step) Resolution
- Internally Programmable Full Scale Current Outputs
Internal Voltage Reference
• Integrated 8-bit A/D Converter
• Temperature Compensation
- Internal Sensor
- -40°C to +100°C Range
- 2.2°C/step resolution
- EEPROM Look-up Table
• Hot Pluggable
• Write Protection Circuitry
- Intersil BlockLock™
- Logic Controlled Protection
• 2-wire Bus with 3 Slave Address Bits
• 3V to 5.5V, Single Supply Operation
• Package
- 14 LD TSSOP
• Pb-Free available (RoHS Compliant)
Applications
• PIN Diode Bias Control
• RF PA Bias Control
Pinout
• Temperature Compensated Process Control
X96011
(14 LD TSSOP)
TOP VIEW
• Laser Diode Bias Control
• Fan Control
A0
1
14
NC
• Motor Control
A1
2
13
NC
• Sensor Signal Conditioning
A2
3
12
NC
• Data Aquisition Applications
VCC
4
11
VSS
• Gain vs Temperature Control
WP
5
10
NC
• High Power Audio
SCL
6
9
NC
• Open Loop Temperature Compensation
SDA
7
8
IOUT
• Close Loop Current, Voltage, Pressure, Temperature,
Speed, Position Programmable Voltage Sources,
Electronic Loads, Output Amplifiers or Function Generator
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Block Diagram
VOLTAGE
REFERENCE
MUX
ADC
MUX
DAC
IOUT
LOOK-UP
TABLE
TEMPERATURE
SENSOR
CONTROL
AND STATUS
SDA
SCL
WP
2-WIRE
INTERFACE
A2, A1, A0
Pin Description
PIN
NUMBER
PIN
NAME
1
A0
Device Address Select Pin 0. This pin determines the LSB of the device address
required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor.
2
A1
Device Address Select Pin 1. This pin determines the intermediate bit of the device address required to communicate
using the 2-wire interface. The A1 pin has an on-chip pull-down resistor.
3
A2
Device Address Select Pin 2. This pin determines the MSB of the device address required to communicate using the
2-wire interface. The A2 pin has an on-chip pull-down resistor.
4
VCC
Supply Voltage.
5
WP
Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing
any “Write” operation. When HIGH, various areas of the memory can be protected using the Block Lock bits BL1 and
BL0. The WP pin has an on-chip pull-down resistor, which enables the Write Protection when this pin is left floating.
6
SCL
Serial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output
at the SDA pin.
7
SDA
Serial Data. This pin is the 2-wire interface data into or out of the device. It is TTL
compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull up
resistor.
8
IOUT
Current Generator Output. This pin sinks or sources current. The magnitude and direction of the current is fully
programmable and adaptive. The resolution is 8 bits.
9, 10,
12,13,14
NC
No Connect.
11
VSS
Ground.
DESCRIPTION
2
FN8215.2
February 25, 2008
X96011
Absolute Maximum Ratings
Thermal Information
All voltages are referred to VSS.
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -65°C to +100°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on every pin except VCC . . . . . . . . . . . . . . . . . -1.0V to +7V
Voltage on VCC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 5.5V
DC Output Current at pin SDA . . . . . . . . . . . . . . . . . . . 0mA to 5mA
DC Output Current at pins Iout . . . . . . . . . . . . . . . . . . . . . -3 to 3mA
Lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Thermal Resistance (Typical, Note 1)
JA (°C/W)
14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +100°C
Temperature While Writing to Memory . . . . . . . . . . . . .0°C to +70°C
Voltage on VCC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V
Voltage on any other Pin. . . . . . . . . . . . . . . . . . . . . . . . . VCC ± 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
SYMBOL
All typical values are for +25°C ambient temperature and 5V at pin VCC. Maximum and minimum specifications
are over the recommended operating conditions. All voltages are referred to the voltage at pin VSS. Bit 7 in
control register 0 is “1”, while other bits in control registers are “0”. 400kHz TTL input at SCL. SDA pulled to VCC
through an external 2k resistor. 2-wire interface in “standby” (Notes 2 and 3 ). WP, A0, A1, and A2 floating.
MAX
UNIT
Iccstby
Standby Current Into VCC Pin
PARAMETER
IOUT floating, sink mode
TEST CONDITIONS
MIN
TYP
2
mA
Iccfull
Full Operation Current Into VCC Pin
2-wire interface reading from
memory, Iout connected to VSS, DAC
input bytes: FFh
6
mA
Iccwrite
Nonvolatile Write Current Into VCC Pin Average from START condition until tWP
after the STOP condition
WP: Vcc, Iout floating, sink mode
VRef unloaded.
IPLDN
On-chip Pull Down Current At Wp, A0, V(WP), V(A0), V(A1), and V(A2) from
A1,and A2
0V to Vcc
VILTTL
Scl And Sda, Input Low
Voltage
VIHTTL
Scl And Sda, Input High
Voltage
IINTTL
Scl And Sda Input Current
Pin voltage between 0 and VCC, and
SDA as an input.
-1
10
µA
VOLSDA
Sda Output Low Voltage
I(SDA) = 2 mA
0
0.4
V
V(SDA) = VCC
0
100
µA
0
0.2 x VCC
V
0.8 x VCC
VCC
V
100
°C
4
0
1
mA
20
µA
0.8
V
2.0
V
IOHSDA
Sda Output High Current
VILCMOS
Wp, A0, A1, And A2 Input Low Voltage
VIHCMOS
Wp, A0, A1, And A2 Input High
Voltage
TSenseRange
Temperature Sensor Range
TSenseAccuracy
Temperature Sensor Accuracy
VPOR
Power-on Reset Threshold Voltage
1.5
2.8
V
VccRamp
VCC Ramp Rate
0.2
50
mV/µs
VADCOK
Adc Enable Minimum Voltage
2.6
2.8
V
(Note 7)
-40
±2
(Figure 8)
°C
NOTES:
2. The device goes into Standby: 200 ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby tWC after a STOP
that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address
Byte.
3. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
4. This parameter is periodically sampled and not 100% tested.
3
FN8215.2
February 25, 2008
D/A Converter Characteristics (See pg. 5 for standard conditions)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC input Byte = FFh,
Source or sink mode, V(IOUT) is
VCC -1.2V in source mode and 1.2V in
sink mode.
(Notes 5, 6 )
1.56
1.58
1.6
mA
1
1
LSB
-2
2
LSB
-0.5
0.5
LSB
-1
1
LSB
IFS
Iout Full Scale Current
OffsetDAC
Iout D/a Converter Offset Error
FSErrorDAC
Iout D/a Converter Full Scale Error
DNLDAC
Iout D/a Converter
Differential Nonlinearity
INLDAC
Iout D/a Converter Integral
Nonlinearity With Respect To A Straight Line
Through 0 And The Full Scale Value
VISink
I1 Sink Voltage Compliance
In this range the current at I1 vary < 1%
1.2
VCC
V
VISource
I1 Source Voltage Compliance
In this range the current at I1 vary < 1%
0
VCC - 1.2
V
IOVER
I1 Overshoot On D/a Converter Data Byte
Transition
0
µA
IUNDER
I1 Undershoot On D/a Converter Data Byte
Transition
DAC input byte changing from 00h to
FFh and vice versa, V(I1) is VCC - 1.2V
in source mode and 1.2V in sink mode.
(Note 7)
0
µA
trDAC
I1 Rise Time On D/a Converter Data Byte
Transition; 10% To 90%
30
µs
TCOI1I2
Temperature Coefficient Of Output
Current Iout
NOTES:
5. LSB is defined as
5
See Figure 5
[ 23 x V(VRef)
255 ] divided by the resistance between R
1
±200
ppm/°C
or R2 to Vss.
6. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed
in LSB.
FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.
DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output
of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error
before calculating DNLDAC.
INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the
measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
7. These parameters are periodically sampled and not 100% tested.
2-Wire Interface AC Characteristics
SYMBOL
fSCL
PARAMETER
Scl Clock Frequency
TEST CONDITIONS
See Table 2-Wire Interface Test
Conditions on page 5
MIN
1 (Note 10)
TYP
MAX
UNITS
400
kHz
(Figure 1, 2 and 3)
tIN
(Note 11)
Pulse Width Suppression Time At
Inputs
50
ns
tAA
(Note 11)
Scl Low To Sda Data Out Valid
900
ns
tBUF
(Note 11)
Time The Bus Free Before Start Of New
Transmission
tLOW
Clock Low Time
1.3
1200
(Note 10)
µs
tHIGH
Clock High Time
0.6
1200
(Note 10)
µs
tSU:STA
Start Condition Setup Time
600
ns
tHD:STA
Start Condition Hold Time
600
ns
4
1300
ns
FN8215.2
February 25, 2008
2-Wire Interface AC Characteristics (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
ns
0
µs
Stop Condition Setup Time
600
ns
tDH
Data Output Hold Time
50
ns
tR
(Note 11)
Sda And Scl Rise Time
20 + 0.1Cb
(Note 8)
300
ns
tF
(Note 11)
Sda And Scl Fall Time
20 + 0.1Cb
(Note 8)
300
ns
tSU:WP
(Note 11)
Wp Setup Time
600
ns
tHD:WP
(Note 11)
Wp Hold Time
600
ns
Cb
(Note 11)
Capacitive Load For Each Bus Line
tSU:DAT
Data In Setup Time
tHD:DAT
Data In Hold Time
tSU:STO
See Table 2-Wire Interface Test
Conditions on page 5
(Figure 1, 2 and 3)
400
pF
2-Wire Interface Test Conditions
Input Pulse Levels
10% to 90% of VCC
Input Rise and Fall Times, between 10% and 90%
10ns
Input and Output Timing Threshold Level
1.4V
External Load at pin SDA
2.3k to VCC and 100pF to VSS
Nonvolatile WRITE Cycle Timing
SYMBOL
PARAMETER
tWC
(Note 9)
Nonvolatile Write Cycle Time
TEST CONDITIONS
MIN
See Figure 3
TYP
MAX
UNITS
5
10
ms
NOTES:
8. Cb = total capacitance of one bus line (SDA or SCL) in pF.
9. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
10. The minimum frequency requirement applies between a START and a STOP condition.
11. These parameters are periodically sampled and not 100% tested.
Timing Diagrams
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA
tDH
tBUF
SDA OUT
FIGURE 1. BUS TIMING
5
FN8215.2
February 25, 2008
STOP
START
SCL
CLK 1
SDA IN
tSU:WP
tHD:WP
WP
FIGURE 2. WP PIN TIMING
SCL
SDA
8TH BIT OF LAST BYTE
ACK
tWC
START
CONDITION
STOP
CONDITION
FIGURE 3. NON-VOLATILE WRITE CYCLE TIMING
622
Intersil Sensor Conditioner Product Family
FEATURES/FUNCTIONS
DEVICE
TITLE
INTERNAL
EXTERNAL
INTERNAL
VOLTAGE
TEMPERATURE SENSOR
REFERENCE
INPUT
SENSOR
VREF
INPUT/
OUPUT
GENERAL
PURPOSE
EEPROM
LOOK-UP
TABLE
ORGANIZATION
# OF
DACS
FSO
CURRENT
DAC
SETTING
RESISTORS
X96010 Sensor Conditioner
with Dual Look-Up
Table Memory and
DACs
No
Yes
Yes
Yes
No
Dual Bank
Dual
Ext
X96011 Temperature
Sensor with LookUp Table Memory
and DAC
Yes
No
Yes
No
No
Single Bank
Single
Int
X96012 Universal Sensor
Conditioner with
Dual Look-Up Table
Memory and DACs
Yes
Yes
Yes
Yes
Yes
Dual Bank
Dual
Ext / Int
NOTE: FSO = Full Scale Output, Ext = External, Int = Internal
6
FN8215.2
February 25, 2008
Device Description
The combination of the X96011 functionality and Intersil’s
QFN package lowers system cost, increases reliability, and
reduces board space requirements.
The on-chip Programmable Current Generator may be
independently programmed to either sink or source current.
The maximum current generated is determined by using an
externally connected programming resistor, or by selecting
one of three predefined values. Both current generators
have a maximum output of ±1.6 mA, and may be controlled
to an absolute resolution of 0.39% (256 steps/8 bit).
The current generator is driven using either an on-board
temperature sensor or control registers. The internal
temperature sensor operates over a very broad temperature
range (-40°C to +100°C). The sensor output drives an 8-bit
A/D converter. The six MSBs of the ADC output selects one
of 64 bytes from the nonvolatile look-up table (LUT).
The contents of the selected LUT row (8-bit wide) drives the
input of an 8-bit D/A converter, which generates the output
current. All control and setup parameters of the X96011,
including the look-up table, are programmable via the 2-wire
serial port.
ADCFILTOFF: ADC FILTERING CONTROL
(NON-VOLATILE)
When this bit is “1”, the status register at 87h is updated after
every conversion of the ADC. When this bit is “0” (default),
the status register is updated after four consecutive
conversions with the same result, on the 6 MSBs.
NV13: CONTROL REGISTERS 1 AND 3 VOLATILITY
MODE SELECTION BIT (NON-VOLATILE)
When the NV13 bit is set to “0” (default), bytes written to
Control registers 1 and 3 are stored in volatile cells, and their
content is lost when the X96011 is powered down. When the
NV13 bit is set to “1”, bytes written to Control registers 1 and
3 are stored in both volatile and nonvolatile cells, and their
value doesn’t change when the X96011 is powered down
and powered back up. See “Writing to Control Registers” on
page 16.
IDS: CURRENT GENERATOR DIRECTION SELECT BIT
(NON-VOLATILE)
The IDS bit sets the polarity of the Current Generator. When
this bit is set to “0” (default), the Current Generator of the
X96011 is configured as a Current Source. The Current
Generator is configured as a Current Sink when the IDS bit
is set to “1”. See Figure 5.
Principles of Operation
Control and Status Registers
The Control and Status Registers provide the user with a
mechanism for changing and reading the value of various
parameters of the X96011. The X96011 contains five
Controls, one Status, and several Reserved registers, each
being one Byte wide (See Figure 4). The Control registers 0
through 6 are located at memory addresses 80h through 86h
respectively. The Status register is at memory address 87h,
and the Reserved registers at memory address 82h, 84h,
and 88h through 8Fh.
All bits in Control register 6 always power-up to the logic state
“0”. All bits in Control registers 0 through 5 power-up to the
logic state value kept in their corresponding nonvolatile
memory cells. The nonvolatile bits of a register retain their
stored values even when the X96011 is powered down, then
powered back up. The nonvolatile bits in Control 0 through
Control 5 registers are all preprogrammed to the logic state “0”
at the factory, except the cases that indicate “1” in Figure 1.
Bits indicated as “Reserved” are ignored when read, and
must be written as “0”, if any Write operation is performed to
their registers.
A detailed description of the function of each of the Control
and Status register bits follows.
Control Register 0
This register is accessed by performing a Read or Write
operation to address 80h of memory.
7
FN8215.2
February 25, 2008
BYTE
ADDRESS
80h
NON-VOLATILE
MSB
LSB
7
6
5
4
1
IDS
NV13
ADCfiltOff
Iout
Direction
0: Source
1: Sink
CONTROL
1, 3
VOLATILITY
0: VOLATILE
1: NONVOLATILE
ADC
filtering
0: On
1: Off
3
2
1
0
REGISTER
NAME
0
0
0
0
CONTROL 0
LDA4
LDA3
LDA2
LDA1
LDA0
CONTROL 1
CONTROL 3
DIRECT ACCESS TO THE LUT
81h
VOLATILE OR
NON-VOLATILE
RESERVED RESERVED
LDA5
DIRECT ACCESS TO THE DAC
83h
VOLATILE OR
NON-VOLATILE
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
85h
NON-VOLATILE
0
0
DDAS
LDAS
0
0
IFSO1
IFSO 0
Direct
Access
to dac
0: Disabled
1: Enabled
Direct
Access
to lut
0: Disabled
1: Enabled
86h
VOLATILE
WEL
CONTROL 5
R Selection
00: Reserved
01: Low Internal
10: Middle Internal
11: High Internal (Default)
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
CONTROL 6
Write Enable
Latch
0: Write
Disabled
1: Write
Enabled
ADC OUTPUT
87H
VOLATILE
AD6
AD7
AD5
AD4
AD3
AD2
AD1
AD0
STATUS
REGISTERS IN BYTE ADDRESSES 82H, 84H, AND 88H THROUGH 8FH ARE RESERVED.
REGISTERS BITS SHOWN AS 0 OR 1 SHOULD ALWAYS USE THESE VALUES FOR PROPER OPERATION.
FIGURE 4. CONTROL AND STATUS REGISTER FORMULA
8
FN8215.2
February 25, 2008
X96011
Control Register 1
WEL: WRITE ENABLE LATCH (VOLATILE)
This register is accessed by performing a Read or Write
operation to address 81h of memory. This byte’s volatility is
determined by bit NV13 in Control register 0.
The WEL bit controls the Write Enable status of the entire
X96011 device. This bit must be set to “1” before any other
Write operation (volatile or nonvolatile). Otherwise, any
proceeding Write operation to memory is aborted and no ACK
is issued after a Data Byte.
LDA5 - LDA0: LUT DIRECT ACCESS BITS
When bit LDAS (bit 4 in Control register 5) is set to “1”, the LUT
is addressed by these six bits, and it is not addressed by the
output of the on-chip A/D converter. When bit LDAS is set to
“0”, these six bits are ignored by the X96011. See Figure 7.
• The WEL bit is a volatile latch that powers up in the “0”
state (disabled). The WEL bit is enabled by writing
100000002 to Control register 6. Once enabled, the WEL
bit remains set to “1” until the X96011 is powered down,
and then up again, or until it is reset to “0” by writing
000000002 to Control register 6.
A value between 00h (0010) and 3Fh (6310) may be written to
these register bits, to select the corresponding row in the
LUT. The written value is added to the base address of the
LUT (90h).
A Write operation that modifies the value of the WEL bit will not
cause a change in other bits of Control register 6.
Control Register 3
Status Register - ADC Output
This register is accessed by performing a Read or Write
operation to address 83h of memory. This byte’s volatility is
determined by bit NV13 in Control register 0.
This register is accessed by performing a Read operation to
address 87h of memory.
DDA7 - DDA0: D/A DIRECT ACCESS BITS
AD7 - AD0: A/D CONVERTER OUTPUT BITS (READ
ONLY)
When bit DDAS (bit 5 in Control register 5) is set to “1”, the
input to the D/A converter is the content of bits DDA7-DDA0,
and it is not a row of LUT. When bit DDAS is set to “0” (default)
these eight bits are ignored by the X96011. See Figure 6.
This byte is the binary output of the on-chip digital
thermometer. The output is 000000002 for -40°C and
111111112 for +100°C. The six MSBs select a row of the LUT.
Look-Up Table
Control Register 5
This register is accessed by performing a Read or Write
operation to address 85h of memory.
IFSO1 - IFSO0: CURRENT GENERATOR FULL SCALE
OUTPUT SET BITS (NON-VOLATILE)
These two bits are used to set the full scale output current at
the Current Generator pin, Iout, according to the following
table. The direction of this current is set by bit IDS in Control
register 0. See Figure 5.
I1FSO1
I1FSO0
I1 Full Scale Output Current
0
0
Reserved (Don’t Use)
0
1
0.4mA
1
0
0.85 mA
1
1
1.3 mA (Default)
LDAS: LUT DIRECT ACCESS SELECT BIT
(NON-VOLATILE)
When bit LDAS is set to “0” (default), the LUT is addressed
by the output of the on-chip A/D converter. When bit LDAS is
set to “1”, LUT is addressed by bits LDA5 - LDA0.
DDAS: D/A DIRECT ACCESS SELECT BIT
(NON-VOLATILE)
When bit DDAS is set to “0” (default), the input to the D/A
converter is a row of the LUT. When bit DDAS is set to “1”,
that input is the content of the Control register 3.
Control Register 6
This register is accessed by performing a Read or Write
operation to address 86h of memory.
9
The X96011 memory array contains a 64-byte look-up table.
The look-up table is associated to pin Iout’s output current
generator through the D/A converter. The output of the look-up
table is the byte contained in the selected row. By default this
byte is the input to the D/A converter driving pin IOUT.
The byte address of the selected row is obtained by adding
the look-up table base address 90h, and the appropriate row
selection bits. See Figure 6.
By default the look-up table selection bits are the 6
MSBs of the digital thermometer output. Alternatively, the
A/D converter can be bypassed and the six row selection
bits are the six LSBs of Control Register 1 for the LUT.
The selection between these options is illustrated in
Figure 6.
Current Generator Block
The Current Generator pin Iout is the output of the current
mode D/A converter.
D/A Converter Operation
The Block Diagram for the D/A converter is shown in
Figure 5.
The input byte of the D/A converter selects a voltage on the
non-inverting input of an operational amplifier. The output of
the amplifier drives the gate of a FET. This node is also fed
back to the inverting input of the amplifier. The drain of the
FET is connected to the output current pin (IOUT) via a
“polarity select” circuit block.
FN8215.2
February 25, 2008
VCC
POLARITY
SELECT
CIRCUIT
IDS: BIT
6 IN CONTROL
REGISTER 0.
DAC
INPUT BYTE
VOLTAGE
DIVIDER
+
-
IFSO[1:0]
BITS 1 AND 0
IN CONTROL
REGISTER 5
11
HIGH_CURRENT
MIDDLE_CURRENT
10
01
LOW_CURRENT
INTERNAL
REFERENCE
VOLTAGE
IOUT PIN
VSS
VSS
VSS
FIGURE 5. D/A CONVERTER BLOCK DIAGRAM
DDA[7:0] : Control register 3
6
8
90h
A
D
D
E
R
8
…
LUT Row
Selection bits
LUT
CFh
8
8
D1
D0 Out
DAC
Input Byte
Select
90h
DDAS: Bit 5 of
Control register 5
FIGURE 6. LOOK-UP TABLE (LUT) OPERATION
VOLTAGE
REFERENCE
LDA[5:0]:
CONTROL
REGISTER 1
6
ADC
VOLTAGE INPUT
FROM INTERNAL
TEMPERATURE
SENSOR
6
8
AD[7:0]
STATUS
REGISTER
D1
OUT
D0
SELECT
LUT ROW
SELECTION BITS
LDAS: BIT 4 IN
CONTROL REGISTER 5
FIGURE 7. LOOK-UP TABLE ADDRESSING
10
FN8215.2
February 25, 2008
By examining the block diagram in Figure 5, we see that the
maximum current through pin IOUT is set by fixing values for
V(VRef) and R. The output current can then be varied by
changing the data byte at the D/A converter input.
Bit DDAS is used to bypass the A/D converter and look-up
table, allowing direct access to the input of the D/A converter
with the byte in control register 3. See Figure 6, and the
descriptions of the control bits.
In general, the magnitude of the current at the D/A converter
output pin may be calculated by Equation 1:
Bit IDS in Control Register 0 select the direction of the
current through pin Iout. See Figure 5, and the descriptions
of the control bits.
(EQ. 1)
I = (V(VRef) / (384 * R)) *N
where N is the decimal representation of the input byte to the
corresponding D/A converter.
The value for the resistor determines the full scale output
current that the D/A converter may sink or source. Bits
IFSO1 and IFSO0 select the full scale output current setting
for Iout as described in “IFSO1 - IFSO0: Current Generator
Full Scale Output Set Bits (Non-volatile)” on page 9.
Bit IDS and in control register 0 select the direction of the
currents through pins Iout (See “IDS: Current Generator
Direction Select Bit (Non-volatile)” on page 7, and )“The IDS
bit sets the polarity of the Current Generator. When this bit is
set to “0” (default), the Current Generator of the X96011 is
configured as a Current Source. The Current Generator is
configured as a Current Sink when the IDS bit is set to “1”.
See Figure 5.”
D/A Converter Output Current Response
Power-on Reset
When power is applied to the VCC pin of the X96011, the device
undergoes a strict sequence of events before the current
outputs of the D/A converters are enabled.
When the voltage at VCC becomes larger than the power-on
reset threshold voltage (VPOR), the device recalls all control
bits from non-volatile memory into volatile registers. Next,
the analog circuits are powered up. When the voltage at VCC
becomes larger than a second voltage threshold (VADCOK),
the ADC is enabled. In the default case, after the ADC
performs four consecutive conversions with the same exact
result, the ADC output is used to select a byte from the
look-up table. The byte becomes the input of the DAC.
During all the previous sequence the input of the DAC is
00h. If bit ADCfiltOff is “1”, only one ADC conversion is
necessary. Bit DDAS and LDAS, also modify the way the
DAC is accessed the first time after power-up, as described
in “Control Register 5” on page 9.
When the D/A converter input data byte changes by an
arbitrary number of bits, the output current changes from an
intial current level (Ix) to some final level (Ix + Ix). The
transition is monotonic and glitchless.
The X96011 is a hot pluggable device. Voltage distrubances
on the VCC pin are handled by the power-on reset circuit,
allowing proper operation during hot plug-in applications.
D/A Converter Control
Serial Interface
The data byte inputs of the D/A converters can be controlled
in three ways:
Serial Interface Conventions
3) Bypassing both the A/D converter and look-up tables, and
directly setting the D/A converter input byte
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. The X96011
operates as a slave in all applications.
The options are summarized in Table 1.
Serial Clock and Data
1) With the A/D converter and through the look-up tables
(default)
2) Bypassing the A/D converter and directly accessing the
look-up tables
TABLE 1. D/A CONVERTER ACCESS SUMMARY
LDAS
DDAS
CONTROL SOURCE
0
0
A/D converter through LUT
(Default)
1
0
Bits LDA5 - LDA0 through LUT
X
1
Bits DDA7 - DDA0
“X” = Don’t Care Condition (May be either “1” or “0”)
11
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions. See Figure 10.
On power-up of the X96011, the SDA pin is in the input
mode.
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met. See Figure 9.
FN8215.2
February 25, 2008
VOLTAGE
VCC
VADCOK
0V
TIME
CURRENT
Ix
ADC TIME
IX X 10%
TIME
FIGURE 8. CONVERTER POWER-ON RESET RESPONSE
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read sequence.
A STOP condition can only be issued after the transmitting
device has released the bus. See Figure 9.
exception of a “Data Byte” addresses to location 86h; 3)
“Data Bytes” following a “Data Byte” addressed to
locations 80h, 85h, or 86h.
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits
of data. See Figure 11.
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address byte. A
valid Slave Address byte must contain the Device Type
Identifier 1010, and the Device Address bits matching the
logic state of pins A2, A1, and A0. See Figure 13.
If a write operation is selected, the device responds with an
ACK after the receipt of each subsequent eight-bit word.
In the read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
1. The X96011 acknowledges all incoming data and
address bytes except: 1) The “Slave Address Byte” when
the “Device Identifier” or “Device Address” are wrong; 2)
All “Data Bytes” when the “WEL” bit is “0”, with the
12
FN8215.2
February 25, 2008
SCL
SDA
STOP
START
FIGURE 9. VALID START AND STOP CONDITIONS
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 10. VALID DATA CHANGES ON THE BUS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER
13
FN8215.2
February 25, 2008
ADDRESS
CFh
SIZE
1
LOOK-UP TABLE
SA6 SA5
0
1
SA4
SA3
SA2
SA1
0
AS2
AS1
AS0
SA0
R/W
64 Bytes
(LUT)
90h
Device Type
Identifier
8Fh
CONTROL AND STATUS
80h
SA7
Device
Address
Read or
Write
16 Bytes
REGISTERS
FIGURE 12. X96011 MEMORY MAP
X96011 Memory Map
The X96011 contains a 80 byte array of mixed volatile and
nonvolatile memory. This array is split up into two distinct
parts, namely: (Refer to Figure 12).
• Look-up Table (LUT)
• Control and Status Registers
The Control and Status registers of the X96011 are used in
the test and setup of the device in a system. These registers
are realized as a combination of both volatile and nonvolatile
memory. These registers reside in the memory locations 80h
through 8Fh. The reserved bits within registers 80h through
86h, must be written as “0” if writing to them, and should be
ignored when reading. Register bits shown as 0 or 1, in
Figure 4, must be written with the indicated value if writing to
them. The reserved registers, 82h, 84h, and from 88h
through 8Fh, must not be written, and their content should
be ignored.
The LUT is realized as nonvolatile EEPROM, and extend
from memory locations 90h–CFh. This LUT is dedicated to
storing data solely for the purpose of setting the outputs of
Current Generators IOUT.
All bits in the LUT are preprogrammed to “0” at the factory.
Addressing Protocol Overview
All Serial Interface operations must begin with a START,
followed by a Slave Address Byte. The Slave address
selects the X96011, and specifies if a Read or Write
operation is to be performed.
It should be noted that the Write Enable Latch (WEL) bit
must first be set in order to perform a Write operation to any
other bit. See “WEL: Write Enable Latch (Volatile)” on
page 9. Also, all communication to the X96011 over the
2-wire serial bus is conducted by sending the MSB of each
byte of data first.
The memory is physically realized as one contiguous array,
organized as 5 pages of 16 bytes each.
SLAVE ADDRESS
BIT(s)
DESCRIPTION
SA7 - SA4
Device Type Identifier
SA3 - SA1
Device Address
FIGURE 13. SLAVE ADDRESS (SA) FORMAT
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 13). This byte includes
three parts:
• The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order to
select the X96011.
• The next three bits (SA3 - SA1) are the Device Address
bits (AS2 - AS0). To access any part of the X96011’s
memory, the value of bits AS2, AS1, and AS0 must
correspond to the logic levels at pins A2, A1, and A0
respectively.
• The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being addressed.
When the R/W bit is “1”, then a Read operation is
selected. A “0” selects a Write operation
(Refer to Figure 13)
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X96011
initiates an internal high voltage write cycle. This cycle
typically requires 5ms. During this time, any Read or Write
command is ignored by the X96011. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a START
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X96011’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. (Refer to Figure 14)
The X96011 2-wire protocol provides one address byte. The
next few sections explain how to access the different areas
for reading and writing.
14
FN8215.2
February 25, 2008
Byte Write Operation
In order to perform a Byte Write operation to the memory
array, the Write Enable Latch (WEL) bit of the Control 6
Register must first be set to “1”. See “WEL: Write Enable
Latch (Volatile)” on page 9.
BYTE LOAD COMPLETED BY
ISSUING STOP. ENTER ACK POLLING
ISSUE “START”
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
For any Byte Write operation, the X96011 requires the Slave
Address Byte, an Address Byte, and a Data Byte (See Figure
15). After each of them, the X96011 responds with an ACK.
The master then terminates the transfer by generating a
STOP condition. At this time, if all data bits are volatile, the
X96011 is ready for the next read or write operation. If some
bits are nonvolatile, the X96011 begins the internal write cycle
to the nonvolatile memory. During the internal nonvolatile write
cycle, the X96011 does not respond to any requests from the
master. The SDA output is at high impedance.
ISSUE “STOP”
NO
ACK RETURNED?
YES
HIGH VOLTAGE
Writing to Control bytes which are located at byte addresses
80h through 8Fh is a special case described in the section
“Writing to Control Registers” .
NO
COMPLETE. CONTINUE COMMAND
SEQUENCE.
YES
ISSUE “STOP”
CONTINUE NORMAL READ OR
WRITE COMMAND SEQUENCE
PROCEED
FIGURE 14. ACKNOWLEDGE POLLING SEQUENCE
WRITE
SIGNALS FROM
the MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
S
T
A
R
T
10 10
S
T
O
P
DATA
BYTE
ADDRESS
BYTE
SLAVE
ADDRESS
0
A
C
K
A
C
K
A
C
K
FIGURE 15. BYTE WRITE SEQUENCE
15
FN8215.2
February 25, 2008
Page Write Operation
The 80-byte memory array is physically realized as one
contiguous array, organized as 5 pages of 16 bytes each. A
“Page Write” operation can be performed to any of the four
LUT pages. In order to perform a Page Write operation, the
Write Enable Latch (WEL) bit in Control register 6 must first
be set (See “WEL: Write Enable Latch (Volatile)” on page 9.)
A Page Write operation is initiated in the same manner as
the byte write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 16 bytes (See Figure 16). After the receipt of
each byte, the X96011 responds with an ACK, and the
internal byte address counter is incremented by one. The
page address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to the first
byte of the same page.
For example, if the master writes 12 bytes to a 16-byte page
starting at location 11 (decimal), the first 5 bytes are written
to locations 11 through 15, while the last 7 bytes are written
to locations 0 through 6 within that page. Afterwards, the
address counter would point to location 7. If the master
supplies more than 16 bytes of data, then new data
overwrites the previous data, one byte at a time.
(See Figure 17).
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle.
A Page Write operation cannot be performed on the page at
locations 80h through 8Fh. The next section describes the
special cases within that page.
Writing to Control Registers
The bytes at locations 80h, 81h, 83h, 85h, and 86h are
written using Byte Write operations. They cannot be written
using a Page Write operation.
Registers Control 1 and 3 have a nonvolatile and a volatile cell
for each bit. At power-up, the content of the nonvolatile cells is
automatically recalled and written to the volatile cells. The
content of the volatile cells controls the X96011’s functionality.
If bit NV13 in the Control 0 register is set to “1”, a Write
operation to these registers writes to both the volatile and
nonvolatile cells. If bit NV13 in the Control 0 register is set to
“0”, a Write operation to these registers only writes to the
volatile cells. In both cases the newly written values effectively
control the X96011, but in the second case, those values are
lost when the part is powered down.
If bit NV13 is set to “0”, a Byte Write operation to Control
registers 0 or 5 causes the value in the nonvolatile cells of
Control registers 1 and 3 to be recalled into their
corresponding volatile cells, as during power-up. This
doesn’t happen when the WP pin is LOW, because Write
Protection is enabled. It is generally recommended to
configure Control registers 0 and 5 before writing to Control
registers 1 or 3.
WRITE
S
T
A
R
T
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
2 < n < 16
ADDRESS
BYTE
SLAVE
ADDRESS
10 10
SIGNALS FROM
THE SLAVE
DATA BYTE (1)
S
T
O
P
DATA BYTE (n)
0
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 16. PAGE WRITE OPERATION
5 bytes
5 BYTES
7 BYTES
ADDRESS = 0
ADDRESS = 6
ADDRESS = 11
ADDRESS = 7
ADDRESS POINTER
ENDS UP HERE
ADDRESS = 15
FIGURE 17. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11.
16
FN8215.2
February 25, 2008
A “Byte Write” operation to Control register 1 or 3, causes
the value in the nonvolatile cells of the other to be recalled
into the corresponding volatile cells, as during power-up.
issued. If the read operation continues the output bytes are
unpredictable. If the byte address is set between 00h and
7Fh, or higher than CFh, the output bytes are unpredictable.
When reading either of the control registers 1 or 3, the Data
Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV13 is “0” (Figure 5).
A Read operation internal pointer can start at any memory
location from 80h through CFh, when the Address Byte is
80h through CFh respectively.
When reading any of the control registers 1, 2, 3, or 4, the
Data Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV13 is "0". See “IDS: Current
Generator Direction Select Bit (Non-volatile)”. See Figure 5.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Slave Address byte with the R/W bit set to “0”,
an Address Byte, a second START, and a second Slave
Address byte with the R/W bit set to “1”. After each of the
three bytes, the X96011 responds with an ACK. Then the
X96011 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eigth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (Figure 18).
Data Protection
There are three levels of data protection designed into the
X96011: 1- Any Write to the device first requires setting of
the WEL bit in Control 6 register; 2- The Write Protection pin
disables any writing to the X96011; 3- The proper clock count,
data bit sequence, and STOP condition is required in order to
start a nonvolatile write cycle, otherwise the X96011 ignores
the Write operation.
WP: Write Protection Pin
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location CFh a stop should be
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT
SDA
SLAVE
ADDRESS
WITH
ADDRESS
BYTE
R/W = 0
10 10
SLAVE
ADDRESS
WITH
A
C
K
A
C
K
R/W = 1
10 10
0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A
R
T
When the Write Protection (WP) pin is active (LOW), any
Write operations to the X96011 is disabled, except the
writing of the WEL bit. See
S
T
O
P
A
C
K
1
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 18. READ SEQUENCE
17
FN8215.2
February 25, 2008
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
SYMBOL
3
L
0.05(0.002)
-A-
MAX
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
A
D
-C-

e
A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
MIN
c
0.10(0.004)
C A M
B S
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
0.65 BSC

14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN8215.2
February 25, 2008