A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family DESCRIPTION FEATURES AND BENEFITS • AEC-Q100 automotive qualified • Continuous-time operation □□ Fast power-on time □□ Low noise • Stable operation over full operating temperature range • Reverse-battery protection • Solid-state reliability • Factory-programmed at end-of-line for optimum performance • Robust EMC performance • High ESD rating • Regulator stability without a bypass capacitor The Allegro™ A1210-A1214 Hall-effect latches are next generation replacements for the popular Allegro 317x and 318x lines of latching switches. The A121x family, produced with BiCMOS technology, consists of devices that feature fast power-on time and low-noise operation. Device programming is performed after packaging, to ensure increased switchpoint accuracy by eliminating offsets that can be induced by package stress. Unique Hall element geometries and low-offset amplifiers help to minimize noise and to reduce the residual offset voltage normally caused by device overmolding, temperature excursions, and thermal stress. The A1210-A1214 Hall-effect latches include the following on a single silicon chip: voltage regulator, Hall-voltage generator, small-signal amplifier, Schmitt trigger, and NMOS output transistor. The integrated voltage regulator permits operation from 3.8 to 24 V. The extensive on-board protection circuitry makes possible a ±30 V absolute maximum voltage rating for superior protection in automotive and industrial motor commutation applications, without adding external components. All devices in the family are identical except for magnetic switchpoint levels. Packages: 3-Pin SOT23W (suffix LH) 1 3-Pin SIP (suffix UA) The small geometries of the BiCMOS process allow these devices to be provided in ultrasmall packages. The package styles available provide magnetically optimized solutions for most applications. Package LH is an SOT23W, a miniature lowprofile surface-mount package, while package UA is a three-lead ultramini SIP for through-hole mounting. Each package is lead (Pb) free, with 100% matte-tin-plated leadframes. 3 2 1 Not to scale 2 3 VCC To all subcircuits Regulator VOUT Amp Gain Offset Trim Control GND Functional Block Diagram A1210-DS, Rev. 13 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family SPECIFICATIONS Selection Guide Part Number Packing* Mounting A1210ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A1210ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A1210LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A1210LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A1210LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1211LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1212LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A1212LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A1212LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1213LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A1213LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A1213LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1214LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A1214LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A1214LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole Ambient, TA BRP (Min) BOP (Max) –150 150 –40ºC to 150ºC –180 180 –40ºC to 150ºC –175 175 –40ºC to 150ºC –200 200 –40ºC to 150ºC –300 300 –40ºC to 85ºC –40ºC to 150ºC *Contact Allegro for additional packing options. Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Supply Voltage VCC 30 V Reverse Supply Voltage VRCC –30 V Output Off Voltage VOUT 30 V Reverse Output Voltage VROUT –0.5 V 25 mA Unlimited G Output Current IOUTSINK Magnetic Flux Density B Operating Ambient Temperature TA Maximum Junction Temperature Storage Temperature 1 G = 0.1 mT (millitesla) Range E –40 to 85 ºC Range L –40 to 150 ºC TJ(max) 165 ºC Tstg –65 to 170 ºC Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family GND Pin-out Diagrams and Terminal List Table Terminal List Name VCC VOUT GND Number Package LH Package UA 1 1 2 3 3 2 2 3 VOUT VOUT Package LH, 3-Pin SOT23W Pin-out Diagram 1 GND 2 VCC 1 VCC 3 Package UA, 3-Pin SIP Pin-out Diagram Description Connects power supply to chip Output from circuit Ground Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family OPERATING CHARACTERISTICS over full operating voltage and ambient temperature ranges, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Units Electrical Characteristics Supply Voltage1 Output Leakage Current Output On Voltage Power-On Time2 Output Rise Time3 Output Fall Time3 Supply Current Reverse Battery Current VCC Operating, TJ < 165°C 3.8 – 24 V IOUTOFF VOUT = 24 V, B < BRP – – 10 µA VOUT(SAT) IOUT = 20 mA, B > BOP – 215 400 mV Slew rate (dVCC/dt) < 2.5 V/μs, B > BOP + 5 G or B < BRP –5G – – 4 µs tr VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns tf VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns ICCON B > BOP – 4.1 7.5 mA ICCOFF B < BRP – 3.8 7.5 mA VRCC = –30 V – – –10 mA tPO IRCC Supply Zener Clamp Voltage VZ ICC = 10.5 mA; TA = 25°C 32 – – V Supply Zener Current4 IZ VZ = 32 V; TA = 25°C – – 10.5 mA 25 78 150 G 15 87 180 G 50 107 175 G 80 – 200 G 140 – 300 G Magnetic Characteristics5 A1210 A1211 Operate Point BOP A1212 A1213 South pole adjacent to branded face of device A1214 Release Point BRP A1210 –150 –78 –25 G A1211 –180 –95 –15 G –175 –117 –50 G –200 – –80 G A1212 A1213 North pole adjacent to branded face of device A1214 –300 – –140 G A1210 50 155 – G A1211 Hysteresis BHYS 80 180 – G 100 225 350 G A1213 160 – 400 G A1214 280 – 600 G A1212 BOP – BRP 1 Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section. 2 For V CC slew rates greater than 250 V/μs, and TA = 150°C, the Power-On Time can reach its maximum value. 3 C =oscilloscope probe capacitance. S 4 Maximum current limit is equal to the maximum I CC(max) + 3 mA. 5 Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for south-polarity magnetic fields. This so-called alge- braic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the field is indicated by the absolute value of B, and the sign indicates the polarity of the field (for example, a –100 G field and a 100 G field have equivalent strength, but opposite polarity). DEVICE QUALIFICATION PROGRAM Contact Allegro for information. EMC (Electromagnetic Compatibility) REQUIREMENTS Contact Allegro for information. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions RθJA Maximum Allowable VCC (V) Package Thermal Resistance Value Units Package LH, on single layer, single-sided PCB with copper limited to solder pads 228 ºC/W Package LH, on single layer, double-sided PCB with 0.926 in2 copper area 110 ºC/W Package UA on single layer, single-sided PCB with copper limited to solder pads 165 ºC/W Power Derating Curve TJ(max) = 165ºC; ICC = ICC(max) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VCC(max) Low-K PCB, Package LH (RθJA = 110 ºC/W) Minimum-K PCB, Package UA (RθJA = 165 ºC/W) Minimum-K PCB, Package LH (RθJA = 228 ºC/W) 20 40 60 80 100 120 VCC(min) 140 160 180 Power Dissipation, PD (m W) Temperature (ºC) Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Lo (R w-K PC θJ A = 11 B, P 0 º ac Min C/ ka W ge (R imum ) LH -K θJA = P C 165 B, P ºC/ a cka W) ge UA Min imu m-K (R P θJA = 228 CB, Pa ºC/W ckag e LH ) 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family CHARATERISTIC DATA Supply Current (On) versus Ambient Temperature Supply Current (On) versus Supply Voltage (A1210/11/12/13/14) (A1210/11/12/13/14) 8.0 8.0 7.0 7.0 VCC (V) 5.0 24 3.8 4.0 3.0 ICCON (mA) ICCON (mA) 6.0 6.0 TA (°C) 5.0 –40 25 150 4.0 3.0 2.0 2.0 1.0 1.0 0 0 –50 0 50 TA (°C) 100 150 0 5 20 25 Supply Current (Off) versus Supply Voltage (A1210/11/12/13/14) (A1210/11/12/13/14) 8.0 7.0 7.0 VCC (V) 5.0 24 3.8 4.0 3.0 ICCOFF (mA) 8.0 6.0 ICCOFF (mA) 15 VCC (V) Supply Current (Off) versus Ambient Temperature 6.0 TA (°C) 5.0 –40 25 150 4.0 3.0 2.0 2.0 1.0 1.0 0 0 –50 0 50 TA (°C) 100 0 150 5 10 15 20 25 VCC (V) Output Voltage (On) versus Ambient Temperature Output Voltage (On) versus Supply Voltage (A1210/11/12/13/14) (A1210/11/12/13/14) 400 400 350 350 300 300 250 VCC (V) 200 24 3.8 150 VOUT(SAT) (mV) VOUT(SAT) (mV) 10 –40 25 150 200 150 100 100 50 50 0 TA (°C) 250 0 –50 0 50 TA (°C) 100 150 0 5 10 15 20 25 VCC (V) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family Operate Point versus Ambient Temperature Operate Point versus Supply Voltage (A1210) (A1210) 150 150 125 VCC (V) BOP (G) 100 24 3.8 75 TA (°C) –40 25 150 100 BOP (G) 125 50 75 50 25 –50 25 0 50 TA (°C) 100 150 0 15 20 25 Release Point versus Supply Voltage (A1210) (A1210) -25 -25 -50 VCC (V) -75 24 3.8 -100 -125 TA (°C) –40 25 150 -75 BRP (G) -50 BRP (G) 10 VCC (V) Release Point versus Ambient Temperature -100 -125 -150 -150 –50 0 50 TA (°C) 100 0 150 5 10 15 20 25 VCC (V) Hysteresis versus Ambient Temperature Hysteresis versus Supply Voltage (A1210) (A1210) 225 225 200 200 VCC (V) 150 24 3.8 125 175 150 –40 25 150 125 100 100 75 75 50 TA (°C) BHYS (G) 175 BHYS (G) 5 50 –50 0 50 TA (°C) 100 150 0 5 10 15 20 25 VCC (V) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family Operate Point versus Ambient Temperature Operate Point versus Ambient Temperature (A1211) (A1212) 175 165 150 125 140 115 24 3.8 90 BOP (G) BOP (G) VCC (V) 100 VCC (V) 75 24 3.8 50 25 65 0 40 -25 15 –50 -50 0 50 TA (°C) 100 150 –50 50 TA (°C) 100 150 Release Point versus Ambient Temperature Release Point versus Ambient Temperature (A1211) (A1212) -50 -30 -55 -75 VCC (V) -80 24 3.8 -105 VCC (V) BRP (G) BRP (G) 0 -100 24 3.8 -125 -130 -150 -155 -175 -180 –50 0 50 TA (°C) 100 150 –50 Hysteresis versus Ambient Temperature 0 50 TA (°C) 100 150 Hysteresis versus Ambient Temperature (A1211) (A1212) 240 350 220 300 180 VCC (V) 160 24 3.8 140 BHYS (G) BHYS (G) 200 VCC (V) 250 24 3.8 200 120 150 100 80 100 –50 0 50 TA (°C) 100 150 –50 0 50 100 150 TA (°C) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family FUNCTIONAL DESCRIPTION Operation The output of these devices switches low (turns on) when a magnetic field perpendicular to the Hall element exceeds the operate point threshold, BOP. After turn-on, the output is capable of sinking 25 mA and the output voltage is VOUT(SAT). Notice that the device latches; that is, a south pole of sufficient strength towards the branded surface of the device turns the device on, and the device remains on with removal of the south pole. When the magnetic field is reduced below the release point, BRP , the device output goes high (turns off). The difference in the magnetic operate and release points is the hysteresis, Bhys, of the device. This built-in hysteresis allows clean switching of the output, even in the presence of external mechanical vibration and electrical noise. Powering-on the device in the hysteresis range, less than BOP and higher than BRP, allows an indeterminate output state. The correct state is attained after the first excursion beyond BOP or BRP. Continuous-Time Benefits Continuous-time devices, such as the A121x family, offer the fastest available power-on settling time and frequency response. Due to offsets generated during the IC packaging process, continuous-time devices typically require programming after packaging to tighten magnetic parameter distributions. In contrast, chopper-stabilized switches employ an offset cancellation technique on the chip that eliminates these offsets without the need for after-packaging programming. The tradeoff is a longer settling time and reduced frequency response as a result of the chopper-stabilization offset cancellation algorithm. The choice between continuous-time and chopper-stabilized designs is solely determined by the application. Battery management is an example where continuous-time is often required. In these applications, VCC is chopped with a very small duty cycle in order to conserve power (refer to figure 2). The duty cycle is controlled by the power-on time, tPO, of the device. Because continuous-time devices have the shorter power-on time, they are the clear choice for such applications. For more information on the chopper stabilization technique, refer to Technical Paper STP 97-10, Monolithic Magnetic Hall Sensing Using Dynamic Quadrature Offset Cancellation and Technical Paper STP 99-1, Chopper-Stabilized Amplifiers with a Track-and-Hold Signal Demodulator. (A) (B) VS V+ VOUT 0 BOP B– VCC A121x VOUT(SAT) BRP 0 Switch to Low Switch to High VCC RL VOUT Output GND B+ BHYS Figure 1: Switching Behavior of Latches On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited when using a circuit such as that shown in Panel B. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family Additional Application Information Extensive applications information for Hall-effect devices is available in: • Hall-Effect IC Applications Guide, Application Note 27701 • Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead Welding and Lead Forming, Application Note 27703.1 • Soldering Methods for Allegro’s Products – SMT and Through-Hole, Application Note 26009 All are provided in Allegro Electronic Data Book, AMS-702, and the Allegro Web site, www.allegromicro.com. 1 2 3 4 5 VCC t VOUT t Output Sampled tPO(max) Figure 2: Continuous-Time Application, B < BRP This figure illustrates the use of a quick cycle for chopping VCC in order to conserve battery power. Position 1, power is applied to the device. Position 2, the output assumes the correct state at a time prior to the maximum Power-On Time, tPO(max). The case shown is where the correct output state is HIGH . Position 3, tPO(max) has elapsed. The device output is valid. Position 4, after the output is valid, a control unit reads the output. Position 5, power is removed from the device. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family POWER DERATING PD = VCC × ICC = 12 V × 4 mA = 48 mW Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RθJC, is relatively small component of RθJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN (1) ΔT = PD × RθJA (2) TJ = TA + ΔT (3) For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 4 mA, and RθJA = 140 °C/W, then: ΔT = PD × RθJA = 48 mW × 140 °C/W = 7°C TJ = TA + ΔT = 25°C + 7°C = 32°C A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RθJA and TA. Example: Reliability for VCC at TA = 150°C, package UA, using minimum-K PCB. Observe the worst-case ratings for the device, specifically: RθJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 7.5 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 7.5 mA = 12.1 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family PACKAGE OUTLINE DRAWINGS For Reference Only – Not for Tooling Use (Reference DWG-2840) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown +0.12 2.98 –0.08 D 1.49 4°±4° A 3 0.180 +0.020 –0.053 0.96 D +0.10 2.90 –0.20 1.91 +0.19 –0.06 2.40 0.70 D 0.25 MIN 1.00 2 1 0.55 REF 0.25 BSC 0.95 Seating Plane B Gauge Plane 8X 10° REF PCB Layout Reference View Branded Face 1.00 ±0.13 0.05 0.95 BSC +0.10 –0.05 0.40 ±0.10 NNN C Standard Branding Reference View N = Last three digits of device part number A Active Area Depth, 0.28 mm B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion D Hall elements, not to scale Figure 3: Package LH, 3-Pin SOT-23W Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family For Reference Only – Not for Tooling Use (Reference DWG-9065) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 2 X 45° B 4.09 +0.08 –0.05 1.52 ±0.05 E 2.04 C 3 X 10° 1.44 E 3.02 E Mold Ejector Pin Indent +0.08 –0.05 45° Branded Face 1.02 MAX 0.51 MAX A 0.79 REF 1 2 3 0.43 +0.05 –0.07 0.41 +0.03 –0.06 1.27 NOM NNN 14.99 ±0.25 1 D Standard Branding Reference View = Supplier emblem N = Last three digits of device part number A Dambar removal protrusion (6X) B Gate and tie bar burr area C Active Area Depth, 0.50 mm REF D Branding scale and appearance at supplier discretion E Hall element, not to scale Figure 4: Package UA, 3-Pin SIP Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A1210, A1211, A1212, A1213, and A1214 Continuous-Time Latch Family Revision History Revision Revision Date 10 May 29, 2012 Description of Revision 11 August 20, 2014 Revised Selection Guide, reformatted datasheet 12 January 1, 2015 Added LX option to Selection Guide 13 September 22, 2015 Update UA package drawing Corrected LH package Active Area Depth value; added AEC-Q100 qualification under Features and Benefits Copyright ©2015, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14