2 1 REVISION HISTORY ECO REV DESCRIPTION APPROVED DATE 0 PRODUCTION DOUG S. 08-26-13 D D U13 LT1763CS8-5 VDD E6 8 +6V IN TP19 TP18 TP17 TP16 TP14 TP15 C90 47uF 1210 5 SHDN GND GND GND C71 1uF OUT 1 SEN 2 BYP 4 +5V C70 0.01uF C68 10uF 0805 CLK 200MHz MAX 2.5VPP E10 +2.5V C63 0.1uF R40 1K C67 0.1uF J4 TP13 R32 33 2 R41 49.9 1206 3 6 7 GND +2.5V CLK 4 CLKIN U11 NC7SZ04P5X R39 1K 3 +6V E9 This circuit conditions the edges of the CNV pulse as follows: The rising edge of CNV is driven by a rising edge of CLKIN. The falling edge of CNV is driven by a falling edge of CNV_EN, so it is wider than 'N' clock cycles. The circuit serves to eliminate jitter on the CNV pulse due to CPLD jitter. The risiing edge of the CNV pulse is thus driven by CLKIN, not CNV_EN. Powers the ADC. 5 Powers the voltage reference IC. Powers the CPLD mamory device. +2.5V BYP C25 0.01uF C32 10uF 0805 R28 1.43k 4 GND 6 CLR TP4 4 D CP 1 +3V Q 2 VCC 8 PR 7 Q GND GND GND SHDN 1 SEN C54 R36 33 R27 1k 3 6 7 5 OUT U9 NL17SZ74 5 IN C31 1uF 3 8 +3V 2 E1 U4 LT1763CS8 0.1uF R37 33 CNV_EN Powers the logic inverters (3PL), flip-flop. E3 U8 LT1763CS8-2.5 SEN BYP 4 C48 0.01uF Powers the CPLD VCCIO. +2.5V TP1 C47 10uF 0805 L2 33 Ohm FB VCCA_2.5V VDD VCC_1.2V IN OUT 2 SEN 3 AGND VCM L5 33 Ohm FB 32 C64 10uF 0805 TP3 9 22 31 30 REFBUF REFBUF VCM REFIN C57 0.1uF 0402 VCCPLL_1.2V 20 19 DCO+ DCO- CNV+ CNV- 28 27 CLK+ CLK- 24 23 DA+ DA- 18 17 OVDD DB+ DB- DCO+ DCO- CLK+ DA+ DA- R35 100 0201 CLK- Powers the CPLD VCCPLL. C37 10uF 0805 +1.2V OVDD 3 2 1 Test Pattern ON EXT REF IN 4 6 SHDN GND C40 3.3uF 5 Powers the CPLD VCCINT. E2 7 8 REFBUF 16 15 IN+ TWOLANES AIN+ 0V - 4.096V 2 R50 10 DB+ DB- ~PD J6 C75 82pF U5 LT3021ES8-1.2 8 C C49 0.1uF 0402 13 +2.5V IN- TESTPAT TP10 C59 10uF 0805 3 C74 DNI VDDL VDDL U10 LTC238X-XX Powers the ADC I/O. 25 BYP 4 C65 0.01uF C99 4.7uF REFGND REFGND SEN 2 OVDD C58 0.1uF 0402 C73 82pF R49 10 3 6 7 SHDN GND GND GND C66 1uF OUT L3 33 Ohm FB AIN0V - 4.096V J5 C53 4.7uF 14 VDDL 1 TP5 C55 0.1uF 0402 5 6 U12 LT1763CS8-2.5 5 Powers the ADC. E4 IN OVDD TP6 C52 4.7uF TP9 8 VDDL Powers the CPLD VCCA. 12 11 SHDN 2 VCCIO_2.5V 3 6 7 5 1 VDD VDD C GND GND GND C51 1uF OUT GND GND GND GND GND GND GND IN L1 33 Ohm FB 1 4 10 21 26 29 33 8 TP2 +2.5V JP3 E5 REFIN C60 4.7uF 3 2 1 Power Down C56 0.1uF 0402 JP4 Two Lanes B VDDL 3 2 1 One Lane 2_LANE B JP2 U14 LTC6655BHMS8-4.096 TP8 BITS 18 16 18 16 18 16 Msps 15 15 10 10 5 5 R33 1K DNI 1K DNI 1K DNI R34 DNI 1K DNI 1K DNI 1K TP7 R38 DNI R53 10K 0402 E7 U17 LT6202CS5 VCMMN 1 R44 0 VREF C87 +6V 0.1uF 5 U10 LTC2387CUH-18 LTC2387CUH-16 LTC2386CUH-18 LTC2386CUH-16 LTC2385CUH-18 LTC2385CUH-16 + 3 - 4 2 * ASSY -A -B -C -D -E -F C77 10uF 0805 C80 4.7uF 8 GND 7 6 5 1. ALL RESISTORS ARE IN OHMS, 0603. ALL CAPACITORS ARE IN MICROFARADS, 0603 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 VOUT_F VIN 2 VOUT_S GND 3 GND GND 4 +6V C69 1uF C76 2.2uF APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; D. STUETZLE HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. D. STUETZLE APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. NOTES: UNLESS OTHERWISE SPECIFIED 1 R54 10K 0402 CUSTOMER NOTICE A SHDN TECHNOLOGY TITLE: SCHEMATIC 18-Bit, 15Msps SAR ADC SIZE IC NO. B SCALE = NONE 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use OnlyA DATE: 1 REV. LTC2387CUH FAMILY DEMO CIRCUIT 2290A Wednesday, May 27, 2015 2 SHEET 1 OF 2 2 1 D D R1 33 U3B U3C IO1 IO2 IO3 IO4 IO5_VREF1 IO6_DIFFL4P IO7_DIFFL4N CLK0 CLK1 U3E BANK2 R2 33 1 2 3 4 7 10 11 22 23 U3D U3F U3G U3H U3I DB2 0402 BANK1 CLK2 CLK3 IO1 IO2 IO3_VREF2 IO4_RUP1 IO5_RDN1 IO6 DB3 0402 R3 33 DB4 0402 R4 33 R14 33 24 25 28 30 31 32 33 34 DB9 0402 DB10 0402 DB11 0402 DB12 0402 DB13 0402 DB14 IO1_DIFFIOB1P IO2_DIFFIOB1N IO3 IO4 IO5 IO6_VREF3 IO7_DIFFIOB9P IO8_DIFFIOB9N IO9 IO10_DIFFIOB11P IO11_DIFFIOB11N R16 33 R5 33 38 39 42 43 44 46 49 50 51 52 53 BANK4 0402 DB15 R25 33 0402 OUTPUT_LATCH R17 33 DB6 0402 0402 R15 33 DB5 0402 R23 33 BANK3 R7 33 0402 DB7 R18 33 0402 DB8 R19 33 R8 33 CYCLONE3-EP3C5E144 CYCLONE3-EP3C5E144 IO1_DIFFIOB12P IO2_DIFFIOB12N IO3 IO4_DIFFIOB16P IO5_DIFFIOB16N IO6 IO7_VREF4 IO8_RUP2 IO9_RDN2 IO10 IO11 IO12_DIFFIOB21P IO13_DIFFIOB21N IO14 BANK5 54 55 58 59 60 64 65 66 67 68 69 70 71 72 BANK6 IO1 IO2 IO3 IO4_RUP3 IO4_RDN3 IO5 IO6_VREF5 IO7 IO8_DIFFIOR8N IO9_DIFFIOR8P CLK7_DIFFCLK3N CLK6_DIFFCLK3P 73 74 75 76 77 79 80 83 84 85 88 89 2_LANE R33 1K BANK7 90 91 100 104 105 106 CLK5_DIFFCLK2N CLK4_DIFFCLK2P IO1 IO2 IO3_VREF6 IO4 VCCIO_2.5V CLKIN IO1 IO2 IO3 IO4 IO5_RUP4 IO6_RDN4 IO7_VREF7 IO8_DIFFIOT16N IO9_DIFFIOT16P IO10 IO11 IO12_DIFFIOT12N IO13_DIFFIOT12P R34 DNI CNV_EN CLK+ R68 33 BANK8 110 111 112 113 114 115 119 120 121 124 125 126 127 IO1_DIFFIOT11N IO2_DIFFIOT11P IO3_DIFFIOT10N IO4_DIFFIOT10P IO5 IO6_VREF8 IO7 IO8 IO9 IO10 IO11_DIFFIOT01N IO12_DIFFIOT01P 128 129 132 133 135 136 137 138 141 142 143 144 0402 DB16 0402 DB17 0402 DB0 0402 DB1 R69 33 R20 33 R21 33 CLKCYCLONE3-EP3C5E144 CYCLONE3-EP3C5E144 CYCLONE3-EP3C5E144 CYCLONE3-EP3C5E144 CYCLONE3-EP3C5E144 CYCLONE3-EP3C5E144 DB17 DB16 J1 PCB EDGE CONN. 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 OUTPUT_LATCH 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 C VCCA_2.5V R22 4.99K R26 4.99K +3V R70 10K C43 0.1uF 0402 R9 10K R10 10K 1 3 5 7 9 J3 HD2X5-100 R12 10K 26 VCCIO3 VCCIO3 40 47 VCCIO4 VCCIO4 56 62 VCCIO5 81 VCCIO6 93 VCCIO7 VCCIO7 117 122 VCCIO8 VCCIO8 130 139 VCCA1 VCCA2 35 107 VCCD_PLL1 VCCD_PLL2 37 109 C20 0.1uF 0402 C46 0.1uF 0402 C29 0.1uF 0402 C18 0.1uF 0402 C1 0.1uF 0402 C4 0.1uF 0402 EPCS4SI8 R71 0 CYCLONE3-EP3C5E144 DCO+ +3V R31 100 0201 C22 0.1uF 0402 VCCIO_2.5V C14 0.1uF 0402 C2 0.1uF 0402 C3 0.1uF 0402 C15 0.1uF 0402 C19 0.1uF 0402 C26 0.1uF 0402 C30 0.1uF 0402 C28 0.1uF 0402 C45 0.1uF 0402 R72 DNI R11 1K R13 10K DA+ +3V +3V +3V D1 BAT54WS +3V D3 BAT54WS DCO- R30 100 0201 C24 0.1uF 0402 B CONF_DONE 1 17 VCCIO2 C98 0.1uF 0402 8 7 6 5 VCC VCC DCLK ASDI D4 BAT54WS D2 BAT54WS 2 VCCIO1 C27 0.1uF 0402 nCS DATA VCC GND 1 5 29 45 61 78 102 116 134 1 2 3 4 2 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT DATA1 FLASH_nCE nSTATUS DCLK DATA0 nCONFIG TDI TCK TMS TDO NCE 2 VCC_1.2V U1 +3V 6 8 9 12 13 14 15 16 18 20 21 86 87 92 94 96 97 98 99 101 103 1 PROG Note that only the VCCIO rails may be changed. C9 10pF C21 10pF C13 10pF C16 10pF DA- C44 0.1uF 0402 DB+ R29 100 0201 VCCA_2.5V MSEL[0,1,2] pins must be set as follows: For VCCIO = 2.5V/3.0V: 1 1 0 For VCCIO = 3.3V: 0 1 0 DB- C5 47uF 0805 C6 4.7uF C41 22nF 0402 C42 22nF 0402 C7 22nF 0402 CUSTOMER NOTICE CYCLONE3-EP3C5E144 VCCPLL_1.2V + A 2 4 6 8 10 2 ARRAY EEPROM GND ASDO nCSO nSTATUS DCLK IO3_DATA0 nCONFIG TDI TCK TMS TDO nCE IO4_DEV_OE IO5_DEV_CLRn CONF_DONE MSEL0 MSEL1 MSEL2 IO6_INIT_DONE IO7_CRC_ERROR IO8_nCEO IO9_CLKUSR WP U3A GND GND GNDA1 GND GND GND GND GND GND GNDA2 GND GND GND GND GND FPGA PROGRAM C17 0.1uF 0402 VCCA_2.5V CONFIG EEPROM 1 2 3 B PWR C12 0.1uF 0402 U3J 6 5 7 3 2 1 JP1 19 27 36 41 48 57 63 82 95 108 118 123 131 140 145 VCCIO_2.5V R6 10K 4 SCL SDA WP A2 A1 A0 TDI +3V U2 24LC024-I /ST VCC 8 R24 4.99K TCK TDO TMS 1 3 5 7 9 J2 HD2X5-100 Be sure to disable the following pin options in Quartus: DEV_OE, DEV_CLRn, INIT_DONE, CRC_ERROR ,CLK_USR, nCEO C23 0.1uF JTAG 2 4 6 8 10 1 C C97 47uF 0805 C96 4.7uF C11 0.01uF 0402 C10 0.01uF 0402 C34 0.1uF 0402 C33 0.1uF 0402 C36 0.1uF 0402 C35 0.1uF 0402 C38 0.1uF 0402 C95 2.2nF 0402 NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTORS ARE IN OHMS, 0603. ALL CAPACITORS ARE IN MICROFARADS, 0603 C8 4.7nF 0402 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; D. STUETZLE HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. D. STUETZLE APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. TECHNOLOGY TITLE: SCHEMATIC 18-Bit, 15Msps SAR ADC SIZE IC NO. B SCALE = NONE 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use OnlyA DATE: 1 REV. LTC2387CUH FAMILY DEMO CIRCUIT 2290A Wednesday, May 27, 2015 2 SHEET 2 OF 2