Quartus II Software version 7.2 Device Support Release Notes

Quartus II Device Support
Release Notes
October 2007
Quartus II version 7.2
This document provides late-breaking information about device support in this
version of the Altera® Quartus® II software. For information about memory, disk
space, and system requirements, refer to the readme.txt file in your
\altera\quartus<version number> directory. For information about New
Features, EDA Tool version support, and existing and resolved software issues,
refer to the Quartus II Software Release Notes.
Device Support & Pin-Out Status........................................................... 2
Full Device Support ........................................................................... 2
Advance Device Support ................................................................... 2
Timing Models ......................................................................................... 3
Preliminary Timing Models............................................................... 3
Final Timing Models ......................................................................... 4
Power Models .......................................................................................... 5
Changes in Device Support.................................................................... 6
Change in Timing Models for Stratix II, Stratix II GX, and Arria GX
Output Pin tCO Derating..................................................................... 6
New Cyclone III Industrial Ordering Codes...................................... 6
Fixed Intermittent Corruption of Initial Memory Content................. 7
Configuration Voltage Constraint for Cyclone III Devices............... 7
I/O Standards Requiring External Resistor Not Supported on
Cyclone III ......................................................................................... 7
Altera Corporation
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Quartus II Device Support Release Notes
Version 7.2
Device Support & Pin-Out Status
This section contains information about the status of support in the Quartus II
software for the devices listed.
Full Device Support
Full compilation, simulation, timing analysis, and programming support is now
available for the following new devices and device packages:
Devices with Full Support
Device Family
Arria™ GX
Cyclone® III
Stratix III
Devices
EP1AGX20CF484
EP1AGX50CF484
EP3C5E144
EP3C5U256
EP3C10F256
EP3C55F484
EP3C55U484
EP3SL150F780ES
EP1AGX35CF484
EP1AGX60CF484
EP3C5F256
EP3C10E144
EP3C10U256
EP3C55F780
EP3SL150F1152ES
Advance Device Support
Compilation, simulation, and timing analysis support is provided for the
following devices that will be released in the near future. Although the Compiler
generates pin-out information for these devices, it does not generate
programming files for them in this release.
Devices with Advance Support with Pin-out Support
Device Family
®
Stratix III
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Devices
EP3SL200F780
EP3SL340H1152
EP3SE260H780
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Quartus II Device Support Release Notes
Version 7.2
Timing Models
This section contains a summary of timing model status in the current version of
the Quartus II software.
Preliminary Timing Models
The following table shows the devices with preliminary timing models in the
current version of the Quartus II software:
Devices with Preliminary Timing Models
Device Family
HardCopy II
Cyclone III
Stratix III
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Device
HC210
HC220
HC240
EP3C10
EP3C25
EP3C55
EP3C120
EP3SE50
EP3SL70
EP3SE110
EP3SL150
EP3SE260
HC210W
HC230
EP3C16
EP3C40
EP3C80
EP3SL50
EP3SE80
EP3SL110
EP3SL200
EP3SL340
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Quartus II Device Support Release Notes
Version 7.2
Final Timing Models
The following table lists the devices with final timing models that are available in
the current version of the Quartus II software:
Devices with Final Timing Models
Device Family
Arria GX
Cyclone II
MAX® II
Stratix II
Stratix II GX
Device
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
EP2C5
EP2C8
EP2C20
EP2C35
EP2C50
EP2C70
EPM240
EPM1270
EPM570
EPM2210
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130
Timing Models Final in Quartus II
Version Number
7.2
7.2
7.2
7.2
7.2
6.0
5.1 SP2
5.1 SP2
5.1 SP2
6.0
5.1 SP2
5.0
5.0
5.0 SP1
5.0 SP1
5.0 SP1
5.0
5.0
5.0 SP1
5.0 SP1
5.1
7.0
7.0
6.1
6.1
The current version of the Quartus II software also includes final timing models
for the ACEX® 1K, APEX® 20K, APEX 20KE, APEX 20KC, APEX II, Cyclone,
FLEX® 6000, FLEX 10K, FLEX 10KA, FLEX 10KE, and MAX 7000S, Stratix,
and Stratix GX device families. Timing models for these device families became
final in versions 4.1 and earlier.
Altera Corporation
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Quartus II Device Support Release Notes
Version 7.2
Power Models
This section contains a summary of power model status for recent devices in the
current version of the Quartus II software.
Device Family
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Cyclone
Cyclone II
Cyclone III
MAX 3000A
MAX 7000AE
MAX 7000B
MAX II
HardCopy II
Arria GX
(1)
Altera Corporation
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Power Model Status
Final – 5.1
Final – 5.1
Final – 6.0
Final – 7.1
Preliminary
Final – 5.1
Final – 6.0
Preliminary
Final – 5.1
Final – 5.1
Final – 5.1
Final – 5.0 SP1
Correlated(1) – 7.2
Final – 7.2
HardCopy II power models are fully correlated to silicon in this release.
5
Quartus II Device Support Release Notes
Version 7.2
Changes in Device Support
Change in Timing Models for Stratix II, Stratix II GX, and
Arria GX Output Pin tCO Derating
The timing models for Stratix II, Stratix II GX, and Arria GX devices have been
corrected. In previous releases, the output pin tCO derating due to capacitive
loading on LVCMOS outputs with Non-Calibrated 50-Ohm termination selected
was incorrectly specified as 0. The change in tCO derating in ps per pF of
capacitive load is provided in the following table:
Device family*
Speed Grade
tCO derating
(ps/pF)
Stratix II
-3
-4
55 63
-5
Stratix II GX
Arria
GX
-3
-4
-5
-6
64 55
63
64
64
* applies to both commercial and industrial grade devices
Applies to: All Stratix II, Stratix II GX, and Arria GX device families
New Cyclone III Industrial Ordering Codes
The following ordering codes have been added to the Quartus II software to
support new Cyclone III devices.
EP3C5E144I7
EP3C10E144I7
EP3C16E144I7
EP3C16U256I7
EP3C25F256I7
EP3C40F324I7
EP3C40U484I7
EP3C55U484I7
EP3C80U484I7
EP3C5F256I7
EP3C10F256I7
EP3C16F256I7
EP3C16U484I7
EP3C25F324I7
EP3C40F484I7
EP3C55F484I7
EP3C80F484I7
EP3C120F484I7
EP3C5U256I7
EP3C10U256I7
EP3C16F484I7
EP3C25E144I7
EP3C25U256I7
EP3C40F780I7
EP3C55F780I7
EP3C80F780I7
EP3C120F780I7
Applies to: Cyclone III device family
Altera Corporation
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Quartus II Device Support Release Notes
Version 7.2
Fixed Intermittent Corruption of Initial Memory Content
Corruption of initial memory content may occur in M4K memory blocks when
the write enable signal is used and connected directly to VCC, and the clock
enable signal is not used. The data corruption occurs immediately after device
configuration. This issue is fixed in version 7.2.
Applies to: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III,
Stratix II GX, and Arria GX devices
Configuration Voltage Constraint for Cyclone III Devices
In an Active Serial (AS) configuration scheme, the VCCIO of IOBANK 1 of the
Cyclone III device must be 3.3 V. In an Active Parallel (AP) configuration
scheme, the VCCIO of IOBANK 1, 6, 7 and 8 must be the same and must be 1.8,
2.5, 3.0 or 3.3V.
Altera recommends that you not use level shifters between a configuration device
and the Cyclone III device in any active configuration scheme.
Applies to: Cyclone III devices
I/O Standards Requiring External Resistor Not
Supported on Cyclone III
This version of the Quartus II software does not support differential I/O standards
requiring external resistor network for Cyclone III on row I/O banks 1, 2, 5 and
6. The affected I/O standards are labeled in the Quartus II software as LVDS_3R,
RSDS_1R, RSDS_3R, MINI_LVDS_3R, PPDS_3R.
You can use the I/O standards that do not require external resistors and are
labeled in the Quartus II software as LVDS, RSDS, mini-LVDS and PPDS. The
I/O standards requiring external resistor network are supported on the column I/O
banks.
Applies to: Cyclone III devices
Altera Corporation
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Quartus II Device Support Release Notes
Version 7.2
Revision History
Revision
1.0
Description
Initial Release
Copyright © 2007 Altera Corporation. All rights reserved. Altera, The
Programmable Solutions Company, the stylized Altera logo, specific device
designations and all other words and logos that are identified as trademarks
and/or service marks are, unless noted otherwise, the trademarks and service
marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are
protected under numerous U.S. and foreign patents and pending applications,
mask work rights, and copyrights.
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