ISL6745 ® PRELIMINARY Data Sheet November 22, 2004 FN9161.3 主要特點 數据資料 精确的死區時間控制的橋型控制器 • • 精确的占空比和死區時間控制 100µA啟動電流 • 可調延遲過流關斷和重新啟動 ISL6745是成本低、雙端控制器。主要應用于全橋和半橋型 拓扑結构的電源和線調節的總線變換器。器件的主要特點是 精确的開關頻率控制、可調軟啟動、和過流關斷保護。另外 ，ISL6745可精确地調整MOSFET不交迭的死區時間低至35 ns，允許電源設計師优化開環總線變換器的效率。ISL6745 還包括電壓控制輸入适合于閉環PWM控制和線壓前饋控制。 • • • 可調振蕩器頻率高至 2MHz 1A MOSFET門极驅動器 可調軟啟動 • • 內部過熱保護 控制到輸出的延遲是35ns ISL6745的低啟動和運作電流特點, 使其在AC-DC和DC-DC 應用容易地偏壓。 • • • 体積小和极少的外部元件 輸入欠壓保護 不含Pb的包裝 這先進的BiCMOS設計特點是可調開關頻率高至1MHz，1A FET 驅動器，和非常低的傳輸延遲适合于過流快反 應。 應用 定購資料 零件號碼 溫度范圍 (°C) ISL6745AU -40 to 105 ISL6745AUZ (See Note) -40 to 105 包裝 10 Ld MSOP 10 Ld MSOP (Pb-free) • • • • 包裝圖號# M10.118 半橋和全橋型拓扑結构的變換器 線調節的總線變換器 AC-DC電源 通信、信息和檔案服務器的電源 M10.118 Add -T suffix to part number for tape and reel packaging 插腳引線 (頂視圖) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. ISL6745 (MSOP) SS 1 1 10 VDD RTD 2 9 VDDP VERR 3 8 OU TB CS 4 7 OU TA CT 5 6 GN D CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143|Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners ISL6745 V DDP FL V BIAS V BIAS 5.00 V V DD OUT A Q + BG T UVLO Q OUT B PW M T OGGLE V BIAS INT ERNAL OT SHUT DOW N 130 - 150 C 70 uA GND ON SS V BIAS + - SS CLAMP RTD - 2.0 V IRT D + - + 15 uA SS CHARGED 3.9 V 4.0 V V BIAS 160 uA S Q R Q OC LAT CH ON - 2.8 V PEAK + CT - I DCH= 55 x IRTD 0.8 V S Q R Q CLK Q RESET DOMINANT VALLEY + SS LOW Q 50 µS RET RIGGERABLE ONE SHOT FAULT LAT CH SET DOMINANT S Q IDCH R Q S Q R Q PW M LAT CH SET DOMINANT ON 4.65V ↓ 4.80V ↑ + BG CS 0.6 V + - OC DETECT PW M COMPARAT OR V BIAS + - CT 15 uA SS 0.8 0.8 ISL6745 內部電路結构 2 0.27 V SS FL V BIAS V BIAS UV V ERR + - ISL6745 額定值 Voltage Ratings bsolute 熱性能的資料 Thermal Information Supply Voltage, VDD ----------------------GND-0.3V to +20V OUTA, OUTB ------------------------------- GND -0.3V to VDD Signal Pins------------------------------------- GND-0.3V to 5V Peak GATE Current ------------------------------------------- 1A ESD Classification Thermal Resistance (Typical, Note 1) -----------θJA ( C/W) 10 Lead MSOP ------------------------------------------------ 128 o o Maximum Junction Temperature ---------- -55 C to 150 C o o Maximum Storage Temperature Range - -65 C to 150 C o Maximum Lead Temperature (Soldering 10s)------300 C o Human Body Model (per JEDEC22 std. Method A114-B)---Class 2 Machine Model (Per JEDEC22 std. Method A115-A)---------Class A Recommended Operating Conditions 運行條件 Supply Voltage Range (Typical) -------------------9-16VDC Temperature Range o o ISL6745AU--------------------------------- -40 C to 105 C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTES: 1) θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2) All voltages are to be measured with respect to GND, unless otherwise specified. 電气規范 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic. o o o 9V<VDD<16V, RTD= 51.1KΩ, CT = 470pF, TA = -40 C to 105 C (Note 4), Typical values are at TA= 25 C. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SUPPLY VOLTAGE Start-Up Current, IDD VDD< START Threshold - - 175 µA Operating Current, IDD COUTA, B = 1nF - 5 8.5 mA 5.9 6.3 6.6 V UVLO START Threshold 5.3 5.7 6.3 V - 0.6 - V 0.55 0.6 0.65 V - 35 - ns CS Sink Current 8 10 - mA Input Bias Current -1 - 1 µA UVLO STOP Threshold Hysteresis CURRENT SENSE Current Limit Threshold (Note 4) CS to OUT Delay PULSE WIDTH MODULATOR Minimum Duty Cycle VERROR < CT Offset - - 0 % Maximum Duty Cycle CT = 470pF, RTD = 51.1KΩ - 94 - % - 99 - % - 0.8 - V/V CT = 470pF, RTD = 1.1KΩ VERR to PWM Comparator Input Gain (Note 4) CT to PWM Comparator Input Gain (Note 4) - 1 - V/V SS to PWM Comparator Input Gain (Note 4) - 0.8 - V/V 143 156 170 µA 1.925 2 2.075 V 45 - 65 µA/µA OSCILLATOR o TA = 25 C Charge Current RTD Voltage Discharge Current Gain 3 ISL6745 電气規范 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic. o o o 9V<VDD<16V, RTD= 51.1KΩ, CT = 470pF, TA = -40 C to 105 C (Note 4), Typical values are at TA= 25 C. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CT Valley Voltage 0.75 0.8 0.85 V CT Peak Voltage 2.70 2.80 2.90 V Net Charging Current 45 - 68 µA SS Clamp Voltage 3.8 4.0 4.2 V - 3.9 - V 12 15 23 µA 0.25 0.27 0.30 V - 0.5 2.0 V Low Level Output Voltage (VOL) VDD – VOUTA or VOUTB, IOUT = -100mA IOUT = 100mA - 0.5 1.0 V Rise Time CGATE = 1nF, VDD = 12V - 17 60 ns Fall Time CGATE = 1nF, VDD = 12V - 20 60 ns Thermal Shutdown (Note 4) - 145 - o Thermal Shutdown Clear (Note 4) - o Hysteresis, Internal Protection (Note 4) - o SOFT-START Overcurrent Shutdown Threshold Voltage Overcurrent Discharge Current (Note 4) Reset Threshold Voltage (Note 4) OUTPUT High Level Output Voltage (VOH) THERMAL PROTECTION NOTES: o 3. Specifications at -40 C are guaranteed by design, not production tested. 4. Guaranteed by design, not 100% tested in production. 4 - 130 15 C C C ISL6745 典型性能曲線圖 5 ISL6745 OUTA and OUTB ISL6745各管腳簡介 OUTA和OUTB為交替半周期輸出端。每個輸出具有1A峰值電 VDD VDD為電源輸入端。要优化抗扰度，用一個陶瓷電容器盡可 流的輸出能力可驅動MOSFETs或MOSFET驅動器，且以非 常低 的阻抗降低過沖和下沖。 能靠近并挎接在VDD和GND引腳。 IC總供應電流，IDD，取決于OUTA和OUTB輸出端的負載。 SS IDD電流是靜態電流和平均輸出電流的總和。平均輸出電流 在這個引腳与GND之間連接軟啟動定時電容器來控制軟啟動 (IOUT)与操工作頻率(FSW)和每輸出端的負載電容的電荷量(Q) 的時間。電容值決定啟動時占空比的增長率，且控制過流關 成 正比， 其值可用下式 計 算: IOUT = 2 × Q × FSW 斷延遲和過流与短路間歇再啟動周期。 (EQ. 1) RTD 這是振蕩器定時電容放電電流控制引腳。一個電阻器應連接 在這引腳和GND之間。而流經這個電阻的電流決定放電電流 功能概述 主要特點 的大小。放電電流的通常值則是這電流的55倍。PWM死區時 間由定時電容放電時間決定。 ISL6745為那些以低成本的橋型拓扑結构且要求准确頻率和死 區時間控制的應用提供了一個极佳的選擇。它有很多特點， CT 振蕩器定時電容應連接在這引腳和GND之 間。 其中有1AFET驅動器、可調軟啟動、過流保護和內部過熱保 CS 護，因而ISL6745能以最少量的外部元件做出一個高度靈活的 這是過流保護比較器的輸入端。過流比較器門限值設置為典 設計。 型值0.600V。在每個開關周期的末端，CS引腳短接于GND。 振荡器 根据電流傳感源阻抗，由于內部時鐘和外部電力開關間的延 遲，可能要求串聯一個電阻。 ISL6745通過改變電阻RTD和電容CT來調振蕩器頻率高達2M HZ。開關周期是定時電容充電和放電時間之和。充電時間由 超出過流門限值會啟動延遲關斷程序。一旦檢測出過流情況 CT和內部電流源(在式中采用160µA)決定，而放電時間取決于 ，軟啟動充電電流源就會被截止。而軟啟動電容通過15A電 RTD和 CT。 流源放電，如果軟啟動電壓降至于3.9V(可承受的過流門限值) 關斷條件出現，OUTA和OUTB輸出會強制降低。當軟啟動電 壓降至0.27V(重新設置門限值)，一個新軟啟動周期開始。如 果过流情况中断，且在50µs时间内未达到关断门限值(3.9V) TC ≈ 1.25 × 10 4 • CT TD ≈ s (EQ.2) 1 • RTD • CT CTDisch arg eCurrentGain s (EQ. 3) ，过流关断是不会发生。软启动充电电流重新运行且软启动 TOSC = TC + TD = 电压复位。 1 FOSC s (EQ. 4) GND TC和TD分別是大概的充電和放電時間，TOSC是振蕩器自由運 器件上所有功能和電源地都以這個引腳為基准。由于高峰值 行周期，而FOSC是振蕩器頻率。放電電流增益(DischargeCur 電流和高頻工作，布局必須是低阻抗的。故建議使用地線板 rentGain=45to65)可在第3頁的表(或Figure1)找到。一個輸出 塊和短接線。 的開關周期等于二個振蕩器周期。由于傳輸延遲約5ns，實際 時間比所計算的時間稍微長。這個延遲直接增加到開關時間 ，且引起定時電容峰值和谷電壓門限過沖，因而增大了定時 電容峰-峰的電壓。另外，如果使用非 常低充電和放電電流， 6 ISL6745 時間誤差將會因CT引腳處的輸入阻抗而增加。 過15A電源放電。過流情況停止后，在50µs時間內，如果軟 EQ.2至4可幫助估計振蕩器頻率。在實踐上,寄生電容會影響 啟動電容器放電至3.9V，輸出停止。這种狀態持續到軟啟動 全部的CT電容，RTD電壓的變化和充電電流遍及溫度的變化及 電壓降至270mV，開始新軟啟動周期。如果在軟啟動電壓降 其他變化是不可被忽視的。這些對頻率的影響最好在真的電 至的3.9V前，且過流情況停止至少50µs，軟啟動充電電流會 路板里評价。EQ.2依据于基本的電容電流公式，I=C*dV/dt。 恢复正常運作，而軟啟動電壓會复位。 根据RTD電壓的變化(如圖4)和充電電流變化(如圖5)，公式2 的結果將會不同計算出的結果。典型性能曲線和上述的公式 過熱保護 一起 更精确地估計工作頻率。 o 內熱傳感器保護器件芯片結溫不超出145 C，而熱遲滯約15 最大占空比（DMAX）和死區時間（DT）可用以下公式計算 o DMAX = TC (EQ. 5) TOSC DT = TOSC × (1 − DMAX ) (EQ. 6) 軟啟動運作 ISL6745使用外部電容和內部電流電源來作軟啟動。軟啟動降 低啟動期間的電壓和浪涌電流。 在用以驅動PWM門控的軟啟動比較器里，振蕩器電容CT信號 与軟啟動SS電壓作比較。當軟啟動電壓（SS）少于2.8V時， 占空比會受到限制。輸出脈寬隨著軟啟動電容電壓的增加而 增加。這使軟啟動期間的占空比可從零增加到最大脈寬。當 軟啟動電壓超過2.8V，軟啟動完成。軟啟動開始于起動或因 過流關斷而复位時。 軟啟動電壓被鉗位在4V. 門极驅動器 ISL6745可灌出和吸收1A峰值電流，且可連接一個MOSFET 驅動器如ISL6700作電平轉移之用。如要限制峰值電流通過 IC，一個外部電阻應連接在IC的推拉輸出(OUTA或OUTB引 腳)和MOSFET的門极之間。而這個小串聯電阻能阻尼由線組 寄生 電感和FET的輸入電容的共振所產生的振蕩。 過流運作 軟啟動周期完成后，過流延遲關斷保護才啟動。如果檢測出 過流情況，軟啟動充電電流電源就會中止，且軟啟動電容通 7 C。 ISL6745 Mini Small Outline Plastic Packages (MSOP) M10.118 (JEDEC MO-187BA) E1 10 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE E SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C 4X θ R1 GAUGE PL ANE SEATING PLANE -CA 4X θ A2 A1 0.10 (0.004) b -H- L L1 SEATING PLANE C -A- e D C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A- and -B-to be determined at Datum plane -H- . 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only NOTES MAX MIN MAX A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e 0.20 (0.008) MILLIMETERS MIN T OP VIEW 0.25 (0.010) INCHES 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - R1 0.003 - θ α 5 o 15 0 o o 6 o 0.07 - 0.07 - 5 o 15 0 o 6 o o Rev.0 12/02 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8