ISL6745EVAL1Z 48V to 12V 120W Half-Bridge Power Supply for Telecom Applications ® Application Note November 5, 2008 AN1439.0 SR HIP2101 UVLO, OVP ISL6720 ISL6745 FIGURE 1. TOP VIEW OF THE ISL6745EVAL1Z EVALUATION BOARD The ISL6745EVAL1Z evaluation board utilizes Intersil’s double-ended voltage-mode PWM controller ISL6745A for half bridge converters with secondary side synchronous rectification. The voltage mode PWM controller ISL6745 is a 10 Ld MSOP device. The input of the evaluation board ranges from 36V to 75V, and the output voltage is regulated to 12V with a maximum load current of 10A. Planar transformers and inductors are used. The triple-output linear regulator ISL6720 is used to provide bias for the primary side controller and drivers. The main specifications are given in the following: • Input voltage: 36V ~ 75V • Output voltage: 12V • Output power: 120W • Output voltage ripple: 50mV • Efficiency: about 90% at full load rated input voltage This application note will give a brief introduction on the operation of the converter, the design constraints, the description of the evaluation board and the performance validation. Figure 1 shows the top view of the evaluation board. Introduction Half-bridge voltage mode converters are widely used in telecommunication systems as an isolated power supply of medium power level because of their simplicity and good performance. Compared with single-ended topologies, such as forward and flyback converters, the voltage stress over the primary switches of the half-bridge is the smallest. The gate driver is also simple. The two switches in the primary side of the transformer can be driven by a symmetrical PWM or asymmetrical PWM, as shown in Figure 2. In a symmetrical PWM scheme, both switches are driven with the 1 same duty ratio and have a deadtime period when both switches are off. The two switches in the primary side are hard-switched and their switching loss will be significant. During this deadtime interval, the synchronous rectification switches in the secondary side are both turned on, which helps to reduce the conduction loss of the SR switches. These features make half-bridge voltage mode converters attractive and cost-effective for low frequency, high current applications. The center-tapped rectification in the secondary side offers some additional advantages. First, the center-tapped structure has twice the frequency than that of the switching frequency. Therefore, the output filter size is smaller compared with converters with the forward structure (such as in an active clamp forward, or flyback). Second, the synchronous rectifier FETs are driven by the voltages from the auxiliary windings, which ensures that both switches are on during such deadtime intervals. The conduction loss in the switches of the center-tapped rectifier is the product of only half of the load current during the deadtime period. Thus, the overall conduction loss is smaller. The ISL6745 is a simplified vision of the ISL6742, which supports the symmetrical PWM of the half-bridge converters with peak current limit and soft-start functions. The simplified circuit schematic of a half bridge converter with diode rectification in the secondary side is shown in Figure 2A The the typical current and voltage waveforms is shown in Figure 2B. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1439 VIN+ C1 S1 +VOUT + C2 RETURN S2 XFORMER GND ISL6720 HIP2101 ISL6745A ISOLATION COMPENSATOR FIGURE 2A. SCHEMATICS BLOCK DIAGRAM VERR C A R R IE R ts S1 D ts t S2 D ts VP CS VSEC tO N VL ID 1 ID 2 FIGURE 2B. SHB CONVERTER WAVEFORM FIGURE 2. THE SYMMETRICAL PWM HALF BRIDGE CONVERTER PWM PATTERNS, AND SECONDARY SIDE RECTIFICATIONS 2 AN1439.0 November 5, 2008 Application Note 1439 Design Criteria For this application, if we allow a 20% adder for transients with a maximum input voltage of 75V, a voltage rating of 100V or higher will suffice. The following specifies the design requirements: • Switching Frequency, fSW: 235kHz The average output current Iout is evenly distributed in the two MOSFETs in the (1 - 2D) interval. As both of the MOSFETs in the primary side are turned off, the load current is supposed to flow evenly in the two SRs, assuming the gate signals are applied. Therefore, the RMS current in each of the SRs is given in Equation 3, where 0 < D < 0.5. • VIN: 48V, Min 36V, Max 75V • VOUT: 12V (nominal) @ IOUT = 8A • POUT: 100W • Efficiency: 85% ~ 90% • Ripple: 1% Is R 1 r m s = Power Stage Design Procedure A symmetrical half-bridge (SHB) converter topology with secondary side central-tape SR is selected for this application. The ISL6745 is used as the PWM controller and HIP2101 is used as FET driver. The relation of the input voltage VIN and output voltage VOUT is given in Equation 1, where D is the duty ratio and N is the transformer turns ratio (N = Ns/Np). = 2 1 ------- ts ( ISR1 ) dt Ts 0 ∫ ⎫ 2 2 1⎧ ----- ⎨ [ 0.5 – D ]ts ( 0.5I OUT ) dt + Dts ( I OUT ) d( t ) ⎬ 0 ts ⎩ Dts ⎭ ∫ ∫ = I OUT 0.75D + 0.125 (EQ. 3) From Equation 3, the conduction loss of the SR can be evaluated according to Equation 4: PSr ON = 2r DS ( ON ) I RMS 2 = 2r DS ( ON ) ( 0.75D + 0.125 )I OUT 2 (EQ. 4) (EQ. 1) V OUT = 2NDV IN According to Equation 1, N should be large enough to ensure the rated output at low line operation. Consider the input range for typical telecommunication applications; the minimum input voltage is 36V. Allowing for some deadtime, a transformer of N = 3/4 can be used. Detailed design of the planar transformer is given in the Intersil Data Sheet “ISL6740, ISL6741: Flexible Double Ended Voltage and Current Mode PWM Controllers,” which can be found at: http://www.intersil.com/data/fn/fn9111.pdf The criteria for selection of the primary side half-bridge FETs and the secondary side synchronous rectifier FETs is largely based on the current and voltage rating of the device. However, the FET drain-source capacitance and gate charge cannot be ignored. The gate charge affects the switching speed of the FETs. Higher gate charge translates into higher drive requirements and/or slower switching speeds. The energy required to drive the gates is dissipated as heat. The FET drain-source capacitance contributes to the switching losses in the SHB, since this portion of energy is not recycled, as in a soft-switched or zero-voltage switched converter. The maximum input voltage, VIN, plus transient voltage, determines the voltage rating required. For the symmetrical half-bridge converter, the voltage across the two primary side MOSFETs is half of the input voltage at steady state. That is, VP = 0.5VIN. The secondary side SR FET voltage stress is twice the transformer second side voltage and is expressed in Equation 2: V S = 2 • 0.5NV IN = NV IN In order to avoid the hard turn-on of the SR, a delay resistor is needed to create the delay of the gate signal, so that the current first flows into the anti-parallel diode of the SRs. A diode is placed in parallel with the delay resistor in order to speed up the turn-off of the SRs and avoid shoot-through. The gate drive loss of the SRs are a function of the switching frequency, driving voltage and Q, as expressed in Equation 5. 2 P GATE = C GATE V fs (EQ. 5) When the primary switch is turned on, it conducts the output inductor current. The primary switch does not conduct current when it is turned off. Therefore, the RMS current in the primary switch is evaluated in Equation 6. I PRMS = = 2 1 ----- ts ( ISR1 ) dt ts 0 ∫ (EQ. 6) ⎫ 2 1⎧ ----- ⎨ Dts ( NI OUT ) d( t ) ⎬ = I OUT N D ts ⎩ 0 ⎭ ∫ The conduction loss of the primary switches can be estimated using Equation 7: PPr ON = 2r DS ( ON ) I PRMS 2 = 2r DS ( ON ) D ( NI OUT ) 2 (EQ. 7) The switching loss of the primary side MOSFET consists of two parts: 1) the overlap of the current and voltage and, 2) the discharge of the charges of the drain-source capacitance of the FET. The switching loss can be estimated using Equation 8: PPr SW = 2I PR V FS (EQ. 8) (EQ. 2) 3 AN1439.0 November 5, 2008 Application Note 1439 Therefore, the total loss that occurred in the switches can be estimated using Equation 9: P LOSS = PSrON + P GATE + PPrSW + PPr ON (EQ. 9) Fairchild FDS3672 FETs, rated at 100V and 7.5A (rDS(ON) = 22m), were selected for the half-bridge switches. The synchronous rectifier FETs must withstand approximately 75% of the input voltage assuming no switching transients are present. A device capable of withstanding at least 55V is required. Empirical testing in the circuit revealed switching transients of 20V were present across the device indicating that a rating of at least 75V is required. The RMS current rating of 7.07A for each SR FET requires a low rDS(ON) to minimize conduction losses. It was decided to use two devices in parallel to simplify the thermal design. The voltage of the output inductor L is related to the secondary side voltage VSEC and output voltage VOUT. V L = V SEC – V OUT voltage-mode pulse width modulator. The opto-coupler is used to transfer the error signal across the isolation barrier. The major components of the feedback control loop are a programmable shunt regulator and an opto-coupler.The opto-coupler offers a convenient means to cross the isolation barrier, but it adds complexity to the feedback control loop. It adds a pole at about 10kHz and a significant amount of gain variation due to the current transfer ratio (CTR). The CTR of the opto-coupler varies with initial tolerance, temperature, forward current, and age. PWM PWM V OUT SHB R FB2 C FB1 C FB2 VCOMP OPTOCOUPLER R FB3 C FB3 R FB1 V ERR R FB4 + V REF (EQ. 10) Therefore, the ripple current through the output inductor is given in Equation 11. The frequency of the ripple current is twice that of the switching frequency. NV IN ( 1 – 2D ) ΔIL = ------------------------------------2LFS (EQ. 11) Clearly, from the ripple current point-of-view, a large inductor is preferable. However, the current slew rate will be impaired. The inductor and output capacitor contributes one double pole at the resonant frequency of the filter, indicating a narrow bandwidth with a large inductor. With a maximum input voltage of 75V, the minimum duty ratio D is about 0.25. If we allow an inductor current ripple of 5% of the rated output current, the minimum inductance required can be calculated according to Equation 12. Here, an inductor of 2µH is selected. V L • t ON L > ----------------------ΔIL (EQ. 12) Under steady state operating conditions, the ripple current in the capacitor is small, so it would seem appropriate to have a low ripple current rated capacitor. However, a high rated ripple current capacitor was selected based on the nature of the intended load and multiple buck regulators. In order to minimize the output impedance of the filter, a Sanyo OSCON 16SH150M capacitor was placed in parallel with a 22µF ceramic capacitor. FIGURE 3. SYSTEM BLOCK DIAGRAM From the small signal model of the half bridge converter, the control to output transfer function frequency dependence is a function of the output load resistance, the value of output capacitor and inductor, and the output capacitance ESR. These variations must be considered when compensating the control loop. The worst case small signal operating point for a voltage mode converter tends to be at maximum VIN, maximum load, maximum COUT, and minimum ESR. The pole and zero of the transfer function are given in Equation 13. s1 + -----V OUT ( S ) VN S ωz G ( s ) = ----------------------- = ------------------ -------------------------------------------VC ( S ) 2N P V S s 2 s 1 + ------------ + ⎛ -------⎞ ⎝ω ⎠ Qω o o (EQ. 13) where: Q = ( RO ) ⁄ ( ω o L ) ω o = 1 ⁄ ( ( CO L ) ) ωz = 1 ⁄ ( C O R C ) (EQ. 14) (EQ. 15) (EQ. 16) RO is the equivalent output load resistance L is the output inductance CO is the output capacitor Control Stage Design Procedure RC is the ESR of the output capacitor The ISL6745EVAL1Z demonstration platform implements a feedback control by means of the opto-coupler and Type 3 Error Amplifier. The system block diagram is shown in Figure 3. SHB is the symmetrical half-bridge converter consisting of the primary switches, transformer and the output filter. PWM is the VS is the peak of the sawtooth ramp signal for PWM modulation. 4 The loop compensation is placed around the Error Amplifier (EA) on the secondary side of the converter. A Type 3 error AN1439.0 November 5, 2008 Application Note 1439 0 -20 -40 PHASE OF SHB (dB) amplifier configuration was selected. The Type 3 compensation configuration has three poles and two zeros, and the configuration depends on the bandwidth requirement. The higher the desired bandwidth of the converter, the more difficult it is to create a solution that is stable over the entire operating range. A good rule of thumb is to limit the bandwidth to about fSW/4, where fSW is the switching frequency of the converter. However, due to the bandwidth constraints of the opto-coupler and the LM431 shunt regulator, the bandwidth was reduced to about 25kHz. -60 -80 -100 -120 -140 The first pole is placed at the origin by default (C20 is an integrating capacitor) which results in excellent DC regulation. If the two zeroes are placed at the same frequency, they should be placed at fLC/2, where fLC is the resonant frequency of the output L-C filter. To reduce the gain peaking at the L-C resonant frequency, the two zeroes are often separated. When they are separated, the first zero can be placed at fLC/5, and the second at just above fLC. The second pole is placed at the lowest expected zero cause by the output capacitor ESR. The third, and last pole is placed at about 1.5 times the crossover frequency. Some liberties where taken with the generally accepted compensation procedure previously described due to the transfer characteristics of the opto-coupler. The effects of the opto-coupler tend to dominate over those of the LM431 so the GBWP effects of the LM431 are not included here. 20 GAIN OF SHB (dB) -180 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 5. THE CONTROL TO OUTPUT PHASE OF THE SHB Referring to the circuit block diagram, the transfer function of the Type 3 can be expressed in Equation 17: V ERR ( S ) G EA ( S ) = ----------------------VO ( S ) ( 1 + sC FB2 R FB1 ) ( 1 + sC FB3 ( R FB2 + R FB3 ) ) = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------C FB1 C FB2 R FB1⎞ ⎛ s ( C FB1 + C FB2 )R FB2 ) ( 1 + sC FB3 R FB3 ) ⎜ 1 + s --------------------------------------------⎟ C FB1 + C FB2 ⎠ ⎝ (EQ. 17) If RFB2>>RFB3, CFB2>>CFB1, the transfer function in Equation 17 can be reduced to the following: 10 V ERR ( S ) ( 1 + sC FB2 R FB1 ) ( 1 + sC FB3 R FB2 ) - = -----------------------------------------------------------------------------------------------------------------------------G EA ( S ) = ----------------------VO ( S ) sC FB1 R FB2 ( 1 + sC FB3 R FB3 ) ( 1 + R FB1 C FB1 ) (EQ. 18) 0 -10 Then the poles and zeros can be determined with the Equations 19 through 22. -20 -30 -40 -50 -160 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 4. THE CONTROL TO OUTPUT GAIN OF THE SHB 5 1 ωp2 = ----------------------------------( C FB1 R FB1 ) (EQ. 19) 1 ωP3 = ---------------------------------( C FB3 R FB3 ) (EQ. 20) 1 ωz2 = ----------------------------------( C FB3 R FB2 ) (EQ. 21) 1 ωz1 = ----------------------------------( C FB2 R FB1 ) (EQ. 22) 60 0 50 -20 40 -40 LOOP PHASE (dB) COMP GAIN (dB) Application Note 1439 30 20 10 -60 -80 -100 0 -120 -10 -140 -20 1 10 100 1k 10k 1M 10M -160 1 10 100 1k 10k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 9. LOOP PHASE MARGIN FIGURE 6. TYPE 3 ERROR AMPLIFIER (EA-3) The loop transfer function Bode plots are given in Figures 8 and 9 for full load rated input voltage. Checking these plots, one will notice that the design gives 90° of phase margin and more than 40dB of gain margin. 40 COMP PHASE (dB) 20 Evaluation Board and Performance 0 The ISL6745EVAL1Z evaluation board is a 4-layer, 4.55”x1.87” RoHS compliant board. All the components are assembled in the top layer. The bill of materials, schematic, and waveforms are given in the following pages. -20 -40 When applying power to the evaluation board, certain precautions need to be followed. -60 -80 -100 1 10 100 1k 10k FREQUENCY (Hz) 1M 10M FIGURE 7. TYPE 3 ERROR AAMPLIFIER (EA-3) 80 LOOP GAIN (dB) 60 1. Powering Considerations: When operated at low input voltages, the evaluation board can draw up to 3.5A of current at a full load of 8A. It is important to choose the correct connector and wire size when attaching the source supply and the load. Monitor the input and output currents. An appropriate power supply is needed with adjustable output voltage (up to 100V) and current (up to 5A). The power supply must be of low impedance to avoid any interaction between the droop of the power supply and the undervoltage-lock-out protection of the evaluation board. 2. Loading Considerations: It is important to choose the correct connector and wire size when attaching the load. An appropriate electronic load with current up to 10A is desirable. The equivalent resistance of the load is 1.2Ω. Therefore, the connection wires should be thick enough. For accurate efficiency measurement, it is important to monitor the voltage directly at the output terminals of the evaluation board (preferably at the point of feedback) because the voltage drop across the load connecting wires will give inaccurate measurements. 40 20 0 -20 -40 1 10 100 1k 10k FREQUENCY (Hz) 1M 10M 3. Air Flow Conditions: Full rated power should never be attempted without providing the specified 200 CFM of air flow over the evaluation board. This can be provided by a stand-alone fan. FIGURE 8. LOOP GAIN MARGIN 6 AN1439.0 November 5, 2008 Application Note 1439 4. For the first time power-up, it is suggested to apply light load, and set the current limit of the source supply to less than 1.5 times of the wattage of the load. A quick efficiency check is the best way to confirm that everything is operating properly. It is common that the incorrect circuit parameters will affect the efficiency adversely. 5. When the current limit set on the source supply is insufficient for the load, the interaction of the source supply folding back and the evaluation board going into undervoltage shutdown will start an oscillation, or chatter, which may have highly undesirable consequences. 6. To measure the output voltage ripple more accurately, it is suggested to measure as closely as possible to the converter’s output terminals. Since the signal being measured is in the millivolt range, the measurement set-up can be susceptible to picking up noise from external sources. The bandwidth of the oscilloscope can be set to 20MHz. Use very short and direct connections to the oscilloscope probe such that the total loop area in the signal and ground connections is as small as possible. Some important waveforms are shown in the “Typical Performance Curves” on page 8. VOLT-METER 100V 5A POWER SUPPLY WITH CURRENT METER Figures 11 and 12 show the ramp signal and the gate signal of the controller ISL6745. The frequency should match the waveform. The gate signals from the ISL6745A are sent to the half-bridge MOSFET driver HIP2101 for the two switches, and they should be symmetrical and 180° out-of-phase. Figure 13 shows the gate drive signals of the primary side switches. These signals are generated from HIP2101, the operation voltage of which is set by the ISL6720. Figure 14 shows the typical current signal. The current signal should be less than 1V. Figures 15 and 16 show the drive signals and drain-source signals of the synchronous rectification in the secondary side. The load/line regulation and efficiency curves are shown in Figures 17 and 18. The circuit has maximum efficiency at low line half load conditions. As the line voltage increases, the switching loss of the primary side MOSFET increases. The gate drive loss of the secondary side also increases as the gate drive loss is related to CV2. As the duty ratio becomes small, the ripple in the inductor increases, and this leads to big transformer AC loss and rectifier reverse recovery loss, in addition to the AC loss of the output inductor. The efficiency drops significantly at high line voltages due to the incremental loss. VOLT-METER + + INPUT OUTPUT - - 100W 10A ELECTRONIC LOAD WITH CURRENT METER OSCILLOSCOPE FIGURE 10. TYPICAL BENCH TEST SETUP 7 AN1439.0 November 5, 2008 Application Note 1439 Typical Performance Curves FIGURE 11. RAMP SIGNAL FIGURE 12. GATE SIGNALS FROM ISL6745 FIGURE 13. DRIVE SIGNALS FOR THE PRIMARY SWITCHES FIGURE 14. DRIVE SIGNAL AND CURRENT SIGNAL FIGURE 15. SECONDARY SIDE GATE DRIVE SIGNALS FIGURE 16. SECONDARY SIDE DRIVE SIGNAL AND DRAIN SOURCES 8 AN1439.0 November 5, 2008 Application Note 1439 Typical Performance Curves 12.150 95 VIN = 36V 12.145 VIN = 36V 90 85 12.135 EFFICIENCY (%) OUTPUT VOLTAGE (V) 12.140 VIN = 60V 12.130 VIN = 48V 12.125 12.120 12.115 VIN = 48V 80 75 VIN = 60V 70 12.110 65 12.105 12.100 0 60 2 4 6 8 LOAD CURRENT (A) FIGURE 17. LINE AND LOAD REGULATION FIGURE 19. OUTPUT VOLTAGE RIPPLE AT 8A LOAD CURRENT, VIN = 36V 9 10 0 2 4 6 8 10 12 LOAD CURRENT (A) FIGURE 18. EFFICIENCY vs INPUT AND LOAD FIGURE 20. OUTPUT VOLTAGE RIPPLE AT 8A LOAD CURRENT, VIN = 60V AN1439.0 November 5, 2008 Application Note 1439 ISL6745EVAL1Z Layout FIGURE 21. LAYER 1 FIGURE 22. LAYER 2 FIGURE 23. LAYER 3 10 AN1439.0 November 5, 2008 Application Note 1439 ISL6745EVAL1Z Layout (Continued) FIGURE 24. LAYER 4 11 AN1439.0 November 5, 2008 ISL6745EVAL1Z Schematic 12 Application Note 1439 AN1439.0 November 5, 2008 Application Note 1439 TABLE 1. BILL OF MATERIALS PART NUMBER QTY ISL6745EVAL1ZREVAPCB 1 16SH150M 1 GRM21BR71H105KA12L REFERENCE DESIGNATOR DESCRIPTION MANUFACTURER PWB-PCB, ISL6745EVAL1Z, REVA, ROHS TITAN C9 CAP, TH, RADIAL, 150µF, 16V, 20%, OSCON SANYO 2 C13, C32 CAP, SMD, 0805,1.0µF, 50V, 10%, X7R, ROHS MURATA GRM43ER72A225KA01B 2 C2, C3 CAP, SMD, 1812, 2.2µF, 100V, 10%, X7R, ROHS MURATA H1045-00101-50V5-T 3 C16, C19, C27 CAP, SMD, 0603, 100pF, 50V, 5%, COG, ROHS H1045-00102-100V10-T 2 C5, C26 CAP, SMD, 0603, 1000pF, 100V, 10%, X7R, ROHS VENKEL H1045-00104-50V10-T 6 C14, C17, C18, C23, C29, C33CAP, SMD, 0603, 0.1µF, 50V, 10%, X7R, ROHS TDK H1045-00221-100V10-T 4 C4, C15, C22, C24 CAP, SMD, 0603, 220pF, 100V, 10%, X7R, ROHS PANASONIC H1045-00224-25V10-T 1 C25 CAP, SMD, 0603, 0.22µF, 25V, 10%, X7R, ROHS TDK H1045-00225-16V10-T 1 C21 CAP, SMD, 0603, 2.2µF, 16V, 10%, X5R, ROHS MURATA H1045-00471-50V5-T 1 C20 CAP, SMD, 0603, 470pF, 50V, 5%, NPO, ROHS PANASONIC H1065-00106-25V10-T 1 C28 CAP, SMD, 1206, 10µF, 25V, 10%, X5R, ROHS VENKEL 1 C1 CAP, SMD, 2220, 4.7µF, 100V, 10%, X7R, ROHS TDK H1087-00104-100V10-T 2 C30, C31 CAP, SMD, 1812, 0.1µF, 100V, 10%, X7R, ROHS VENKEL H1087-00226-25V20-T 2 C8, C10 CAP, SMD, 1812, 22µF, 25V, 20%, X7R, ROHS H1087-00561-100V10-T 2 C11, C12 CAP, SMD, 1812, 560pF, 100V, 10%, X7R, ROHS VENKEL DR73-1R0-R 1 L1 COIL-PWR inductor, 7.6mm, 1.0µH, 20%, 5.28A COOPER HM65-H4R0LF 1 L2 INDUCTOR, SMD, 13X12, 4.0µH, 20%, 10.3A, ROHS BI TECHNOLOGIES 1514-2 4 P1, P2, P3, P4 CONN-TURRET, TERMINAL POST, TH, ROHS KEYSTONE 5002 14 TP1-TP5, TP9-TP17CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS KEYSTONE 5007 3 TP6, TP7, TP8 CONN-COMPACT TEST, VERTICAL, WHT, ROHS KEYSTONE 12CWQ06FNPBF 1 CR5 DIODE-RECTIFIER, SMD,D-PAK, 60V, 12A, ROHS IRF 1 CR11 DIODE, SMD, SOT-23, 30V, 50mA, ROHS FAIRCHILD BAT54-T 5 CR3, CR4, CR6, CR7, CR8SCHOTTKY, SMD, SOT23, 3P, 30V, 200mA, SINGLE FAIRCHILD BAT54S-T 2 CR1, CR2 SCHOTTKY, SMD, SOT23, 3P, 30V, 200mA, DUAL FAIRCHILD 1 VR2 ZENER, SMD, SOT23, 3P, 6.8V, 225mW, ROHS ON SEMI 2 CR9, CR10 DIODE-RECTIFIER, SMD, 2P, SMA, 100V, 1A, ROHS DIODES INC. 1 VR1 ZENER, SMD, SOT-23, 3P, 13V, 350mW, ROHS ON SEMI HIP2101IBZ 1 U1 IC-HALF BRIDGE DRIVER, 8P, SOIC, 100V, ROHS INTERSIL ISL6720AARZ 1 U6 IC-100V LINEAR REGULATOR, DFN, 4X4, ROHS INTERSIL ISL6745AUZ 1 U3 IC- CONTROLLER, 10P, MSOP, ROHS INTERSIL LM393M 1 U7 IC-DUAL COMPARATOR, 8P, SOP, ROHS FAIRCHILD 1 U5 DNP 1 U2 IC-HI ISO PHOTOCOUPLER, 4P, SSOP, ROHS ES1B-13-F PS2801-1-A 13 PANASONIC TDK CA EASTERN LAB AN1439.0 November 5, 2008 Application Note 1439 TABLE 1. BILL OF MATERIALS (Continued) PART NUMBER QTY REFERENCE DESIGNATOR DESCRIPTION MANUFACTURER 1 U8 DNP LM431BIM3 1 U4 Shunt regulator FDS3672-T 6 Q1, Q2, QR1, QR2, QR3, QR4, N-CHANNEL, 8P, SO-8, 100V, 7.5A, ROHS FAIRCHILD H2511-00010-1/10W1-T 3 R46, R47, R48 RES, SMD, 0603, 1Ω, 1/10W, 1%, TF, ROHS PHILLIPS H2511-00030-1/10W1-T 2 R7, R8 RES, SMD, 0603, 3Ω,1/10W, 1%, TF, ROHS VENKEL H2511-00100-1/10W1-T 1 R33 RES, SMD, 0603, 10Ω, 1/10W, 1%, TF, ROHS KOA H2511-001R5-1/10W1-T 2 R50, R52 RES, SMD, 0603, 1.5Ω,1/10W, 1%, TF, ROHS VENKEL H2511-00R00-1/10W-T 4 R26, R31, R45, R54 RESISTOR, SMD, 0603, 0Ω, 1/10W, TF, ROHS H2511-01000-1/10W1-T 4 R11, R15, R29, R30 RES, SMD, 0603, 100Ω, 1/10W, 1%,TF, ROHS H2511-01001-1/10W1-T 5 R34, R36, R44, R51, R53RES, SMD, 0603, 1k, 1/10W, 1%, TF, ROHS KOA H2511-01002-1/10W1-T 3 R17, R18, R16 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS 2 R9, R10 DNP H2511-01003-1/10W1-T 2 R27, R28 RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS H2511-01133-1/10W1-T 1 R21 RES, SMD, 0603, 113k, 1/10W, 1%, TF, ROHS PANASONIC H2511-01433-1/10W1-T 1 R25 RES, SMD, 0603, 143k, 1/10W, 1%, TF, ROHS VENKEL H2511-02001-1/10W1-T 1 R37 RES, SMD, 0603, 2k, 1/10W, 1%, TF, ROHS KOA H2511-02002-1/10W1-T 3 R20, R22, R24 RES, SMD, 0603, 20k, 1/10W, 1%, TF, ROHS VENKEL R42, R43, R44 DNP National Semi KOA KOA H2511-02200-1/10W1-T 2 R12, R42 RES, SMD, 0603, 220Ω, 1/10W, 1%, TF, ROHS YAGEO H2511-02493-1/10W1-T 1 R39 RES, SMD, 0603, 2.49k, 1/10W, 1%, TF, ROHS YAGEO H2511-02803-1/10W1-T 1 R23 RES, SMD, 0603, 280k, 1/10W, 1%, TF, ROHS PANASONIC H2511-03011-1/10W1-T 1 R32 RES, SMD, 0603, 3.01k, 1/10W, 1%, TF, ROHS KOA H2511-03833-1/10W1-T 1 R43 RES, SMD, 0603, 3.83k, 1/10W, 1%, TF, ROHS VENKEL H2511-04221-1/10W1-T 1 R38 RES, SMD, 0603, 4.22k, 1/10W,1%,TF,ROHS ROHM H2511-04990-1/10W1-T 2 R35, R41 RES,SMD, 0603, 499Ω, 1/10W, 1%, TF, ROHS KOA H2511-05101-1/10W1-T 1 R19 RES, SMD, 0603, 5.11k, 1/10W, 1%, TF, ROHS KOA H2511-09533-1/10W1-T 1 R40 RES, SMD, 0603, 9.53k, 1/10W, 1%, TF, ROHS VENKEL H2512-06R34-1/8W1-T 2 R13, R14 RES, SMD, 0805, 6.34Ω, 1/8W, 1%, TF, ROHS VENKEL H2513-01000-1/4W1-T 1 R49 RES, SMD, 1206, 100Ω, 1/4W, 1%, TF, ROHS STACKPOLE H2515-003R3-1W1-T 1 R1 RES, SMD, 2512,3.3Ω, 1W, 1%, TF, ROHS KOA H2515-018R2-1W1-T 1 R4 RES, SMD, 2512, 18.2Ω, 1W, 1%, TF, ROHS KOA H2515-02001-1W1-T 1 R2 RES, SMD, 2512, 2k, 1W, 1%, TF, ROHS PANASONIC H2515-04021-1W1-T 1 R3 RES, SMD, 2512, 4.02k, 1W, 1%, TF, ROHS PANASONIC 31660-LF1 1 T1 TRANSFORMER, SMD, 27.9X21.6, 83µH, 25%, 10kHz, CUSTOM, ROHS MIDCOM P8205NL 1 T2 TRANSFORMER-CURRENT SENSE, SMD, 8P, 500µH,10A, ROHS PULSE 14 AN1439.0 November 5, 2008 Application Note 1439 TABLE 1. BILL OF MATERIALS (Continued) PART NUMBER QTY REFERENCE DESIGNATOR DESCRIPTION SJ-5003-BLACK 4 Bottom four corners. BUMPONS, 0.44” W x 0.20” H, DOMETOP, BLACK 3M 8X12-STATIC-BAG 1 Place assy in bag. BAG, STATIC, 8X12, ZIP LOC INTERSIL LABEL-SERIAL NUMBER 1 MANUFACTURER LABEL, FOR SERIAL NUMBER AND BOM REV # All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 AN1439.0 November 5, 2008