Logic selection guide 2016 Standard Logic and Mini Logic in leaded and leadless packages 2 NXP Logic selection guide 2016 Standard Logic and Mini Logic: tuned for today’s systems Logic may have been around since the days when engineers still used slide rules, but logic is still an essential part of embedded design. It’s the go-to resource for I/O expansion and interfacing between analog and digital domains, but that’s just the beginning. In many ways, today’s designers need logic 4 Enables quick reconfiguration, by adding gates outside the core logic or MCU, for selection of debugging and functional modes more than ever. Why? Because today’s systems need to be smaller, more power efficient, and more portable than ever before. That means managing tight layouts, and dealing with looped traces, which can generate cross-talk and create signal-integrity issues. It also means working with multi-layer boards, implementing real-time 4Provides the interface between peripherals, by performing level translation, reset control, power sequencing, signal switching, signal isolation, and so on 4 Uses low-power functions to add new features without overtaxing the battery 4 Enables the integration of touchscreens and responses to real-world events, and supporting multitasking operations. In many cases, the right logic device makes these things easier to manage, and helps optimize operation. touchpads with multiplexers, shifters, and latches 4 Implements video switching between different displays and video formats by doing format conversion, adapting interfaces to controllers, and multiplexing/demultiplexing the connectors 4 E xtends GPIO and drives LEDs 4 Supports automotive applications by implementing simple motor control, smart key detection, security alarms, speed alerts, and more Here are just some of the ways that Standard and Mini Logic works in today’s embedded systems: NXP Logic selection guide 2016 3 Table of contents Standard Logic and Mini Logic: tuned for today’s systems 3 Where logic really stands out 6 NXP is the #1 volume leader 7 Combination and configurable logic 8 Our approach to quality 11 Portfolio overview 12 Special features 15 Bus hold Source termination Overvoltage-tolerant inputs Overvoltage-tolerant outputs Power-off leakage (IOFF) circuitry Schmitt-trigger inputs Live insertion Low-threshold inputs Open-drain outputs Input-clamping diodes Low delay isolation High-voltage families HEF4000B logic HC(T) logic AHC(T) logic VHC(T) logic XC7 logic NPIC logic CBT(D) logic Low-voltage families 4 Product listing by function 16 17 18 19 19 20 21 22 23 23 24 25 25 28 38 42 43 44 45 46 LV logic LVC logic ALVC logic LVT logic ALVT logic 46 48 54 56 58 AVC(M) logic AUP logic AXP logic CBTLV(D) logic 59 60 63 64 NXP Logic selection guide 2016 65 Analog switches Buffers/inverters/drivers Bus switches Counters/frequency dividers Decoders/demultiplexers Digital comparators Digital multiplexers Encoders FIFO registers 66 68 75 76 78 80 80 81 82 Flip-flops Full adders Gates AND gates Combination gates EXCLUSIVE-OR gates EXCLUSIVE-NOR gates NAND gates NOR gates OR gates Latches / registered drivers Level shifters/translators Multivibrators Parity generators/checkers Phase-locked loops Schmitt triggers Shift registers/LED drivers Transceivers 82 86 87 87 88 89 89 90 92 93 94 96 98 99 99 100 102 104 Q100 Standard Logic functions & packages 107 Analog switches Buffers/inverters Bus switches Counters/frequency dividers Digital decoders/demultiplexers Flip-flops Digital multiplexers Gates Latches/registered drivers 107 108 110 110 111 112 112 114 116 Multivibrators Level shifters/translators Shift registers Schmitt triggers 117 117 118 118 Transceivers Standard logic packages 120 121 Q100 Mini Logic functions & packages 122 Bus switches Analog switches Buffers/inverters Flip-flops Digtial multiplexers Digtial decoders/demultiplexers Gates 122 122 123 125 125 125 126 Multivibrators Scmitt-triggers Latches/registered drivers Mini Logic packages Level shifters/translators 128 128 128 129 129 Packages 130 Nomenclature 133 Package diagrams 134 SOT353 SOT363 SOT457 SOT505-2 SOT650-1 SOT753-1 SOT765-1 SOT833-1 SOT886 SOT891 SOT902-2 SOT996 SOT1049-3 SOT1081-1/2 SOT1089 SOT1202 SOT1203 SOT1226 134 134 135 135 136 136 137 137 138 138 139 139 140 140 141 141 142 142 SOT815-1 SOT402-1 SOT403-1 SOT360-1 143 143 144 144 SOT337-1 SOT338-1 SOT339-1 SOT519-1 SOT724-1 SOT1174 SOT1161 SOT137-1 SOT556-1 SOT340-1 SOT355-1 145 145 146 146 147 147 148 148 149 149 150 SOT815-1 150 Design tools 151 Competitive cross reference 154 Where logic really stands out Logic is great for making minor modifications and fine-tuning performance in the later design stages, but that’s not all it can do. Today’s logic devices let you add features and improve functionality, so you can meet your design requirements right from the start, even before you need to think about lastminute revisions. ASIC-driven systems In systems that use application-specific integrated circuits (ASICs), logic gates can be used to provide control or “glue” functions. Modern logic families Computing In tablets and laptops, logic can be used for battery charging and discharging blocks, and to provide standby mode, power-down, and start-up control include features, such as overvoltage tolerance, that enable them to be used as glue logic between ASICs that use different supply voltages. In some cases, this can extend the lifetime of legacy ASICs. Available in small-footprint packages, such as PicoGate, MicroPak, and Diamond, today’s glue logic is suitable for space-constrained applications. sequences. In docking stations and systems that support multiple displays, logic provides the bus switches, resets, and audio blocks that reduce the impact of noisy signals, and can be used to buffer the clock and data signals. MCU-driven systems In systems that use a microcontroller (MCU), logic products are used for low-cost I/O expansion. Shift registers are used for digital I/O expansion, and analog switches are used to multiplex analog sensor inputs. The combination of the two enables the selection of lower-pincount MCUs with fewer analog-to-digital converters. When used this way, standard logic enables true cost optimization of an application. Dual supply-voltage translators make it possible to use MCU-based systems across multiple supply-voltage domains. 6 NXP Logic selection guide 2016 Mobile In mobile devices such as smartphones, tablets, and cameras, logic provides multiplexing, buffering, and level-translation functions for the baseband, RF interfaces, memory, and other peripherals. Audio Logic buffers are used in external speakers and other high-end audio equipment to buffer the clock, sync, and data signals sent to the audio interface and docking station. NXP is the #1 volume leader For the last 50 years, NXP’s logic business has supported the growing global demand for logic. Today, as the No. 1 volume logic supplier, we offer a remarkably broad portfolio of cutting-edge solutions and best-in-class packages. Add this to our ability to support high-volume requirements, and our reputation as a trusted supplier of exceptionally high quality, and NXP is the logical choice as a partner for the long term. Selection formats, so you can be confident that, whichever We offer thousands of products, so it’s easier to find what you want, when you want it. You can be certain that our portfolio has just the right combination of functions, packages, and operating voltages. We also offer special features that make your work easier, by simplifying design, increasing performance, adding flexibility, or all of the above. package you select, it will be available for as long as you need it. Innovation Logic continues to evolve, and that means our portfolio does, too. We consistently deliver new ideas, whether it’s higher integration, lower power, smaller packaging, or just a better way to do things. Combination logic, for example, provides more than one function in a single package, so you can do more with a single inventory item. Another example is configurable logic, which lets you use a single package to configure up to nine different functions. The benefits are better system performance with a lower bill of materials, and a smaller board. Packaging We are a recognized leader in packaging technology, and offer the industry’s largest portfolio of logic functions in leadless DQFN, MicroPak, and Diamond packages. That includes more than 50 leadless packages, all of which are qualified for use in automotive applications. And, while we offer a wide range of the latest leadless formats, we also understand that legacy packages, like SO and TSSOP, still have their place in some designs. We continue to support these older Voltages Today’s systems often include products that work at different operating voltages, and there’s no single voltage that works for every system. We offer a wide variety of operating voltages to choose from, so you can simplify your selection process and improve system performance. Look for coverage in both the low and the high end of the operating range, from 0.8 to 5 V and beyond. Ruggedness If you’re designing a system that needs to perform in rugged environments, our many products that conform to the automotive standard AEC-Q100 can help you meet the necessary requirements. Our automotive logic devices have been verified to perform at higher temperatures, and can be counted on to provide reliable operation in tough situations. Commitment Having a partner you can count on makes it easier to meet deadlines and complete designs. At NXP, we are fully committed to the logic market and continue to invest in new process technologies, new packaging technologies, and new manufacturing facilities. These are the things that keep our portfolio competitive, and ensure our longevity as technology partner. NXP Logic selection guide 2016 7 Combination and configurable logic NXP’s combination and configurable logic devices make it possible to do more with less, because they give you more ways to implement the “glue” logic functions commonly found in today’s complex systems. These flexible and innovative single-package solutions let you replace discrete logic solutions with a configurable or combination logic device, so you can potentially reduce pin count, device count, system cost, and assembly-related expenses. These devices can also simplify inventory control and reduce qualification effort, since there are fewer discrete logic devices to deal with. What is combination logic? makes pick-and-place operations more efficient, and Combination logic places two or more dissimilar functions in a single package. The functions can either be internally cascaded or fully independent. lowers the cost of assembly. Combining functions also reduces the footprint of the solution and, if the devices are internally cascaded, simplifies the PCB layout. Benefits of combination logic Combination logic reduces the number of components in the bill of materials (BOM), and that improves logistics, Learn more: www.nxp.com/logic 0832 COMBINATION A B C 3208 COMBINATION 1 OR 3 4 6 Y 3 INPUT OR – AND Combination logic = one package, two or more different functions 8 NXP Logic selection guide 2016 A B C 1 3 4 6 3 INPUT AND – OR Y What is configurable logic? Configurable logic places up to nine functions in a single package. These functions include 2-input AND, OR, NAND, NOR, XOR, or XNOR gates, plus inverters and buffers, and a 2:1 mux. The logic function is selected by connecting input pins to either GND or VCC. Schmitt-trigger inputs are standard. Low inputthreshold options are included in NXP’s portfolio, to interface between different supply-voltage domains. device requires only one tape-and-reel position in the pick-and-place machine, and this increased efficiency lowers the assembly cost. Benefits of configurable logic Using a configurable logic device to replace three components in an application (an inverter, a buffer, and an AND gate, for example), means only one device needs to be qualified, not three. Similarly, from a logistics standpoint, the configurable device replaces three types on the BOM, and this reduces inventory costs. In the manufacturing phase, the configurable can mean lower system cost, improved inventory management, and fewer qualification expenses during development. Simply put, dual PCB configurable logic is the next step in logic design. A C A C B C Y Dual PCB configurable logic for more ways to save space and lower cost Dual PCB configurable logic from NXP combines two configurable logic devices in a single package. It gives engineers a more flexible, more economical way to implement control logic solutions. These advantages Learn more: www.nxp.com/logic B C Y B C Y B C Y Y Y B B C Y Y A C Y A C Y A Y Configurable logic = one package, nine or more functions NXP Logic selection guide 2016 9 10 NXP Logic selection guide 2016 Our approach to quality At NXP, we recognize the vital importance of quality in electronic components, and understand its critical effect on the viability and economics of finished equipment. This is especially true for semiconductors, which often perform critical circuit functions in harsh environments. Our commitment to quality means we continuously strive to improve our products and processes to ensure they reach the highest possible quality standards. Zero-defect program We have an NXP-wide “zero-defect” quality program in Green products place, and view it as a part of our everyday way of doing Concern for the environment has driven us to offer a business. Our pursuit of improvement is ongoing, as we broad portfolio of Dark Green products that are free strive to eliminate incidents in production, reduce the of lead and halogen, and we comply fully with the rate of incoming complaints, and lower the defect-per- European Union’s Restriction on Hazardous Substances billion (DPB) level to zero. (RoHS) Directive 2002/95/EC. Six-Sigma program Automotive portfolio As part of our overall corporate strategy, we involve the To support automotive applications and other entire organization in process improvement. “Design applications that operate under extreme conditions, for Six-Sigma” and “Design for eXcellence” (DfX) are we offer the –Q100 portfolio. These are all qualified to embedded in our processes for creating products. NXP's internal automotive grade, which exceeds the In production, we employ a structured approach to requirements required by the Automotive Electronics identifying outliers (maverick lots) and defects, and Council AEC-Q100 standard. remove them from the manufacturing process to minimize any spill-over effect. Certifications and standards We have achieved certification for all the international Safe-Launch (DfX) standards relevant to our industry, including ISO/IEC Our guiding philosophy for all product launches is to 9001, ISO/IEC 14001, and OHSAS 18001, as well as ISO/ achieve a best-in-class DPB level immediately, at the TS 16949 and VDA 6.3 (for automotive sites). start of production. Complaint handling In cooperation with customers, we use continual process improvement to achieve best-in-class performance in handling complaints and solving problems. NXP Logic selection guide 2016 11 Portfolio overview From old favorites to new innovations We help reduce complexity while adding flexibility, by We offer one of the broadest selections of logic, from offering a long list of special features available across mature BiCMOS families to the latest in advanced, low- a number of families. Also, to support industrial and power CMOS technology. We constantly find ways to automotive applications, our logic is available in options reduce power consumption and minimize footprint. Our that are characterized and specified from -40 to +125 °C. advanced CMOS processes deliver robust performance, and are the reason why we can provide so many low- The NXP logic portfolio includes: power families that support low-voltage applications. Standard logic functions available in SO, TSSOP and DQFN packages with 14 contacts or more. We are always careful to match the needs of today’s Mini Logic functions in smaller footprint PicoGate and applications and systems, and that’s why our portfolio MicroPak packages with 10 contacts or less. focuses on reduced power consumption and smaller size. Logic portfolio by family, in high- and low-voltage categories High-voltage families I N C R E A S I N G Family Supply voltage (V) P E R F O R M A N C E HEF4000B HC(T) AHC(T) VHC(T) XC7 NPIC CBT(D) 3 to 15 2 to 6 2 to 5.5 2 to 5.5 2 to 5.5 2.3 to 5.5 4.5 to 5.5 Propagation delay, typ (ns) 60 9 5 5 5 5 0.25 Output drive (mA) ±3 ±8 ±8 ±8 ±8 100 Not applicable Standby current (µA) Temperature range (°C) AEC-Q100 option 600 80 40 40 40 200 3 -40 to +85 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +85 • • • • • • • • • • • • • • Process technology CMOS Functions Gates • • • • • MSI • • • • • Buffers • • Analog switches • • Bus interfaces/channels (bits) LED drivers • • 8 8 • • Bus switches • Level translators • Features Overvoltage-tolerant inputs up to 5 V Schmitt-trigger inputs • • Low-threshold inputs Open-drain outputs Input-clamping diodes TTL inputs Low delay isolation 12 NXP Logic selection guide 2016 • • • • • • • • • • • • • • • • • • • • • • Low-voltage families I N C R E A S I N G Family Supply voltage (V) LV LVC P E R F O R M A N C E ALVC LVT ALVT AVC(M) AUP AXP CBTLV(D) 1 to 3.6 1.2 to 3.6 1.2 to 3.6 2.7 to 3.6 2.3 to 3.6 1.2 to 3.6 0.8 to 3.6 0.7 to 2.75 2.3 to 3.6 9 2 2 2 1.5 2 4 3 0.15 Output drive (mA) ±8 ±24 ±24 -32/64 -32/64 ±8 ±4 ±8 Not applicable Standby current (µA) 20 20 40 120 90 20 0.9 0.6 10 -40 to +85 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 • • • • • • • • • • • Propagation delay, typ (ns) Temperature range (°C) AEC-Q100 option 1 2 -40 to +125 -40 to +125 • • • • • • Process technology CMOS • BiCMOS • • • Functions Gates • • MSI • • Buffers • • Configurable and combination logic Analog switches • • • • • • • • Bus interfaces/channels (bits) • 8/16/32 8/16/32 8/16/32 8/16 16/32 Bus switches • Level translators • • • • • Bus hold • • • • • Source termination • • • • • Live insertion3 • • • • • • Overvoltage-tolerant inputs to 5 V • • • • • • • • • • • Features Overvoltage-tolerant inputs to 3 V4 • Power-off leakage (IOFF) circuitry Schmitt-trigger inputs • • • Open-drain outputs • • Input-clamping diodes • Low-threshold inputs • • • • • • • • • Low delay isolation • Rail-to-rail switching • Some functions up to 5.5 V PicoGate functions (1G, 2G, and 3G) operate up to 5.5 V 3 Functions meet some or all the requirements for live insertion 4 AXP inputs tolerant to 2.75 V only 1 2 NXP Logic selection guide 2016 13 Logic portfolio by function Bus switches • • Decoders/demultiplexers • • Digital comparators • • Digital multiplexers • Encoders • FIFO registers • • Full adders Gates • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • AND gates • • • • • • • • • • • Combination gates • • EXCLUSIVE-NOR gates • • EXCLUSIVE-OR gates • • • NAND gates • • • NOR gates • • • • OR gates • • • • Latches/registered drivers • • • Level shifters/translators • • Multivibrators • • Parity generators/ checkers • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Phase-locked loops • • Schmitt triggers • • • • Shift registers/LED drivers • • • • • • • Transceivers • • • NXP Logic selection guide 2016 • • CBTLV(D) • • Configurable multi-function gates 14 AXP • • Counters/frequency dividers Flip-flops • AUP • AVC(M) • ALVT • • LVT • • ALVC • LVC Buffers/inverters/drivers LV • CBT(D) • Low-voltage families NPIC AHC(T) • XC7 HC(T) Analog switches Functions VHC(T) HEF4000B High-voltage families • • • • • • • • Special features NXP offers a variety of special features that improve performance, simplify design, lower cost, reduce the design footprint, and eliminate external components. This section highlights the features available across a number of families: Bus hold 16 Source termination Overvoltage-tolerant inputs Overvoltage-tolerant outputs Power-off leakage (IOFF) circuitry Schmitt-trigger inputs Live insertion Low-threshold inputs Open-drain outputs Input-clamping diodes Low delay isolation 17 18 19 19 20 21 22 23 23 24 The portfolio matrixes on page 14 show the features available in each family. NXP Logic selection guide 2016 15 BUS HOLD VCC Input pin OE1 A0 A1 A2 A3 A4 A5 A6 A7 GND Data signals VCC OE2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Using resistors to set default logic state Resistors that set the default logic state can be sized as follows: RPD < V TH/IBHHO RPU < (VCC - V TH)/ IBHLO The input switching threshold voltage (V TH) is approximately equal to (VIH + VIL)/2 Bus-hold cell CMOS input buffer The bus-hold feature The state of the bus-hold cell is indeterminate at powerup, so external resistors may be needed to set a default state at power-up, as shown here: Where you’ll find it The bus-hold feature is standard on all LVT and ALVT bus-interface products, including 8-, 16-, and 32-bit buffers, inverters, drivers, flip-flops, latches/registered drivers, level shifters/translators, and transceivers. On other families, the bus-hold feature is indicated by an “H” in the product number (e.g. 74LVCH245). Bus hold 16 Control signals 74LVCH541 Why it’s important CMOS inputs are high impedance. If they’re not defined, they can cause false switching and increase power consumption. The bus-hold feature defines the input by latching in the last logic level applied to the input. This eliminates the external components required to define the inputs, and that saves space, reduces the BOM, and reduces placement cost. VCC Controller What it does Defines inputs and ensures that oscillations and excessive current consumption, due to floating inputs, are avoided. Can eliminate external pull-up/pull-down resistors. NXP Logic selection guide 2016 3.3 V 2.5 V 1.8 V 1.2 V LVC, ALVC, LVT, ALVT, AVC(M) LVC, ALVC, ALVT, AVC(M) LVC, ALVC, AVC(M) AVC(M) SOURCE TERMINATION What it does Improves impedance matching in distributed systems and eliminates the need for external termination resistors. Rs VIN ZL Where you’ll find it Source-termination options are available in the lowvoltage BiCMOS families (LVT and ALVT) and the lowvoltage CMOS families [LVC, ALVC, AVC(M)]. Many of NXP’s 8-, 16-, and 32-bit products – including buffers, inverters, drivers, flip-flops, latches/registered drivers, and transceivers – have source-termination options. In transceivers, source termination is included on all I/O ports. VSIG Buffer driving a source-terminated distributed load A “2” is used to identify device types that include source termination (e.g. 74LVT2244 & 74LVC162244). 3.3 V 2.5 V 1.8 V 1.2 V LVC, ALVC, LVT, ALVT, AVC(M) LVC, ALVC, ALVT, AVC(M) LVC, ALVC, AVC(M) AVC(M) Source-termination resistor Why it’s important Source termination is commonly used to terminate distributed systems so as to avoid issues with signal integrity. The output resistance of the driver is matched to the characteristic impedance of the distributed system using an external resistor. Integrated source termination solves signal-integrity issues associated with distributed systems without the need of external components, and thus reduces BOM and cost. Sourcetermination resistors NXP Logic selection guide 2016 17 OVERVOLTAGE-TOLERANT INPUTS What they do Enable high-to-low voltage-level translation without external components. Why they’re important Devices with overvoltage-tolerant inputs do not have input clamp diodes on digital inputs, and can be used to interface to higher-voltage systems without using external current-limiting resistors. This reduces BOM and cost. Where you’ll find them The following families, in alphabetical order, have digital inputs that are overvoltage-tolerant and can be used to interface with subsystems operating at a higher supply voltage: AHC, ALVC, ALVT, AUP, AVC, AXP, CBTLV(D), LVC, and LVT. PicoGate devices in the LVC family can be used to interface subsystems with a power supply of 5.0 V to subsystems with a supply of as low as 1.8 V. The table shows the supply range of each family and the maximum input voltage that can be applied. Input voltage max (V) Supply voltage (V) AXP 2.75 0.7 to 2.75 AUP 3.6 0.8 to 3.6 AVC 3.6 1.2 to 3.6 AHC 5.5 2.0 to 5.5 CBTLV(D) 3.6 2.3 to 3.6 Family 18 NXP Logic selection guide 2016 Input voltage max (V) Supply voltage (V) LVC 5.5 1.65 to 3.6 LVC PicoGate devices 5.5 1.65 to 5.5 ALVC devices without bus hold 3.6 1.65 to 3.6 LVT 5.5 2.7 to 3.6 ALVT 5.5 2.3 to 3.6 Family CMOS input with no diode to VCC The overshoot clamp diode in a typical CMOS input is removed and there is no DC current path to VCC through the inputs. In an input cell with overvoltage protection, as VIN > VCC + Vt, no current flows to VCC in the input cell. This feature is available across all voltages. As mentioned above, the AVC and AUP families have a maximum VIN of 3.6 V. The LVC and ALVC families offer the feature on versions without bus hold. VCC ESD protection Input buffer Typical simplified CMOS input VCC ESD protection Input buffer Over-voltage-tolerant CMOS input Overvoltage protection provided by CMOS input with no diode to VCC OVERVOLTAGE-TOLERANT OUTPUTS 3-state CMOS output 3-stated outputs prevent a current path from the output to the supply voltage when a voltage higher than the supply voltage is applied to the output. In some applications, such as mixed-voltage multi-drop backplane applications, there is a risk of data contention and even damage due to clamping caused by 3-state outputs that are not overvoltage-tolerant. The AUP, AVC(M), AXP, and LVC logic families all have overvoltagetolerant 3-state CMOS outputs that switch the back gate of the PMOS output driver to VCC or the output voltage, whichever is higher. VCC 1 Bus 3-State 0 Simplified CMOS Input D G P N S+BG P Parasitic diode to VCC Overvoltage protection provided by 3-state CMOS output VCC 3-state BiCMOS output The LVT and ALVT families have overvoltage-tolerant 3-state BiCMOS outputs. A Schottky diode between VCC and the back gate prevents current flow to VCC. The BiCMOS outputs also include self-protection. The output is set to 3-state when VOUT > VCC + 0.5 V. Comparator VOUT OE IN CMOS portion of BICMOS output Overvoltage protection provided by 3-state CMOS output POWER-OFF LEAKAGE (IOFF) CIRCUITRY What it does Prevents potentially damaging leakage paths through the device when it’s powered down. Why it’s important Enables power-management strategies to use partial power-down of subsystems, saves energy in batterypowered applications, and prevents damage to devices in telecommunications-infrastructure applications. Where you’ll find it The following families, in alphabetical order, include power-off leakage (IOFF) circuitry: ALVC, ALVT, AVC(M), AUP, AXP, LVC, and LVT. 5V Poweroff leakage LVC (IOFF) circuitry 3.3 V 2.5 V 1.8 V 1.2 V LVC, LVC, LVC, ALVC, ALVC, ALVC, AVC(M), LVT, ALVT, AVC(M), AUP, ALVT, AVC(M), AUP, AXP AVC(M), AUP, AXP AUP AXP Bus VCC1 = 0 AUP1G08 0.8 V AXP VCC2 Ioff Ioff Ioff Device 1 VCC3 Device 2 Disabling power using the IOFF feature NXP Logic selection guide 2016 19 SCHMITT-TRIGGER INPUTS What it does Uses input hysteresis to prevent false switching and ensure well-defined outputs when driven by slowly transitioning signals. Where you’ll find it Schmitt-trigger inputs are standard on any of NXP’s 14, 17, 132, 4093, 40106, and configurable logic devices. 5V Why it’s important Enables asynchronous analog systems to interface with digital systems. High treshold level Low threshold level 3.3 V HC, AHC, HEF4000B, VHC, SchmittHC(T), XC7, trigger AHC(T), LV, LVC, inputs VHC(T), ALVC, XC7, LV, LVC LVT, ALVT, AUP 0.8 V HC, AHC, VHC, XC7, LVC, ALVC, ALVT LVC, ALVC, AUP, AXP AUP, AXP 1.8 V Symbol for a Schmitt-trigger input Upper threshold Input voltage NXP Logic selection guide 2016 1.2 V 0.8 V Output voltage Lower threshold 20 1.8 V Logic 1 Logic 0 Operation of Schmitt-trigger input 2.5 V AXP LIVE INSERTION What it does Enables the installation or removal of a board while the system is powered up. Low Bus System part powering up/down Active system part flow into the inputs and outputs of an unpowered device ensures that, when the device is inserted, the effective load seen on a powered data bus is minimal. Upon detection of the inserted board, the output enable input should be used to prevent data contention on the backplane. Devices that include power-up 3-state allow more time for the inserted board to be detected and the state of the output enable pin to be set. Live insertion with IOFF and 3-state outputs This feature, listed in datasheets as IPU/IPD or IOZPU/IOZPD, supports the same power-down mode as IOFF, but adds the ability to keep outputs 3-stated during power-up High Live insertion Why it’s important Live insertion, which is also known as hot swapping or hot plugging, involves inserting or extracting a board without switching off the power. That minimizes down time, and makes it easier to repair or upgrade a system. The goal is to maintain data integrity on the system bus while preventing damage to components on the host system or on the inserted/extracted card. Various degrees of bus isolation makes this possible. and power-down. This prevents outputs from turning on before reaching the VCC trip point, as shown in the figure. 3-state power-up mode also prevents the bus from loading at power-up. The 3-state power-up feature is available on NXP’s low-voltage LVT and ALVT families (the outputs 3-state below VCC = 1.2 V), and on the 5 V ABT family (the outputs 3-state below VCC = 2 V). OE follows VCC, ensuring device remains in 3-state (Z) during power-up/down Vcc 3.3 V Where you’ll find it Every NXP logic family supports some level of bus isolation, but live insertion is enabled by using one of three features: IOFF on its own, IOFF with 3-state outputs, or IOFF, 3-state outputs and the BIAS V pin. 1.2 V Output Off (Z) Live insertion with IOFF The IOFF feature, which is described later in this chapter, supports partial power-down mode. Preventing current 5V Live insertion with IOFF Live insertion with IOFF and 3-state outputs LVC Mini Logic On Off (Z) Power-up mode with 3-state outputs 3.3 V 2.5 V 1.8 V 1.2 V LVC, ALVC, LVC, ALVC, LVC, AVC(M), AVC(M), AUP, AVC(M), AUP, AVC(M), AUP, AUP AXP AXP AXP 0.8 V AXP LVT, ALVT NXP Logic selection guide 2016 21 LOW-THRESHOLD INPUTS What it does Support voltage-level translation. The circuitry is shown below: Why it’s important Being able to configure the system to translate voltages, according to the recommended guidelines for the input and output voltage levels of each component, makes the system more predictable, improves overall performance, and saves energy. Low-threshold inputs CMOS devices with input switching thresholds lower than the typical values can be used for low-to-high The combination of N1 sizing and drop across D1 determines the input threshold. Also, the P2 PMOS reduces the crossbar current through the inverter. HCT and AHCT products include TTL inputs, they operate at 5 V supply and can be used to interface to 3.3 V outputs. AUP1T devices operate in the 3.6 V range and can be used to interface with 1.8 V outputs. Low-threshold inputs voltage-level translation. 5V 3.3 V 2.5 V 1.8 V HCT AHCT VHCT XC7SET AUP AUP AUP VCC D2 100 Ω input P2 D3 170 Ω polysilicon resistor diffused diode resistor P1 P3 to logic circuit D1 N1 N3 GND Simplified CMOS input with lower-then-typical threshold values 22 NXP Logic selection guide 2016 OPEN-DRAIN OUTPUTS Open-drain outputs An open-drain output can be pulled up to a voltage level that matches the requirements of the device it’s driving. As shown in the figure, a pull-up resistor (RPU) is used between the output and the pull-up voltage (VPU). VPU can be set higher or lower than VCC, making open-drain outputs suitable for both low-to-high and high-to-low voltage-level translation. Where you’ll find it The AHCT and HCT families support legacy TTL levels. They operate at 5 V and can be used to interface with 3.3 V inputs. AUP1T devices operate at 3.3 V and can be used to interface with 1.8 V inputs. The LVT and ALVT families operate at 3.3 V and can be used to interface with 2.5 V inputs. Many of NXP’s buffer, inverter, and gate devices include open-drain outputs. VPU Level shifter with open-drain output 5V Pull-up resistor (RPU) Opendrain outputs 3.3 V HEF4000B, HC, NPIC, AHC, HC(T), LV, LVC, AHC(T), AUP LV, LVC 2.5 V 1.8 V 1.2 V 0.8 V LVC, AUP, AXP AUP, AXP AUP, AXP AXP Input GND Open-drain output and pull-up resistor for level translation INPUT-CLAMPING DIODES What they do Provide overvoltage and ESD protection, and enable high-to-low level translation. Why they’re important In families that have an input-clamping diode to VCC, the diode is a critical part of the input ESD-protection circuit. The clamping property of the diode can also be used with an external current-limiting resistor so the input can be interfaced to higher voltages. On some NXP logic devices, the inputs have input-clamping diodes to VCC and GND. When using CMOS devices that have current-limiting resistors at the inputs, the input voltage can exceed maximum specified values as long as the Inputclamping diodes 5V 3.3 V 2.5 V 1.8 V 1.2 V HEF4000B, HC(T), LV HC, LV HC, LV LV LV Clamping diode VCC2 = 5 V VCC1 = 15 V Device A RCL maximum current rating is observed. Where you’ll find them The HEF4000B, HC(T), NPIC, and LV families all utilize ESD-protection circuits that include input-clamping diodes to VCC. RCL = 15 V - (5.0 V + 0.7 V) IIK GND ESD protection Input buffer IIK is found in the limiting values table of the datasheet Input-clamping diodes support high-to-low level translation NXP Logic selection guide 2016 23 LOW DELAY ISOLATION What it does Enables the isolation of outputs on the same bus line without introducing significant delay. Why it’s important The propagation delay of 3-state buffers used for output isolation can seriously impact the timing margin, and this can be a critical issue in certain designs, including large synchronous backplane applications. VCC = 5 V Where you’ll find it NXP’s CBT(D) and CBTLV(D) families of bus switches provide isolation with a propagation delay of just 250 ps. Low delay isolation 5V 3.3 V CBT(D) CBTLV(D) 2.5 V CBTD3384 CBT3384 OE 3 V CPU 5 V CPU 3V 5V 3 V MEMORY 5 V I/O 3V CBT/CBTD3384 switch application 24 NXP Logic selection guide 2016 5V 1.8 V 1.2 V High-voltage families This section includes the following high-voltage logic families, in ascending order of performance HEF4000B logic HC(T) logic AHC(T) logic VHC(T) logic XC7 logic NPIC logic CBT(D) logic 25 28 38 42 43 44 45 HEF4000B LOGIC The HEF4000B series may be one of the oldest CMOS logic families around, but it’s still a popular choice due to its ease of design-in, wide operating supply range, excellent noise immunity, and low power consumption. HEF4000B logic devices are specified over 3 to 15 V and are optimized for 5, 10, and 15 V operation. Equipped with buffered outputs, HEF4000B devices exhibit lower static and dynamic noise than TTL devices. Buffered outputs also result in symmetrical output and improved transfer characteristics as loads increase. HEF4000B logic is pin-compatible with older CMOS4000 and 14500 devices. Due to the LOCMOS process flow, HEF4000B devices offer lower stray capacitances, smaller size, and higher packaging density. Other important features include built-in ESD protection, overvoltage-tolerant inputs, and higher guaranteed fan-out for TTL and LS devices. Standard HEF4000B devices are fully rated from -40 to +85 °C. Packages for extended temperature range (-55 to +125 °C) are available as HEC devices. Features and benefits 4Supply range from 3 to 15 V 4 Standard temperature range of -40 to +85 °C 4 Available extended temperature range (HEC) of -55 to +125 °C 4 8/12-bit shift registers can drive 20 mA loads (HEF4x94B) 4 Nearly all parts available in TSSOP and SO packages Applications 4 Medical equipment 4 General industrial applications 4 Consumer electronics 4 Toys and games 4 Glue-logic applications NXP Logic selection guide 2016 25 HEF4000B selection table (cont.) SO TSSOP SSOP Suffix T Suffix TT Suffix TS Type number Function Description HEF4000B NOR gates dual 3-input NOR gate • HEF4001B NOR gates quad 2-input NOR gate • HEF4002B NOR gates dual 4-input NOR gate • HEF4007UB Combination dual complementary pair and inverter • HEF40098B Buffers/inverters/drivers hex inverter • HEF40106BP Schmitt triggers hex inverter Schmitt trigger • HEF40106BTT Schmitt triggers hex inverter Schmitt trigger HEF4011B NAND gates quad 2-input NAND gate • HEF4011UB NAND gates quad 2-input NAND gate • HEF4013B D-type flip-flops dual D-tye flip-flop with set and reset; positive-edge trigger • HEF4014B Shift registers 8-bit shift register with synchronous parallel enable • HEF4015B Shift registers dual 4-bit serial-in/parallel-out shift register • HEF4016B Analog switches quad single-pole, single-throw analog switch • HEF40174B D-type flip-flops hex D-type flip-flop with reset; positive-edge trigger • HEF40175B D-type flip-flops quad D-type flip-flop with reset; positive-edge trigger • HEF4017B BCD/decade counters Johnson decade counter with 10 decoded outputs • HEF40193B Binary counters/timers presettable synchronous 4-bit binary up/down counter; separate up/ down clocks • HEF4020B Binary counters/timers 14-stage binary ripple counter • HEF4021B Shift registers 8-bit shift register with asynchronous parallel load • HEF4023B NAND gates triple 3-input NAND gate • HEF40240B Buffers/inverters/drivers octal inverter/line driver (3-state) • HEF40244B Buffers/inverters/drivers octal buffer/line driver (3-state) • HEF4024B Binary counters/timers 7-stage binary ripple counter • HEF4025B NOR gates triple 3-input NOR gate • HEF4027B J-K type flip-flops dual J-K flip-flop • HEF4028B Decoders/ demultiplexers 1-of-10 Decoder • HEF4030B EXCLUSIVE-OR gates quad 2-input EXCLUSIVE-OR gate • HEF40373B Latches/registered drivers octal D-type transparent latch (3-state) • HEF40374B D-type flip-flops octal D-type flip-flop; positive-edge trigger (3-state) • HEF4040B Binary counters/timers 12-stage binary ripple counter • quad R/S latch with set and reset (3-state) • quad R/S latch with set and reset (3-state) • HEF4043B HEF4044B Latches/registered drivers Latches/registered drivers • • • • HEF4046B Phase locked loops phase-locked-loop with VCO • HEF4047B Multivibrators monostable/astable multivibrator • HEF4049B Buffers/inverters/drivers hex inverter/line driver • HEF4050B Buffers/inverters/drivers hex buffer/line driver • HEF4051B Analog switches single-pole, octal-throw analog switch • • HEF4052B Analog switches dual single-pole, quad-throw analog switch • • 26 NXP Logic selection guide 2016 • HEF4000B selection table (cont.) SO TSSOP SSOP Suffix T Suffix TT Suffix TS • Type number Function Description HEF4053B Analog switches triple single-pole, double-throw analog switch • HEF4059B Divider counters programmable divide-by-n counter • HEF4060B Divider counters 14-stage binary ripple counter with oscillator • HEF4066B Analog switches quad single-pole, single-throw analog switch • HEF4067B Analog switches single-pole, 16-throw analog switch • HEF4068B NAND gates 8-input NAND gate • HEF4069UB Buffers/inverters/drivers hex inverter; unbuffered • HEF4070B EXCLUSIVE-OR gates quad 2-input EXCLUSIVE-OR gate • HEF4071B OR gates quad 2-input OR gate • HEF4072B OR gates dual 4-input OR gate • HEF4073B AND gates triple 3-input AND gate • HEF4075B OR gates triple 3-input OR gate • HEF4077B EXCLUSIVE-NOR gates quad 2-input EXCLUSIVE-NOR gate • HEF4081B AND gates quad 2-input AND gate • HEF4082B AND gates dual 4-input AND gate • HEF4093B Schmitt triggers quad 2-input NAND gate Schmitt trigger • Shift registers 8-bit serial-in/serial or parallel-out shift register with output register (3-state) • quad low-to-high voltage translator (3-state) • BCD to 7-segment latch/decoder/driver with lamp test input • 4-to-16 decoder/demultiplexer with address latches • HEF4094B HEF4104B HEF4511B HEF4514B Level shifters/ translators Decoders/ demultiplexers Decoders/ demultiplexers HEF4516B Binary counters/timers presettable synchronous 4-bit binary up/down counter • HEF4517B Shift registers dual 64-bit serial-in/parallel-out shift register • HEF4518B BCD/decade counters dual BCD counter • HEF4520B Binary counters/timers dual 4-bit synchronous binary counter • HEF4521B Binary counters/timers 24-stage frequency divider and oscillator • HEF4526B Binary counters/timers programmable 4-bit binary down counter • HEF4528B Multivibrators dual retriggerable monostable multivibrator with reset • HEF4538B Multivibrators dual retriggerable precision monostable multivibrator • HEF4541B Binary counters/timers programmable timer • BCD to 7-segment latch/decoder/driver with phase input • dual 1-to-4 line decoder/demultiplexer • HEF4543B HEF4555B Decoders/ demultiplexers Decoders/ demultiplexers HEF4557B Shift registers 1-to-64 bit shift register with variable length • HEF4585B Digital comparators 4-bit magnitude comparator • HEF4794B Shift registers HEF4894B Shift registers 8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) 12-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) • • • • NXP Logic selection guide 2016 27 HC(T) LOGIC HC(T) devices are high-speed CMOS logic available in the industry’s broadest range of functions. HC products are for use in CMOS applications from 2.0 to 6.0 V and HCT products are for use in TTL applications from 4.5 to 5.5 V. All HC(T) devices offer a balanced output drive of 8 mA and a typical propagation delay of 9 ns, and are fully specified from -40 to +125 °C. Features and benefits 4 9 ns typical propagation delay 4 Output drive capability IOH / IOL = ±8 mA 4 Low power 4 Input clamp diodes 4 Broad portfolio Applications 4 Industrial 4 Consumer electronics 4 Computer peripherals HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT Type number Function Description 74HC00 NAND gates quad 2-input NAND gate • • • • 74HCT00 NAND gates quad 2-input NAND gate; TTL-enabled • • • • 74HC02 NOR gates quad 2-input NOR gate • • • • 74HCT02 NOR gates quad 2-input NOR gate; TTL-enabled • • • • 74HC03 NAND gates quad 2-input NAND gate; open-drain • • • NAND gates quad 2-input NAND gate; open-drain; TTL-enabled • • • hex inverter • • • • hex inverter; TTL-enabled • • • • 74HCT03 74HC04 74HCT04 Buffers/inverters/ drivers Buffers/inverters/ drivers 74HC08 AND gates quad 2-input AND gate • • • • 74HCT08 AND gates quad 2-input AND gate; TTL-enabled • • • • 74HC10 NAND gates triple 3-input NAND gate • • • • • • • • • 74HCT10 NAND gates 74HC107 J-K type flip-flops 74HCT107 J-K type flip-flops 74HC109 J-K type flip-flops 74HCT109 J-K type flip-flops 74HC11 AND gates 74HCT11 AND gates 74HC112 J-K type flip-flops 74HCT112 J-K type flip-flops 74HC123 Multivibrators 74HCT123 Multivibrators 74HC125 Buffers/inverters/ drivers 28 triple 3-input NAND gate; TTL-enabled dual J-K flip-flop with reset; negativeedge trigger dual J-K flip-flop with reset; negativeedge trigger; TTL-enabled dual J-/K flip-flop with set and reset; positive-edge trigger dual J-/K flip-flop with set and reset; positive-edge trigger; TTL-enabled • • • • • • triple 3-input AND gate • • • triple 3-input AND gate; TTL-enabled • • • • • • • • • • • • • • • • • • • • • dual J-K flip-flop with set and reset; negative-edge trigger dual J-K flip-flop with set and reset; negative-edge trigger; TTL-enabled dual retriggerable monostable multivibrator with reset dual retriggerable monostable multivibrator with reset; TTL-enabled quad buffer/line driver (3-state) NXP Logic selection guide 2016 Suffix GW, GV HC(T) selection table (cont.) Type number 74HCT125 74HC126 74HCT126 DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT quad buffer/line driver (3-state); TTL-enabled • • • quad buffer/line driver (3-state) • • • • • • • • • • • • • • • • • • • • dual 2-to-4 line decoder/demultiplexer • • • • dual 2-to-4 line decoder/ demultiplexer; TTL-enabled • • • • Schmitt triggers 74HCT139 SO Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers 74HCT132 74HC139 SSOP Description Schmitt triggers 74HCT138 VSSOP Function 74HC132 74HC138 TSSOP Decoders/ demultiplexers Decoders/ demultiplexers Decoders/ demultiplexers Decoders/ demultiplexers quad buffer/line driver (3-state); TTL-enabled quad 2-input NAND gate Schmitt trigger quad 2-input NAND gate Schmitt trigger; TTL-enabled 3-to-8 line decoder/demultiplexer; inverting 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 74HC14 Schmitt triggers hex inverter Schmitt trigger • • • • 74HCT14 Schmitt triggers hex inverter Schmitt trigger; TTL-enabled • • • • 74HC147 Encoders 10-to-4 line priority encoder • • 74HCT147 Encoders 10-to-4 line priority encoder; TTL-enabled 74HC151 Digital multiplexers 8-input multiplexer • • • 74HCT151 Digital multiplexers 8-input multiplexer; TTL-enabled • • • 74HC153 Digital multiplexers dual 4-input multiplexer • • • 74HCT153 Digital multiplexers dual 4-input multiplexer; TTL-enabled • • • 4-to-16 line decoder/demultiplexer • • • • 4-to-16 line decoder/demultiplexer; TTL-enabled • • • • 74HC154 74HCT154 Decoders/ demultiplexers Decoders/ demultiplexers • 74HC157 Digital multiplexers quad 2-input multiplexer • • • • 74HCT157 Digital multiplexers quad 2-input multiplexer; TTL-enabled • • • • 74HC160 BCD/decade counters • • • 74HCT160 BCD/decade counters 74HC161 Binary counters/ timers 74HCT161 Binary counters/ timers 74HC163 Binary counters/ timers 74HCT163 Binary counters/ timers 74HC164 Shift registers 74HCT164 Shift registers 74HC165 Shift registers 74HCT165 Shift registers presettable synchronous BCD decade counter; asynchronous reset presettable synchronous BCD decade counter; asynchronous reset; TTL-enabled presettable synchronous 4-bit binary counter; asynchronous reset presettable synchronous 4-bit binary counter; asynchronous reset; TTL-enabled presettable synchronous 4-bit binary counter; synchronous reset presettable synchronous 4-bit binary counter; synchronous reset; TTL-enabled 8-bit serial-in/parallel-out shift register 8-bit serial-in/parallel-out shift register; TTL-enabled 8-bit parallel or serial-in/serial-out shift register 8-bit parallel or serial-in/serial-out shift register; TTL-enabled Suffix GW, GV • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • NXP Logic selection guide 2016 29 HC(T) selection table (cont.) Type number Function 74HC166 Shift registers 74HCT166 Shift registers 74HC173 D-type flip-flops 74HC174 D-type flip-flops 74HCT174 D-type flip-flops 74HC175 D-type flip-flops 74HCT175 D-type flip-flops 74HC191 74HCT191 74HC193 74HCT193 Binary counters/ timers Binary counters/ timers Binary counters/ timers Binary counters/ timers Description 8-bit parallel or serial-in/serial-out shift register 8-bit parallel or serial-in/serial-out shift register; TTL-enabled quad D-type flip-flop; positive-edge trigger (3-state) hex D-type flip-flop with reset; positive-edge trigger hex D-type flip-flop with reset; positive-edge trigger; TTL-enabled quad D-type flip-flop with reset; positive-edge trigger quad D-type flip-flop with reset; positive-edge trigger; TTL-enabled presettable synchronous 4-bit binary up/down counter presettable synchronous 4-bit binary up/down counter; TTL-enabled presettable synchronous 4-bit binary up/down counter presettable synchronous 4-bit binary up/down counter; TTL-enabled 4-bit bidirectional parallel or serial-in/ parallel-out shift register 4-bit bidirectional parallel or serial-in/ parallel-out shift register; TTL-enabled TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT • • • • • • • • • • • • • • • • • • • • • • • Suffix GW, GV • • • • • • • • • 74HC194 Shift registers 74HCT194 Shift registers 74HC1G00 NAND gates single 2-input NAND gate • 74HCT1G00 NAND gates single 2-input NAND gate; TTL-enabled • 74HC1G02 NOR gates single 2-input NOR gate • 74HCT1G02 NOR gates single 2-input NOR gate; TTL-enabled • single inverter • single inverter; TTL-enabled • single 2-input AND gate • single 2-input AND gate: TTL-enabled • single buffer/line driver (3-state) • single buffer/line driver; TTL-enabled (3-state) • single buffer/line driver (3-state) • single buffer/line driver; TTL-enabled (3-state) • 74HC1G04 74HCT1G04 74HC1G08 74HCT1G08 Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers AND gates Buffers/inverters/ 74HC1G125 drivers Buffers/inverters/ 74HCT1G125 drivers Buffers/inverters/ 74HC1G126 drivers Buffers/inverters/ 74HCT1G126 drivers • 74HC1G14 Schmitt triggers single inverter Schmitt trigger; • 74HCT1G14 Schmitt triggers single inverter Schmitt trigger; TTL-enabled • 74HC1G32 OR gates single 2-input OR gate • 74HCT1G32 OR gates single 2-input OR gate; TTL-enabled • 74HC1G66 Analog switches single-pole, single-throw analog switch • 74HCT1G66 Analog switches single-pole, single-throw analog switch; TTL-enabled • 74HC1G86 EXCLUSIVE-OR gates single 2-input EXCLUSIVE-OR gate • 30 NXP Logic selection guide 2016 HC(T) selection table (cont.) Type number Function Description 74HCT1G86 EXCLUSIVE-OR gates single 2-input EXCLUSIVE-OR gate; TTL-enabled 74HC20 NAND gates dual 4-input NAND gate 74HCT20 NAND gates dual 4-input NAND gate; TTL-enabled 74HC221 Multivibrators 74HCT221 Multivibrators 74HC238 74HCT238 74HC240 74HCT240 74HC241 74HCT241 74HC244 74HCT244 Decoders/ demultiplexers Decoders/ demultiplexers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT • • dual non-retriggerable monostable multivibrator with reset dual non-retriggerable monostable multivibrator with reset; TTL-enabled • • • • • • • • 3-to-8 decoder/demultiplexer • • • 3-to-8 decoder/demultiplexer; TTL-enabled • • • octal inverter/line driver (3-state) • • • octal inverter/line driver (3-state); TTL-enabled • • • octal buffer/line driver (3-state) • • • octal buffer/line driver; TTL-enabled (3-state) • • • octal buffer/line driver(3-state) • • • • octal buffer/line driver; TTL-enabled (3-state) • • • • 74HC245 Transceivers octal transceiver (3-state) • • • • 74HCT245 Transceivers octal transceiver (3-state); TTL-enabled • • • • 74HC251 Digital multiplexers 8-input multiplexer (3-State) • • • 74HCT251 Digital multiplexers 8-input multiplexer (3-State); TTL-enabled • • • 74HC253 Digital multiplexers dual 4-input multiplexer (3-State) • • 74HCT253 dual 4-input multiplexer (3-State); Digital multiplexers TTL-enabled • • 74HC257 Digital multiplexers quad 2-input multiplexer (3-State) • • • 74HCT257 Digital multiplexers quad 2-input multiplexer (3-State); TTL-enabled • • • 8 bit addressable latch • • • • 8 bit addressable latch; TTL-enabled • • • • 74HC259 74HCT259 Latches/registered drivers Latches/registered drivers 74HC27 NOR gates triple 3-input NOR gate • • • • 74HCT27 NOR gates triple 3-input NOR gate; TTL-enabled • • • • 74HC273 D-type flip-flops • • • • 74HCT273 D-type flip-flops • • • • Parity generators/ checkers Parity generators/ checkers octal D-type flip-flop with reset; positive-edge trigger octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled 9-bit odd/even parity generator/ checker 9-bit odd/even parity generator/ checker; TTL-enabled Shift registers 8-bit universal shift register (3-state) 74HCT299 Shift registers 8-bit universal shift register (3-state); TTL-enabled 74HC2G00 NAND gates dual 2-input NAND gate • • • 74HCT2G00 NAND gates dual 2-input NAND gate; TTL-enabled • • • 74HC280 74HCT280 74HC299 Suffix GW, GV • • • • • • • • • NXP Logic selection guide 2016 31 HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT Type number Function Description 74HC2G02 NOR gates dual 2-input NOR gate • • • 74HCT2G02 NOR gates dual 2-input NOR gate; TTL-enabled • • • 74HC2G04 74HCT2G04 Buffers/inverters/ drivers Buffers/inverters/ drivers dual inverter • dual inverter; TTL-enabled • 74HC2G08 AND gates dual 2-Input AND gate • • • 74HCT2G08 AND gates dual 2-Input AND gate; TTL-enabled • • • dual buffer/line driver (3-state) • • • dual buffer/line driver (3-state); TTL-enabled • • • dual buffer/line driver (3-state) • • • dual buffer/line driver (3-state); TTL-enabled • • • Buffers/inverters/ drivers Buffers/inverters/ 74HCT2G125 drivers Buffers/inverters/ 74HC2G126 drivers Buffers/inverters/ 74HCT2G126 drivers 74HC2G125 74HC2G14 Suffix GW, GV Schmitt triggers dual inverter Schmitt trigger • 74HCT2G14 Schmitt triggers dual inverter Schmitt trigger; TTL-enabled • 74HC2G17 Schmitt triggers dual buffer Schmitt trigger • 74HCT2G17 Schmitt triggers dual buffer Schmitt trigger; TTL-enabled • 74HC2G32 OR gates dual 2-input OR gate • • • 74HCT2G32 OR gates dual 2-input OR gate; TTL-enabled • • • 74HC2G34 74HCT2G34 Buffers/inverters/ drivers Buffers/inverters/ drivers 74HC2G66 Analog switches 74HCT2G66 Analog switches 74HC2G86 74HCT2G86 EXCLUSIVE-OR gates EXCLUSIVE-OR gates dual 2-input OR gate • dual buffer; TTL-enabled • dual single-pole, single-throw analog switch dual single-pole, single-throw analog switch; TTL-enabled dual 2-input EXCLUSIVE-OR gate • • • • • • • • • dual 2-input EXCLUSIVE-OR gate; TTL-enabled 74HC30 NAND gates 8-input NAND gate • • • 74HCT30 NAND gates 8-input NAND gate; TTL-enabled • • • 74HC32 OR gates quad 2-input OR gate • • • • 74HCT32 OR gates quad 2-input OR gate; TTL-enabled • • • • hex buffer/line driver (3-state) • • • • • • 74HC365 74HCT365 74HC366 74HCT366 74HC367 74HCT367 74HC368 32 Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers hex buffer/line driver (3-state); TTL-enabled hex buffer/line driver; Inverting (3-state) hex inverter/line driver (3-state); Inverting TTL-enabled hex inverter/line driver hex buffer/line driver (3-state); TTL-enabled hex buffer/line driver; Inverting (3-state) NXP Logic selection guide 2016 • • • • • • • • • • • • • HC(T) selection table (cont.) Type number 74HCT368 74HC373 74HCT373 74HC3G07 74HCT3G07 74HC3G14 74HCT3G14 74HC3G34 74HCT3G34 Suffix BQ Suffix GD, GM, GT • • • • • • • • • • • • • • • • • • • dual decade ripple counter • • • dual decade ripple counter; TTL-enabled • • • dual decade ripple counter • • • • dual 4-bit binary ripple counter; TTL-enabled • • • • triple inverter • • • triple inverter; TTL-enabled • • • triple inverter; open-drain • • • triple inverter; open-drain; TTL-enabled • • • triple buffer; open-drain • • • triple buffer; open-drain; TTL-enabled • • • Schmitt triggers triple inverter Schmitt trigger • • • Schmitt triggers triple inverter Schmitt trigger; TTL-enabled • • • triple buffer • • • triple buffer; TTL-enabled • • • • BCD/decade counters BCD/decade counters Binary counters/ timers Binary counters/ timers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers octal D-type transparent latch (3-state); TTL-enabled octal D-type flip-flop; positive-edge trigger (3-state) octal D-type flip-flop; positive-edge trigger (3-state); TTL-enabled octal D-type flip-flop with data enable; positive-edge trigger octal D-type flip-flop with data enable; positive-edge trigger; TTL-enabled NOR gates dual 4-input NOR gate 74HCT4002 NOR gates dual 4-input NOR gate; TTL-enabled 74HC40105 FIFO registers 4-bit x 16-word FIFO register 74HCT40105 FIFO registers 74HC4015 Shift registers 74HCT4015 Shift registers 74HC4016 Analog switches 74HCT4016 Analog switches 74HCT4017 Suffix D • 74HC4002 74HC4017 Suffix DB octal D-type transparent latch (3-state) D-type flip-flops 74HCT3G06 Suffix DC • 74HCT377 74HC3G06 Suffix DP, PW • D-type flip-flops 74HCT3G04 MicroPak PicoGate • 74HC377 74HC3G04 DQFN hex inverter/line driver; Inverting (3-state); TTL-enabled D-type flip-flops 74HCT393 SO Buffers/inverters/ drivers Latches/registered drivers Latches/registered drivers 74HCT374 74HC393 SSOP Description D-type flip-flops 74HCT390 VSSOP Function 74HC374 74HC390 TSSOP BCD/decade counters BCD/decade counters 4-bit x 16-word FIFO register; TTL-enabled dual 4-bit serial-in/parallel-out shift register dual 4-bit serial-in/parallel-out shift register; TTL-enabled quad single-pole, single-throw analog switch quad single-pole, single-throw analog switch; TTL-enabled Johnson decade counter with 10 decoded outputs Johnson decade counter with 10 decoded outputs; TTL-enabled • • • • • • • • • • • Suffix GW, GV • • • • • • • • • • NXP Logic selection guide 2016 33 HC(T) selection table (cont.) Type number Function 74HC4020 74HCT4020 74HC4040 74HCT4040 Binary counters/ timers Binary counters/ timers Binary counters/ timers Binary counters/ timers Description 74HCT4053 Analog switches 74HC4059 Divider counters 74HCT4059 74HC4060 74HCT4060 Divider counters Binary counters/ timers Binary counters/ timers Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT • • • 12-stage binary ripple counter • • • • 12-stage binary ripple counter; TTL-enabled • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • single-pole, octal-throw analog switch Analog switches Suffix DC • Analog switches 74HC4053 Suffix DP, PW 14-stage binary ripple counter; TTL-enabled 74HC4051 Analog switches MicroPak PicoGate • phase-locked-loop with VCO; TTL-enabled 74HCT4052 DQFN • Phase locked loops Analog switches SO • 74HCT4046A 74HC4052 SSOP • Phase locked loops phase-locked-loop with VCO Analog switches VSSOP 14-stage binary ripple counter 74HC4046A 74HCT4051 TSSOP single-pole, octal-throw analog switch; TTL-enabled dual single-pole, quad-throw analog switch dual single-pole, quad-throw analog switch; TTL-enabled triple single-pole, double-throw analog switch triple single-pole, double-throw analog switch; TTL-enabled programmable divide-by-n counter programmable divide-by-n counter; TTL-enabled 14-stage binary ripple counter with oscillator 14-stage binary ripple counter with oscillator; TTL-enabled quad single-pole, single-throw analog switch quad single-pole, single-throw analog switch; TTL-enabled • • • • • • • • • • • • • • • • 74HC4066 Analog switches 74HCT4066 Analog switches 74HC4067 Analog switches single-pole, 16-throw analog switch • • • • 74HCT4067 Analog switches single-pole, 16-throw analog switch; TTL-enabled • • • • 74HC4075 OR gates triple 3-input OR gate • • 74HCT4075 OR gates triple 3-input OR gate; TTL-enabled • • • 74HC4094 Shift registers • • • 74HCT4094 Shift registers • • 74HC42 74HCT42 Decoders/ demultiplexers Decoders/ demultiplexers 74HC423 Multivibrators 74HCT423 Multivibrators 74HC4316 Analog switches 74HCT4316 Analog switches 74HC4351 Analog switches 34 8-bit serial-in/serial or parallel-out shift register with output register (3-state) 8-bit serial-in/serial or parallel-out shift register with output register; TTL-enabled (3-state) BCD to decimal decoder (1-of-10) BCD to decimal decoder (1-of-10); TTL-enabled dual retriggerable monostable multivibrator with reset dual retriggerable monostable multivibrator with reset; TTL-enabled quad single-pole, single-throw analog switch with translation quad single-pole, single-throw analog switch with translation; TTL-enabled single-pole, octal-throw analog switch with latch NXP Logic selection guide 2016 • • • • • • • • • • • • • • • • Suffix GW, GV HC(T) selection table (cont.) Type number Function 74HCT4351 Analog switches 74HCT4353 Analog switches 74HC4511 Decoders/ demultiplexers 74HCT4511 Decoders/ demultiplexers 74HC4514 74HCT4514 74HC4515 74HCT4515 74HC4520 74HCT4520 Decoders/ demultiplexers Decoders/ demultiplexers Decoders/ demultiplexers Decoders/ demultiplexers Binary counters/ timers Binary counters/ timers 74HC4538 Multivibrators 74HCT4538 Multivibrators 74HC4851 Analog switches 74HCT4851 Analog switches 74HC4852 Analog switches 74HCT4852 Analog switches 74HC540 74HCT540 74HC541 74HCT541 74HC5555 74HCT5555 74HC563 74HCT563 74HC573 74HCT573 Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Binary counters/ timers Latches/registered drivers Latches/registered drivers Latches/registered drivers Latches/registered drivers 74HC574 D-type flip-flops 74HCT574 D-type flip-flops 74HC594 Shift registers Description single-pole, octal-throw analog switch with latch; TTL-enabled Triple 2-channel analog multiplexer/ demultiplexer with latch; TTL-enabled BCD to 7-segment latch/decoder/ driver with lamp test input BCD to 7-segment latch/decoder/ driver with lamp test input; TTL-enabled 4-to-16 decoder/demultiplexer with address latches 4-to-16 decoder/demultiplexer with address latches; TTL-enabled 4-to-16 decoder/demultiplexer with address latches; inverting 4-to-16 decoder/demultiplexer with address latches; inverting; TTL-enabled dual 4-bit synchronous binary counter dual 4-bit synchronous binary counter; TTL-enabled dual retriggerable precision monostable multivibrator dual retriggerable precision monostable multivibrator; TTL-enabled single-pole, octal-throw analog switch single-pole, octal-throw analog switch; TTL-enabled dual single-pole, quad-throw analog switch dual single-pole, quad-throw analog switch; TTL-enabled TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • octal inverter/line driver (3-state) • • octal inverter/line driver; TTL-enabled (3-state) • • • • • • • • octal buffer/line driver (3-state) octal buffer/line driver (3-state); TTL-enabled programmable delay timer with oscillator programmable delay timer with oscillator; TTL-enabled octal D-type transparent latch; inverting (3-state) octal D-type transparent latch; inverting (3-state); TTL-enabled octal D-type transparent latch; inverting (3-state) octal D-type transparent latch (3-state); TTL-enabled octal D-type flip-flop; positive-edge trigger (3-state) octal D-type flip-flop; positive-edge trigger (3-state); TTL-enabled 8-bit serial-in/parallel-out shift register with output storage register Suffix GW, GV • • • • • • • • • • • • • • • • • • • • • • NXP Logic selection guide 2016 35 HC(T) selection table (cont.) Type number Function 74HCT594 Shift registers 74HC595 Shift registers 74HCT595 Shift registers 74HC597 Shift registers 74HCT597 Shift registers Description TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT • • • • • • • • • • • • • • • • Binary counters/ timers Binary counters/ timers Binary counters/ timers 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register (3-state); TTL-enabled 8-bit parallel or serial-in/parallel-out shift register with parallel input storage register 8-bit parallel or serial-in/parallel-out shift register with parallel input storage register; TTL-enabled programmable ripple counter with oscillator (3-state) programmable ripple counter with oscillator (3-state) programmable ripple counter with oscillator (3-state); TTL-enabled 74HC652 Transceivers octal registered transceiver (3-state) • 74HCT652 Transceivers octal registered transceiver (3-state); TTL-enabled • 74HC6323A 74HC640 74HCT640 74HC670 74HCT670 74HC688 74HCT688 Latches/registered drivers Latches/registered drivers Digital comparators Digital comparators • • • • • • • • 4-bit x 4-word register (3-state) • • 4-bit x 4-word register (3-state); TTL-enabled • • 8-bit magnitude comparator • • • 8-bit magnitude comparator; TTL-enabled • • • 74HC7030 FIFO registers 9-bit x 64-word FIFO register (3-state) • 74HCT7030 FIFO registers 9-bit x 64-word FIFO register (3-state); TTL-enabled • 74HCT7046A Phase locked loops PLL with lock detector; TTL-enabled 74HC74 D-type flip-flops 74HCT74 D-type flip-flops 74HC7403 FIFO registers dual D-type flip-flop with set and reset; positive-edge trigger dual D-type flip-flop with set and reset; positive-edge trigger; TTL-enabled 4-bit x 16-word FIFO register (3-state); TTL-enabled octal inverter/line driver Schmitt trigger (3-State) octal inverter/line driver Schmitt trigger (3-State); TTL-enabled octal buffer/line driver Schmitt trigger (3-State) octal buffer/line driver Schmitt trigger (3-State); TTL-enabled FIFO registers 74HC7540 Schmitt triggers 74HCT7540 Schmitt triggers 74HC7541 Schmitt triggers 74HCT7541 Schmitt triggers 74HC7731 Shift registers quad 64-bit shift register 74HCT7731 Shift registers quad 64-bit shift register; TTL-enabled Digital comparators EXCLUSIVE-OR gates EXCLUSIVE-OR gates 4-bit magnitude comparator; TTL-enabled 74HC86 74HCT86 36 • • • • • • • • 4-bit x 16-word FIFO register (3-state) 74HCT7403 74HCT85 • • • • • • • • • • • • • • • • quad 2-input EXCLUSIVE-OR gate • • • quad 2-input EXCLUSIVE-OR gate; TTL-enabled • • • NXP Logic selection guide 2016 Suffix GW, GV HC(T) selection table (cont.) Type number Function 74HC9114 Schmitt triggers 74HCT9114 Schmitt triggers 74HC9115 Schmitt triggers 74HCT9115 Schmitt triggers 74HC93 74HCT93 74HC05 74HC137 Binary counters/ timers Binary counters/ timers Buffers/inverters/ drivers Decoders/ demultiplexers Description TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix DP, PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GM, GT 9-bit inverter Schmitt trigger; opendrain (3-state) 9-bit inverter Schmitt trigger; opendrain (3-state); TTL-enabled 9-bit buffer Schmitt trigger; open-drain (3-state) 9-bit buffer Schmitt trigger; open-drain (3-state); TTL-enabled • • • • 4-bit binary ripple counter • 4-bit binary ripple counter; TTL-enabled • • hex inverter; open-drain • 3-to-8 line decoder/demultiplexer with address latches; inverting • • • Digital multiplexers quad 2-input multiplexer; inverting 74HC1GU04 Buffers/inverters/ drivers single inverter; unbuffered 74HC21 AND gates dual 4-input AND gate • • • 74HC237 Decoders/ demultiplexers 3-to-8 decoder/demultiplexer with address latches • • • 74HC243 Transceivers quad transceiver (3-state) • • 74HC283 Full adders 4-bit binary full adder with fast carry • • 74HC2GU04 74HC3GU04 74HC40103 74HC4024 74HC4049 74HC4050 • • • Dual inverter; unbuffered • Triple inverter; unbuffered • • • 8-bit synchronous binary down counter • • • 7-stage binary ripple counter • • • hex inverter with 15V tolerant inputs • • • hex inverter with 15V tolerant inputs • • • • 74HC564 D-type flip-flops octal D-type flip-flop; inverting; positive-edge trigger (3-state) 74HC58 Combination dual AND-OR gate 74HC590 Binary counters/ timers 8-bit binary counter with output register (3-state) • • 74HC7014 Schmitt triggers hex buffer precision Schmitt trigger • • 74HC7266 EXCLUSIVE-NOR gates quad 2-input EXCLUSIVE-NOR gate 74HC73 J-K type flip-flops dual J-K flip-flop with reset; negativeedge trigger 74HC75 Latches/registered drivers Quad Bistable Transparent Latch 74HCT534N D-type flip-flops 74HCT7273 74HCT9046A 74HCU04 • • 74HC158 Buffers/inverters/ drivers Buffers/inverters/ drivers Binary counters/ timers Binary counters/ timers Level shifters/ translators Level shifters/ translators Suffix GW, GV octal D-type flip-flop; inverting; positive-edge trigger; TTL-enabled (3-state) octal D-type flip-flop; inverting; D-type flip-flops positive-edge trigger; TTL-enabled (3-state) PLL with bandgap controlled VCO; Phase locked loops TTL-enabled Buffers/inverters/ hex inverter; unbuffered drivers • • • • • • • • • • • • • • • • • • • • NXP Logic selection guide 2016 37 AHC(T) LOGIC AHC(T) devices are advanced high-speed CMOS logic. They are upgrades of the HC(T) family, with overvoltage-tolerant inputs for true mixed-voltage applications. AHC devices are for use in CMOS applications from 2.0 to 6.0 V and AHCT devices are for use in TTL applications from 4.5 to 5.5 V. All AHC(T) devices offer a balanced output drive of 8 mA and a typical propagation delay of 5 ns, and are fully specified from -40 to +125 °C. AHC(T) selection table (cont.) Features and benefits 4 Typical propagation delay of 5 ns 4 Output drive capability IOH / IOL = ±8 mA 4 Low power 4 5 V tolerant inputs 4 Low noise: VOLP = 0.8 V (max.) Applications 4 Industrial 4 Consumer electronics 4 Computer peripherals 4 Communications TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GF, GM, GN, GS, GT Type number Function Description 74AHC00 NAND gate Quad 2-input NAND gate • • • 74AHCT00 NAND gate Quad 2-input NAND gate; TTL-enabled • • • 74AHC02 NOR gate Quad 2-input NOR gate • • • 74AHCT02 NOR gate Quad 2-input NOR gate; TTL-enabled • • • 74AHC04 Buffer/inverter/ Hex inverter driver • • • 74AHCT04 Buffer/inverter/ Hex inverter; TTL-enabled driver • • • 74AHC08 AND gate Quad 2-input AND gate • • • 74AHCT08 AND gate Quad 2-input AND gate; TTL-enabled • • • 74AHC123A Multivibrator Dual retriggerable monostable multivibrator with reset • • • 74AHCT123A Multivibrator Dual retriggerable monostable multivibrator with reset; TTL-enabled • • • 74AHC125 Buffer/inverter/ Quad buffer/line driver (3-state) driver • • • 74AHCT125 Buffer/inverter/ Quad buffer/line driver; TTL-enabled driver (3-state) • • • 74AHC126 Buffer/inverter/ Quad buffer/line driver (3-state) driver • • • 74AHCT126 Buffer/inverter/ Quad buffer/line driver; TTL-enabled driver (3-state) • • • 74AHC132 Schmitt trigger Quad 2-input NAND gate Schmitt trigger • • • 74AHCT132 Schmitt trigger Quad 2-input NAND gate Schmitt trigger; TTL-enabled • • • 74AHC138 Decoder/ demultiplexer 3-to-8 line decoder/demultiplexer; inverting • • • 74AHCT138 Decoder/ demultiplexer 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled • • • 74AHC139 Decoder/ demultiplexer Dual 2-to-4 line decoder/ demultiplexer • • 74AHCT139 Decoder/ demultiplexer Dual 2-to-4 line decoder/ demultiplexer; TTL-enabled • • 74AHC14 Schmitt trigger Hex inverter Schmitt trigger • • 38 NXP Logic selection guide 2016 • Suffix DP, GW, GV AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GF, GM, GN, GS, GT Suffix DP, GW, GV Type number Function Description 74AHCT14 Schmitt trigger Hex inverter Schmitt trigger; TTL-enabled • • • 74AHC157 Digital multiplexer Quad 2-input multiplexer • • • 74AHCT157 Digital multiplexer Quad 2-input multiplexer; TTL-enabled • • • 74AHC164 Shift register 8-bit serial-in/parallel-out shift register • • • 74AHCT164 Shift register 8-bit serial-in/parallel-out shift register; TTL-enabled • • • 74AHC1G00 NAND gate Single 2-input NAND gate • 74AHCT1G00 NAND gate Single 2-input NAND gate; TTL-enabled • 74AHC1G02 NOR gate Single 2-input NOR gate • 74AHCT1G02 NOR gate Single 2-input NOR gate; TTL-enabled • 74AHC1G04 Buffer/inverter/ Single inverter driver • 74AHCT1G04 Buffer/inverter/ Single inverter; TTL-enabled driver • 74AHC1G06 Buffer/inverter/ Single inverter; open drain driver • 74AHCT1G06 Buffer/inverter/ Single inverter; open drain; driver TTL-enabled • 74AHC1G07 Buffer/inverter/ Single buffer; open drain driver • 74AHCT1G07 Buffer/inverter/ Single buffer; open drain; driver TTL-enabled • 74AHC1G08 AND gate Single 2-input AND gate • 74AHCT1G08 AND gate Single 2-input AND gate; TTL-enabled • 74AHC1G125 Buffer/inverter/ Single buffer/line driver (3-state) driver • 74AHCT1G125 Buffer/inverter/ Single buffer/line driver; TTL-enabled driver (3-state) • 74AHC1G126 Buffer/inverter/ Single buffer/line driver (3-state) driver • 74AHCT1G126 Buffer/inverter/ Single buffer/line driver; TTL-enabled driver (3-state) • 74AHC1G14 Schmitt trigger Single inverter Schmitt trigger • 74AHCT1G14 Schmitt trigger Single inverter Schmitt trigger; TTL-enabled • 74AHC1G17 Schmitt trigger Single buffer with Schmitt trigger • 74AHCT1G17 Schmitt trigger Single buffer with Schmitt trigger; TTL-enabled • 74AHC1G32 OR gate Single 2-input OR gate • 74AHCT1G32 OR gate Single 2-input OR gate • 74AHC1G66 Analog switch Single-pole, Single-throw analog switch • 74AHCT1G66 Analog switch Single-pole, Single-throw analog switch; TTL-enabled • 74AHC1G79 D-type flip-flop Single D-type flip-flop; positive-edge trigger • 74AHCT1G79 D-type flip-flop Single D-type flip-flop; positive-edge trigger; TTL-enabled • 74AHC1G86 EXCLUSIVEOR gate 2-input EXCLUSIVE-OR gate • NXP Logic selection guide 2016 39 AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GF, GM, GN, GS, GT Suffix DP, GW, GV Type number Function Description 74AHCT1G86 EXCLUSIVEOR gate 2-input EXCLUSIVE-OR gate TTL-enabled 74AHC240 Buffer/inverter/ Octal inverter/line driver (3-state) driver 74AHCT240 Buffer/inverter/ Octal inverter/line driver; TTLdriver enabled (3-state) • • • 74AHC244 Buffer/inverter/ Octal buffer/line driver (3-state) driver • • • 74AHCT244 Buffer/inverter/ Octal buffer/line driver; TTL-enabled driver (3-state) • • • 74AHC245 Transceiver Octal transceiver (3-state) • • • 74AHCT245 Transceiver Octal transceiver; TTL-enabled (3-state) • • • 74AHC257 Digital multiplexer Quad 2-input multiplexer (3-state) • • 74AHCT257 Digital multiplexer Quad 2-input multiplexer; TTL-enabled (3-state) • • 74AHC259 Latch/ registered driver 8 bit addressable latch • • 74AHCT259 Latch/ registered driver 8-Bit addressable latch; TTL-enabled • • 74AHC273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger • • • 74AHCT273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled • • • 74AHC2G00 NAND gate Dual 2-input NAND gate • • • 74AHCT2G00 NAND gate Dual 2-input NAND gate; TTL-enabled • • • 74AHC2G08 AND gate Dual 2-input AND gate • • • 74AHCT2G08 AND gate Dual 2-Input AND gate; TTL-enabled • • • 74AHC2G125 Buffer/inverter/ Dual buffer/line driver (3-state) driver • • • 74AHCT2G125 Buffer/inverter/ Dual buffer/line driver; TTL-enabled driver (3-state) • • • 74AHC2G126 Buffer/inverter/ Dual buffer/line driver (3-state) driver • • • 74AHCT2G126 Buffer/inverter/ Dual buffer/line driver; TTL-enabled driver (3-state) • • • 74AHC2G241 Buffer/inverter/ Dual buffer/line driver (3-state) driver • • • 74AHCT2G241 Buffer/inverter/ Dual buffer/line driver; TTL-enabled driver (3-state) • • • 74AHC2G32 OR gate Dual 2-input OR gate • • • 74AHCT2G32 OR gate Dual 2-input OR gate • • 74AHC30 NAND gate 8-input NAND gate • • • 74AHCT30 NAND gate 8-input NAND gate; TTL-enabled • • • 74AHC32 OR gate Quad 2-input OR gate • • • 74AHCT32 OR gate Quad 2-input OR gate; TTL-enabled • • • 74AHC373 Latch/ registered driver Octal D-type transparent latch (3-state) • • 74AHCT373 Latch/ registered driver Octal D-type transparent latch; TTL-enabled (3-state) • • 40 NXP Logic selection guide 2016 • • • AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Suffix PW Suffix DC Suffix DB Suffix D Suffix BQ Suffix GD, GF, GM, GN, GS, GT Suffix DP, GW, GV Type number Function Description 74AHC374 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • 74AHCT374 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • 74AHC377 D-type flip-flop Octal D-type flip-flop with data enable; positive-edge trigger • • 74AHCT377 Octal D-type flip-flop with data D-type flip-flop enable; positive-edge trigger; TTL-enabled • • 74AHC3G04 Buffer/inverter/ Triple inverter driver • • • 74AHCT3G04 Buffer/inverter/ Triple inverter; TTL-enabled driver • • • 74AHC3G14 Schmitt trigger Triple inverter Schmitt trigger • • • 74AHCT3G14 Triple inverter Schmitt trigger; Schmitt trigger TTL-enabled • • • 74AHC541 Buffer/inverter/ Octal buffer/line driver (3-state) driver • • • 74AHCT541 Buffer/inverter/ Octal buffer/line driver; TTL-enabled driver (3-state) • • • 74AHC573 Latch/ registered driver Octal D-type transparent latch (3-state) • • • 74AHCT573 Latch/ registered driver Octal D-type transparent latch; TTL-enabled (3-state) • • • 74AHC574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74AHCT574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) • • • 74AHC594 Shift register 8-bit serial-in/parallel-out shift register with output storage register • • • • 74AHCT594 Shift register 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled • • • • 74AHC595 Shift register 8-bit serial-in/parallel-out shift register with output storage register (3-state) • • • 74AHCT595 Shift register 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) • • • 74AHC74 D-type flip-flop Dual D-type flip-flop with set and reset; positive-edge trigger • • • 74AHCT74 Dual D-type flip-flop with set and D-type flip-flop reset; positive-edge trigger; TTL-enabled • • • 74AHC86 EXCLUSIVEOR gate Quad 2-input EXCLUSIVE-OR gate • • • 74AHCT86 EXCLUSIVEOR gate Quad 2-input EXCLUSIVE-OR gate; TTL-enabled • • • 74AHC1G09 AND gate Single 2-input AND gate; open drain 74AHC1GU04 Buffer/inverter/ Single inverter; unbuffered driver 74AHC3GU04 Buffer/inverter/ Triple inverter; unbuffered driver 74AHCU04 Buffer/inverter/ Hex inverter; unbuffered driver • • • • • • • • NXP Logic selection guide 2016 41 VHC(T) LOGIC VHC and VHCT devices are high-speed CMOS logic. They are upgrades of the HC(T) family, with overvoltage-tolerant inputs for true mixed-voltage applications. VHC products are for use in CMOS applications from 2.0 to 6.0 V. VHCT products are for use in TTL applications from 4.5 to 5.5 V. All VHC(T) devices offer balanced output drive of 8 mA and a typical propagation delay of 5 ns, and are fully specified from -40 to +125 °C. Features and benefits 4 Typical propagation delay of 5 ns 4 Balanced output drive IOH / IOL = ±8 mA 4 Low power 4 5 V tolerant inputs 4 Low noise: VOLP = 0.8 V (max.) Applications 4Industrial 4Consumer electronics 4Computer peripherals 4Communications 4Mixed-voltage applications VHC(T) selection table TSSOP SO QFN Suffix PW Suffix D Suffix BQ Type number Function Description 74VHC02 NOR gates quad 2-input NOR gate • • • 74VHCT02 NOR gates quad 2-input NOR gate; TTL-enabled • • • 74VHC08 AND gates quad 2-input AND gate • • • 74VHCT08 AND gates quad 2-input AND gate; TTL-enabled • • • 74VHC125 Buffers/inverters/drivers quad buffer/line driver (3-state) • • • 74VHCT125 Buffers/inverters/drivers quad buffer/line driver (3-state) • • • 74VHC126 Buffers/inverters/drivers quad buffer/line driver (3-state) • • • 74VHCT126 Buffers/inverters/drivers quad buffer/line driver (3-state); TTL-enabled • • • 74VHC14 Schmitt triggers hex inverter Schmitt trigger • • • 74VHCT14 Schmitt triggers hex inverter Schmitt trigger; TTL-enabled • • • 74VHC244 Buffers/inverters/drivers octal inverter/line driver (3-state) • • • 74VHCT244 Buffers/inverters/drivers octal inverter/line driver (3-state); TTL-enabled • • • 74VHC245 Transceivers octal transceiver (3-state) • • • 74VHCT245 Transceivers octal transceiver; TTL-enabled (3-state) • • • 74VHC32 OR gates quad 2-input OR gate • • • 74VHCT32 OR gates quad 2-input OR gate; TTL-enabled • • • 74VHC541 Buffers/inverters/drivers octal buffer/line driver (3-state) • • • 74VHCT541 Buffers/inverters/drivers octal buffer/line driver (3-state); TTL-enabled • • • 74VHC595 Shift registers 8-bit serial-in/parallel-out shift register with output storage register (3-state) • • • 74VHCT595 Shift registers 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) • • • 42 NXP Logic selection guide 2016 XC7 LOGIC XC7 devices are very high-speed CMOS logic. They are upgrades of the HC(T) family, with overvoltage-tolerant inputs for true mixed-voltage applications. XC7SH and XC7WH products are for use in CMOS applications that range from 2.0 to 6.0 V. XC7SET products are for use in TTL applications from 4.5 to 5.5 V. All XC7 devices offer a balanced output drive of 8 mA and a typical propagation delay of 5 ns, and are fully specified from -40 to +125 °C. Features and benefits 4 Typical propagation delay of 5 ns 4 Balanced output drive IOH / IOL = ±8 mA 4 Low power 4 5 V tolerant inputs 4 Low noise: VOLP = 0.8 V (max.) Applications 4 Industrial 4 Consumer electronics 4 Computer peripherals 4 Communications 4 Mixed-voltage applications XC7 selection table MicroPak PicoGate VSSOP Suffix GD, GM, GF, GT Suffix DP, GW, GV Suffix DC Type number Function Description XC7SET02 NOR gates single 2-input NOR gate; TTL-enabled • XC7SET04 Buffers/inverters/drivers single inverter; TTL-enabled • XC7SET08 AND gates single 2-input AND gate; TTL-enabled • XC7SET125 Buffers/inverters/drivers single buffer/line driver; TTL-enabled (3-state) XC7SET14 Schmitt triggers single inverter Schmitt trigger; TTL-enabled • XC7SET32 OR gates single 2-input OR gate; TTL-enabled • XC7SET86 EXCLUSIVE-OR gates 2-input EXCLUSIVE-OR gate; TTL-enabled • XC7SH02 NOR gates single 2-input NOR gate • XC7SH04 Buffers/inverters/drivers single inverter • XC7SH08 AND gates single 2-input AND gate • XC7SH125 Buffers/inverters/drivers single buffer/line driver (3-state) XC7SH14 Schmitt triggers single inverter Schmitt trigger • XC7SH32 OR gates single 2-input OR gate • XC7SH86 EXCLUSIVE-OR gates 2-input EXCLUSIVE-OR gate • XC7SHU04 Buffers/inverters/drivers single inverter; unbuffered • XC7WH126 Buffers/inverters/drivers dual buffer/line driver (3-state) • • XC7WH14 Schmitt triggers triple inverter Schmitt trigger • • • XC7WT14 Schmitt triggers triple inverter Schmitt trigger • • • • • • • NXP Logic selection guide 2016 43 NPIC LOGIC The NPIC family is a series of LED drivers based on shift registers. When used for I/O expansion, they enable the use of a low-cost controller with a low pincount. The serial output supports cascading, making it possible for three controller I/O to control the state of 16, 24, or more LEDs. They are fully specified from -40 to +125 °C. Features and benefits 4 33 V, 100 mA open-drain outputs 4 Simple 3.3 or 5 V control interface 4 I/O expansion 4 High frequency 4 Cascadable Applications 4 LED drivers 4Displays 4 Control units NPIC selection table TSSOP SO DQFN Suffix PW Suffix D Suffix BQ Type number Function Description NPIC6C4894 Shift register 12-bit serial-in/parallel-out shift register with output storage register (3-state) • • NPIC6C595 Shift register 8-bit serial-in/parallel-out shift register with output storage register (3-state) • • • NPIC6C596 Shift register/LED driver 8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) • • • NPIC6C596A Shift register/LED driver 8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) • • • 44 NXP Logic selection guide 2016 CBT(D) LOGIC CBT and CBTD bus switches are low-delay, single-transistor or transmission-gate solutions for multiplexing data buses, hotswapping boards in backplanes, memory interleaving, signal conditioning, or unidirectional level shifting. They are fully specified from either -40 to +85 °C or from -40 to +125 °C. Features and benefits 4 5 -to-3.3 V level shifting 4 3.3-to-1.8 V level shifting 4 Low propagation delay 4 T TL control inputs Applications 4 Telecommunications infrastructure 4 Memory interleaving 4 Industrial control 4 Unidirectional level shifting 4 Cell phones CBT(D) selection table TSSOP SSOP SO DQFN MicroPak Suffix DGG, PW Suffix DS, DK Suffix D Suffix BQ Suffix GF, GM, GN, GS Type number Function Description CBT16210 Bus switch 20-bit bus switch • • CBT16211 Bus switch 24-bit bus switch • • CBT16212 Bus switch 24-bit bus exchange switch • • CBT16292 Bus switch 12-bit 2:1 mux/demux • CBT3125 Bus switch Quad bus switch • • • CBT3126 Bus switch Quad bus switch • • • CBT3244A Bus switch Octal bus switch • • • • CBT3245A Bus switch Octal bus switch • • • • CBT3251 Bus switch 8:1 mux/demux • • • CBT3253A Bus switch Dual 4:1 mux/demux • • • CBT3257A Bus switch Quad 2:1 mux/demux • • • CBT3306 Bus switch Dual bus switch • CBT3384 Bus switch 10-bit bus switch • • CBT3861 Bus switch 10-bit bus switch • • CBTD16210 Bus switch 20-bit bus switch level translator • • CBTD3306 Bus switch Dual bus switch level translator • CBTD3384 Bus switch 10-bit bus switch level translator • • CBTD3861 Bus switch 10-bit bus switch level translator • • • • • • • • • • • NXP Logic selection guide 2016 45 Low-voltage families This section includes the following low-voltage logic families, in ascending order of performance LV logic LVC logic ALVC logic LVT logic ALVT logic AVC(M) logic AUP logic AXP logic CBTLV(D) logic 46 48 54 56 58 59 60 63 64 LV LOGIC The LV family provides the performance of 5 V HCMOS within the supply range of 3.0 to 3.6 V. The typical operating range is from 1.0 to 3.6 V, but many functions are specified from 1.0 to 5.5 V, with low ground bounce and high reliability. Offering fully compatible TTL input levels and balanced propagation delays for high speed, LV devices deliver higher output drive and higher speed than 5 V HCMOS devices. The family is pin-compatible with HC(T) devices and is fully specified from -40 to +125 °C. Features and benefits 4Wide operating voltage (1.0 to 5.5 V) 4 Optimized for low-voltage applications (1.0 to 3.6 V) 46 NXP Logic selection guide 2016 4 Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V 4 Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C 4 Typical high-level output voltage 4 ( VOH) undershoot: > 2 V at VCC= 3.3 V and Tamb = 25 °C Applications 4Industrial control (linear amplifiers, crystal oscillators, etc.) 4Battery back-up systems (chargers, UPS systems, etc.) 4Electronic data-processing peripherals 4Automotive electrical systems LV selection table TSSOP SSOP SO DQFN Suffix PW Suffix DB Suffix D Suffix BQ • • • • • • • Type number Function Description 74LV00 NAND gate Quad 2-input NAND gate 74LV02 NOR gate Quad 2-input NOR gate 74LV03 NAND gate Quad 2-input NAND gate; open drain 74LV04 Buffer/inverter/driver Hex inverter 74LV08 AND gate Quad 2-input AND gate • • • 74LV123 Multivibrator Dual retriggerable monostable multivibrator with reset • • • 74LV125 Buffer/inverter/driver Quad buffer/line driver (3-state) • • • 74LV132 Schmitt trigger Quad 2-input NAND gate Schmitt trigger • • • • 74LV138 Decoder/demultiplexer 3-to-8 line decoder/demultiplexer; inverting • • • • 74LV139 Decoder/demultiplexer Dual 2-to-4 line decoder/demultiplexer • • • • 74LV14 Schmitt trigger Hex inverter Schmitt trigger • • • • 74LV153 Digital multiplexer Dual 4-input multiplexer • • • 74LV164 Shift register 8-bit serial-in/parallel-out shift register • • • 74LV165 Shift register 8-bit parallel or serial-in/serial-out shift register • • • 74LV165A Shift register 8-bit parallel or serial-in/serial-out shift register • 74LV174 D-type flip-flop Hex D-type flip-flop with reset; positive-edge trigger • • • 74LV241 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74LV244 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74LV245 Transceiver Octal transceiver (3-state) • • • 74LV251 Digital multiplexer 8-input multiplexer (3-state) • • • 74LV259 Latch/registered driver 8 bit addressable latch • • • 74LV27 NOR gate Triple 3-input NOR gate 74LV273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger • • • 74LV32 OR gate Quad 2-input OR gate • • • 74LV365 Buffer/inverter/driver Hex buffer/line driver (3-state) • • • 74LV367 Buffer/inverter/driver Hex buffer/line driver (3-state) • • • 74LV373 Latch/registered driver Octal D-type transparent latch (3-state) • • • 74LV374 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74LV377 D-type flip-flop Octal D-type flip-flop with data enable; positive-edge trigger • • • 74LV393 Binary counter/timer Dual 4-bit binary ripple counter • • • 74LV4020 Binary counter/timer 14-stage binary ripple counter • • • 74LV4051 Analog switch Single-pole, octal-throw analog switch • • • 74LV4052 Analog switch Dual single-pole, quad-throw analog switch • • • 74LV4053 Analog switch Triple single-pole, double-throw analog switch • • • 74LV4060 Binary counter/timer 14-stage binary ripple counter with oscillator • • • 74LV4066 Analog switch Quad single-pole, single-throw analog switch • • • 74LV4094 Shift register 8-bit serial-in/serial or parallel-out shift register with output register (3-state) • • • 74LV541 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74LV573 Latch/registered driver Octal D-type transparent latch (3-state) • • • 74LV574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • • • • • • • 8-bit serial-in/parallel-out shift register with output storage register (3-state) Dual D-type flip-flop with set and reset; positive-edge trigger • • • • • • • • • • 74LV595 Shift register 74LV74 D-type flip-flop 74LV86 EXCLUSIVE-OR gate Quad 2-input EXCLUSIVE-OR gate • • • • 74LVU04 Buffer/inverter/driver Hex inverter; unbuffered • • • • NXP Logic selection guide 2016 47 LVC LOGIC LVC logic is specified over 1.65 to 3.6 V in standard formats, and from 1.65 to 5.5 V in PicoGate packages. With a balanced output drive of 24 mA and a typical propagation delay of 2 ns, and an extensive set of special features, the LVC family is well suited for parallel-interface applications. All LVC devices are fully specified from -40 to 125 °C. 4 Live insertion/extraction permitted 4 Buffers and drivers with 30 Ω integrated series termination (optional) 4 Bus hold on data inputs (optional) 4 Bus-interface functions in 16- and 32-bit versions Applications 4 STBs, DVD players, HDTVs 4 Workstations 4 Telecom and networking equipment 4 Advanced bus interfaces 4 Computer peripherals Features and benefits 4 Typical propagation delay of 2 ns 4 Output drive capability IOH / IOL = ±24 mA 4 Low power 4 5 V-tolerant I/O LVC selection table (cont.) TSSOP VSSOP SSOP SO Suffix DGG, PW Suffix DB, DL Suffix D Suffix DC Type number Function Description 74LVC162244A Buffer/inverter/ driver 16-bit buffer/line driver with 30 Ω termination resistors (3-state) • • 74LVCH162244A Buffer/inverter/ driver 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • 74LVC162245A Transceiver 16-bit transceiver with 30 Ω termination resistors (3-state) • • 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) • • 74LVCH162245A Transceiver DQFN BGA Suffix Suffix BQ, EC, EV BX 74LVC162373A Latch/registered driver 16-bit D-type transparent latch with 30 Ω termination resistors (3-state) • • 74LVCH162373A Latch/registered driver 16-bit D-type transparent latch with bus hold and 30 Ω termination resistors (3-state) • • 74LVC16244A Buffer/inverter/ driver 16-bit buffer/line driver (3-state) • • 74LVCH16244A Buffer/inverter/ driver 16-bit buffer/line driver with bus hold (3-state) • 74LVC16245A Transceiver 16-bit transceiver (3-state) • • • 74LVCH16245A Transceiver 16-bit transceiver with bus hold (3-state) • • • 74LVC16373A Latch/registered driver 16-bit D-type transparent latch (3-state) • • 74LVCH16373A Latch/registered driver 16-bit D-type transparent latch with bus hold (3-state) • • 74LVC16374A D-type flip-flop 16-bit D-type flip-flop; positive-edge trigger (3-state) • • • 74LVCH16374A D-type flip-flop 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • • • 74LVC1T45 Level shifter/ translator Single dual-supply voltagetranslating transceiver (3-state) 48 NXP Logic selection guide 2016 • MicroPak PicoGate Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV • • • • LVC selection table (cont.) TSSOP VSSOP SSOP Suffix DGG, PW Suffix DB, DL Suffix DC SO Suffix D DQFN BGA Suffix Suffix BQ, EC, EV BX MicroPak PicoGate Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV • • Type number Function Description 74LVCH1T45 Level shifter/ translator Single dual-supply voltagetranslating transceiver with bus hold (3-state) 74LVC244A Buffer/inverter/ driver Octal buffer/line driver (3-state) • • • • 74LVCH244A Buffer/inverter/ driver Octal buffer/line driver with bus hold (3-state) • • • • 74LVC245A Transceiver Octal transceiver (3-state) • • • • 74LVCH245A Transceiver Octal transceiver with bus hold (3-state) • • • • 74LVC2T45 Level shifter/ translator Dual-bit dual-supply voltagetranslating transceiver (3-state) • • 74LVCH2T45 Level shifter/ translator Dual-bit dual-supply voltagetranslating transceiver with bus hold (3-state) • • 74LVC8T245 Level shifter/ translator 8-bit dual-supply voltagetranslating transceiver (3-state) • 74LVC00A NAND gate Quad 2-input NAND gate • • • • 74LVC02A NOR gate Quad 2-input NOR gate • • • • 74LVC04A Buffer/inverter/ driver Hex inverter • • • • 74LVC06A Buffer/inverter/ driver Hex inverter; open drain • • • 74LVC07A Buffer/inverter/ driver Hex buffer; open drain • • • 74LVC08A AND gate Quad 2-input AND gate • • • • 74LVC109 JK-type flip-flop Dual J-/K flip-flop with set and reset; positive-edge trigger • • • 74LVC10A NAND gate Triple 3-input NAND gate • • • • 74LVC11 AND gate Triple 3-input AND gate • • • • 74LVC125A Buffer/inverter/ driver Quad buffer/line driver (3-state) • • • • 74LVC126A Buffer/inverter/ driver Quad buffer/line driver (3-state) • • • • 74LVC132A Schmitt trigger Quad 2-input NAND gate Schmitt trigger • • • 74LVC138A Decoder/ demultiplexer 3-to-8 line decoder/ demultiplexer; inverting • • • • 74LVC139 Decoder/ demultiplexer Dual 2-to-4 line decoder/ demultiplexer • • • • 74LVC14A Schmitt trigger Hex inverter Schmitt trigger • • • • 74LVC157A Digital multiplexer Quad 2-input multiplexer • • • • 74LVC161 Binary counter/ timer Presettable synchronous 4-bit binary counter; asynchronous reset • • • • 74LVC16240A Buffer/inverter/ driver 16-bit inverter/line driver (3-state) • • 74LVC16241A Buffer/inverter/ driver 16-bit buffer/line driver (3-state) • • 74LVC163 Binary counter/ timer Presettable synchronous 4-bit binary counter; synchronous reset • • • • • NXP Logic selection guide 2016 49 LVC selection table (cont.) TSSOP VSSOP SSOP Suffix DGG, PW Suffix DB, DL Suffix D • • Suffix DC SO DQFN BGA Suffix Suffix BQ, EC, EV BX MicroPak PicoGate Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV Type number Function Description 74LVC169 Binary counter/ timer Presettable synchronous 4-bit binary up/down counter 74LVC1G00 NAND gate Single 2-input NAND gate • • 74LVC1G02 NOR gate Single 2-input NOR gate • • 74LVC1G04 Buffer/inverter/ driver Single inverter • • 74LVC1G06 Buffer/inverter/ driver Single inverter; open drain • • 74LVC1G07 Buffer/inverter/ driver Single buffer; open drain • • 74LVC1G08 AND gate Single 2-input AND gate • • 74LVC1G10 NAND gate Single 3-input NAND gate • • 74LVC1G11 AND gate Single 3-input AND gate • • 74LVC1G123 Multivibrator Single retriggerable monostable multivibrator • • 74LVC1G126 Buffer/inverter/ driver Single buffer/line driver (3-state) • • 74LVC1G14 Schmitt trigger Single inverter Schmitt trigger • • 74LVC1G157 Digital multiplexer Single 2-input multiplexer • • 74LVC1G17 Schmitt trigger Single buffer Schmitt trigger • • 74LVC1G18 Decoder/ demultiplexer 1-to-2 demultiplexer (3-state) • • 74LVC1G19 Decoder/ demultiplexer 1-to-2 decoder/demultiplexer • • 74LVC1G27 NOR gate Single 3-input NOR gate • • 74LVC1G3157 Analog switch Single-pole, double-throw analog switch • • 74LVC1G32 OR gate Single 2-input OR gate • • 74LVC1G332 OR gate Single 3-input OR gate • • 74LVC1G34 Buffer/inverter/ driver Single buffer • • 74LVC1G38 NAND gate Single 2-input NAND gate; open drain • • 74LVC1G384 Analog switch Single-pole, Single-throw analog switch • • 74LVC1G386 EXCLUSIVE-OR gate Single 3-Input EXCLUSIVE-OR gate • • 74LVC1G53 Analog switch Single-pole, double-throw analog switch 74LVC1G57 Configurable multi-function gate Configurable gate; Schmitt trigger • • 74LVC1G58 Configurable multi-function gate Configurable gate; Schmitt trigger • • 74LVC1G66 Analog switch Single-pole, Single-throw analog switch • • • 74LVC1G74 D-type flip-flop Single D-type flip-flop with set and reset; positive-edge trigger • • • 74LVC1G79 D-type flip-flop Single D-type flip-flop; positive-edge trigger • • • 50 NXP Logic selection guide 2016 • • • • • • LVC selection table (cont.) TSSOP VSSOP SSOP Suffix DGG, PW Suffix DB, DL Suffix DC SO Suffix D DQFN BGA Suffix Suffix BQ, EC, EV BX MicroPak PicoGate Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV Type number Function Description 74LVC1G80 D-type flip-flop Single D-type flip-flop; positive-edge trigger • • • 74LVC1G86 EXCLUSIVE-OR gate Single 2-input EXCLUSIVE-OR gate • • • 74LVC1G97 Configurable multi-function gate Configurable gate; Schmitt trigger • • • 74LVC1G98 Configurable multi-function gate Configurable gate; Schmitt trigger • • • 74LVC1G99 Configurable multi-function gate Configurable gate; Schmitt trigger • • • 74LVC1GU04 Buffer/inverter/ driver Single inverter; unbuffered • • • 74LVC2244A Buffer/inverter/ driver Octal buffer/line driver with 30 Ω termination resistors (3-state) • • • • 74LVC2245A Transceiver Octal transceiver with 30 Ω termination resistors (3-state) • • • • 74LVC240A Buffer/inverter/ driver Octal inverter/line driver (3-state) • • • • 74LVC241A Buffer/inverter/ driver Octal buffer/line driver (3-state) • • • • 74LVC257A Digital multiplexer Quad 2-input multiplexer (3-state) • • • • 74LVC27 NOR gate Triple 3-input NOR gate • • • • 74LVC273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger • • • • 74LVC2952A Transceiver Octal registered transceiver with 30 Ω termination resistors (3-state) • • • • 74LVC2G00 NAND gate Dual 2-input NAND gate • • • • 74LVC2G02 NOR gate Dual 2-input NOR gate • • • • 74LVC2G04 Buffer/inverter/ driver Dual inverter • • • • 74LVC2G06 Buffer/inverter/ driver Dual inverter; open drain • • • • 74LVC2G07 Buffer/inverter/ driver Dual buffer; open drain • • • • 74LVC2G08 AND gate Dual 2-input AND gate • • • • 74LVC2G125 Buffer/inverter/ driver Dual buffer/line driver; TTL-enabled (3-state) • • • • 74LVC2G126 Buffer/inverter/ driver Dual buffer/line driver; TTL-enabled (3-state) • • • • 74LVC2G14 Schmitt trigger Dual inverter Schmitt trigger • • • 74LVC2G17 Schmitt trigger Dual buffer Schmitt trigger • • • 74LVC2G240 Buffer/inverter/ driver Dual inverter/line driver (3-state) • • • • 74LVC2G241 Buffer/inverter/ driver Dual buffer/line driver (3-state) • • • • 74LVC2G32 OR gate Dual 2-input OR gate • • • • 74LVC2G34 Buffer/inverter/ driver Dual buffer • • • • NXP Logic selection guide 2016 51 LVC selection table (cont.) TSSOP VSSOP SSOP Suffix DGG, PW Suffix DC Suffix DB, DL SO Suffix D DQFN BGA Suffix Suffix BQ, EC, EV BX MicroPak PicoGate Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV Type number Function Description 74LVC2G38 NAND gate Dual 2-input NAND gate; open drain • • • • 74LVC2G53 Analog switch Single-pole, double-throw analog switch • • • • 74LVC2G66 Analog switch Dual single-pole, single-throw analog switch • • • • 74LVC2G74 D-type flip-flop Single D-type flip-flop with set and reset; positive-edge trigger • • • • 74LVC2G86 EXCLUSIVE-OR gate Dual 2-input EXCLUSIVE-OR gate • • • • 74LVC2GU04 Buffer/inverter/ driver Dual inverter; unbuffered • • • • 74LVC32245A Transceiver 32-bit transceiver (3-state) 74LVC32A OR gate Quad 2-input OR gate • • • • 74LVC373A Latch/registered driver Octal D-type transparent latch (3-state) • • • • 74LVC374A D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • • 74LVC377 D-type flip-flop Octal D-type flip-flop with data enable; positive-edge trigger • • • 74LVC38A NAND gate Quad 2-input NAND gate; open drain • • • 74LVC3G04 Buffer/inverter/ driver Triple inverter • • • 74LVC3G06 Buffer/inverter/ driver Triple inverter; open drain • • • 74LVC3G07 Buffer/inverter/ driver Triple buffer; open drain • • • 74LVC3G14 Schmitt trigger Triple inverter Schmitt trigger • • • 74LVC3G17 Schmitt trigger Triple buffer Schmitt trigger • • • 74LVC3G34 Buffer/inverter/ driver Triple buffer • • • 74LVC3GU04 Buffer/inverter/ driver Triple inverter; unbuffered • • • 74LVC4066 Analog switch Quad single-pole, singlethrow analog switch • • • 74LVC4245A Level shifter/ translator 8-bit dual-supply voltagetranslating transceiver (3-state) • • • 74LVC541A Buffer/inverter/ driver Octal buffer/line driver (3-state) • • • • 74LVC543A Transceiver Octal registered transceiver (3-state) • • • • 74LVC544A Transceiver Octal registered transceiver; inverting (3-state) • • • 74LVC573A Latch/registered driver Octal D-type transparent latch (3-state) • • • 74LVC574A D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74LVC594A Shift register 8-bit serial-in/parallel-out shift register with output storage register • • • 52 NXP Logic selection guide 2016 • • • LVC selection table (cont.) TSSOP VSSOP SSOP Suffix DGG, PW Suffix DB, DL Suffix DC SO Suffix D DQFN BGA Suffix Suffix BQ, EC, EV BX Type number Function Description 74LVC595A Shift register 8-bit serial-in/parallel-out shift register with output storage register (3-state) • • • 74LVC623A Transceiver Octal transceiver with dual enable (3-state) • • • 74LVC646A Transceiver Octal registered transceiver (3-state) • • 74LVC74A D-type flip-flop Dual D-type flip-flop with set and reset; positive-edge trigger • • • • 74LVC821A D-type flip-flop 10-bit D-type flip-flop; positive-edge trigger (3-state) • • • • 74LVC827A Buffer/inverter/ driver 10-bit buffer/line driver (3-state) • • • • 74LVC841A Latch/registered driver 10-bit D-type transparent latch (3-state) • • • • 74LVC86A EXCLUSIVE-OR gate Quad 2-input EXCLUSIVE-OR gate • • • • 74LVCH162374A D-type flip-flop 16-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positiveedge trigger (3-state) • • • • 74LVCH16541A Buffer/inverter/ driver 16-bit buffer/line driver with bus hold (3-state) 74LVCH322244A Buffer/inverter/ driver 32-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • 32-bit transceiver with bus hold and 30 Ω termination resistors (3-state) • 74LVCH322245A Transceiver 74LVCH32244A Buffer/inverter/ driver 32-bit buffer/line driver with bus hold (3-state) • 74LVCH32245A Transceiver 32-bit transceiver with bus hold (3-state) • 74LVCH32373A Latch/registered driver 32-bit D-type transparent latch (3-state) • 74LVCH32374A D-type flip-flop 32-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • 74LVCU04A Buffer/inverter/ driver Hex inverter; unbuffered 74LVCV2G66 Analog switch Dual single-pole, single-throw analog switch; overvoltage tolerant • MicroPak PicoGate Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV • • • NXP Logic selection guide 2016 53 ALVC LOGIC ALVC logic devices are specified over a voltage range of 1.65 to 3.6 V. They have a balanced output drive of 24 mA and a typical propagation delay of 2 ns, and are well suited for parallel-interface applications. ALVC products are fully specified from -40 to 85 °C. Features and benefits Typical propagation delay of 2 ns Output drive capability IOH / IOL = ±24 mA Low power 3.6 V-tolerant I/O Live insertion/extraction permitted uffers and drivers with 30 Ω integrated series termination B (optional) Bus hold on data inputs (optional) Bus-interface functions in 16- and 32-bit versions Applications STBs, DVD players, HDTVs Workstations Telecom and networking equipment Advanced bus interfaces Computer peripherals ALVC selection table (cont.) TSSOP SSOP QFN BGA Suffix DGG, PW Suffix D, DL Suffix BQ, BX Suffix EC Type number Function Description 74ALVC16244 Buffer/inverter/driver 16-bit buffer/line driver (3-state) • • 74ALVCH16244 Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • • 74ALVC16245 Transceiver 16-bit transceiver (3-state) • • 74ALVCH16245 Transceiver 16-bit transceiver with bus hold (3-state) • • 74ALVC00 NAND gate Quad 2-input NAND gate • • • 74ALVC02 NOR gate Quad 2-input NOR gate • • • 74ALVC04 Buffer/inverter/driver Hex inverter • • • 74ALVC08 AND gate Quad 2-input AND gate • • • 74ALVC125 Buffer/inverter/driver Quad buffer/line driver (3-state) • • • 74ALVC14 Schmitt trigger Hex inverter Schmitt trigger • • • 74ALVC162334A Latch/registered driver 16-bit registered driver with 30 Ω termination resistors (3-state) • • • 74ALVC162834A Latch/registered driver 18-bit registered driver with 30 Ω termination resistors (3-state) • • • 74ALVC164245 Level shifter/translator 16-bit dual-supply voltage-translating transceiver (3-state) • • • 74ALVC16834A Latch/registered driver 18-bit registered driver (3-state) • • • 74ALVC16835A Latch/registered driver 18-bit registered driver (3-state) • • • 74ALVC16836A Latch/registered driver 20-bit registered driver (3-state) • • • 74ALVC244 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74ALVC245 Transceiver Octal transceiver (3-state) • • • 74ALVC32 OR gate Quad 2-input OR gate • • • 54 NXP Logic selection guide 2016 ALVC selection table (cont.) TSSOP SSOP QFN BGA Suffix DGG, PW Suffix D, DL Suffix BQ, BX Suffix EC Type number Function Description 74ALVC373 Latch/registered driver Octal D-type transparent latch (3-state) • • • 74ALVC541 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74ALVC573 Latch/registered driver Octal D-type transparent latch (3-state) • • • 74ALVC574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74ALVC74 D-type flip-flop Dual D-type flip-flop with set and reset; positive-edge trigger • • • 74ALVCH162245 Transceiver 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) • • 74ALVCH162601 Transceiver 18-bit universal bus transceiver with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) • 74ALVCH162827 Buffer/inverter/driver 20-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • 74ALVCH16373 Latch/registered driver 16-bit D-type transparent latch with bus hold (3-state) • • 74ALVCH16374 D-type flip-flop 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • • 74ALVCH16500 Transceiver 18-bit universal bus transceiver with bus hold; negative edge trigger (3-state) • 74ALVCH16501 Transceiver 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) • 74ALVCH16543 Transceiver 16-bit registered transceiver with bus hold (3-state) • 74ALVCH16600 Transceiver 18-bit universal bus transceiver with bus hold; negative edge trigger (3-state) • 74ALVCH16601 Transceiver 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) • 74ALVCH16646 Transceiver 16-bit registered transceiver with bus hold (3-state) • 74ALVCH16652 Transceiver 16-bit registered transceiver with bus hold (3-state) • 74ALVCH16821 D-type flip-flop 20-bit D-type flip-flop; positive-edge trigger (3-state) • • 74ALVCH16823 D-type flip-flop 18-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • • 74ALVCH16825 Buffer/inverter/driver 18-bit buffer/line driver with bus hold (3-state) • 74ALVCH16827 Buffer/inverter/driver 20-bit buffer/line driver with bus hold (3-state) • 74ALVCH16832 Latch/registered driver 7-bit to 28-bit address register/driver (3-state) • 74ALVCH16841 Latch/registered driver 20-bit D-type transparent latch with bus hold (3-state) • 74ALVCH16843 Latch/registered driver 18-bit D-type transparent latch with bus hold (3-state) • 74ALVCH16952 Transceiver 16-bit registered transceiver with bus hold (3-state) • 74ALVCH32973 Latch/registered driver 16-bit transceiver and transparent D-type latch with 8 independent buffers • • NXP Logic selection guide 2016 • 55 LVT LOGIC The LVT family combines the low power dissipation and low noise of CMOS with the high speed and high output drive of bipolar products. LVT devices exhibit highly stable static and dynamic characteristics over a wide temperature range, are specified over 2.7 to 3.6 V, and support live insertion. With output drive as high as 64 mA and typical propagation delay of 2 ns, these devices are well suited for parallel-backplane applications. They are fully specified from -40 °C to 85 °C. Features and benefits 4 Typical propagation delay of 2 ns 4 Output drive capability IOH / IOL = -32/+64 mA 4 Supply voltage range VCC = 2.7 to 3.6 V 4 5 V-tolerant I/O 4 Bus hold on data inputs 4 Power-up/power-down 3-state 4 Live insertion 4 Buffers and drivers with 30 Ω integrated series termination (optional) Applications 4 Backplane drivers 4 Workstations 4 Telecom and networking equipment 4 Advanced bus interfaces 4 Computer peripherals LVT selection table (cont.) TSSOP SSOP Suffix DGG, PW SO Suffix Suffix DB, DL D QFN BGA Suffix BQ, BX Suffix EC, EV Type number Function Description 74LVT125 Buffer/inverter/driver Quad buffer/line driver with bus hold (3-state) • • • • 74LVTH125 Buffer/inverter/driver Quad buffer/line driver with bus hold (3-state) • • • • 74LVT16244B Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • • • 74LVTH16244B Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • • • 74LVT16245B Transceiver 16-bit transceiver with bus hold (3-state) • • • 74LVTH16245B Transceiver 16-bit transceiver with bus hold (3-state) • • • 74LVT16374A D-type flip-flop 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • • • 74LVTH16374A D-type flip-flop 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) 74LVT2245 Transceiver Octal transceiver with bus hold and 30 Ω termination resistors (3-state) • • • 74LVTH2245 Transceiver Octal transceiver with bus hold and 30 Ω termination resistors (3-state) • • • 74LVT244A Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • • 74LVTH244A Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • 74LVT244B Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • • 74LVTH244B Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • • 74LVT574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74LVTH574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74LVT00 NAND gate Quad 2-input NAND gate • • • 74LVT02 NOR gate Quad 2-input NOR gate • • • 74LVT04 Buffer/inverter/driver Hex inverter • • • 74LVT08 AND gate Quad 2-input AND gate • • • 74LVT10 NAND gate Triple 3-input NAND gate • • • 74LVT126 Buffer/inverter/driver Quad buffer/line driver with bus hold (3-state) • • • • 74LVT14 Schmitt trigger Hex inverter Schmitt trigger • • • • Buffer/inverter/driver 16-bit inverter/line driver with bus hold and 30 Ω termination (3-state) • • 74LVT162240A 56 NXP Logic selection guide 2016 • • • • • LVT selection table (cont.) TSSOP SSOP Suffix DGG, PW SO Suffix Suffix DB, DL D QFN BGA Suffix BQ, BX Suffix EC, EV Type number Function Description 74LVT162244B Buffer/inverter/driver 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • 74LVT162245B Transceiver 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) • • 74LVT162373 Latch/registered driver 16-bit D-type transparent latch with bus hold and 30 Ω termination resistors (3-state) • • 74LVT162374 D-type flip-flop 16-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) • • 74LVT16240A Buffer/inverter/driver 16-bit inverter/line driver with bus hold (3-state) • • 74LVT16373A Latch/registered driver 16-bit D-type transparent latch with bus hold (3-state) • • 74LVT16500A Transceiver 18-bit universal bus transceiver with bus hold; negativeedge trigger (3-state) • • 74LVT16501A Transceiver 18-bit universal bus transceiver with bus hold; positiveedge trigger (3-state) • • 74LVT16543A Transceiver 16-bit registered transceiver with bus hold (3-state) • • 74LVT16646A Transceiver 16-bit registered transceiver with bus hold (3-state) • • 74LVT16652A Transceiver 16-bit registered transceiver with bus hold (3-state) • • • 74LVT2241 Buffer/inverter/driver Octal buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • • 74LVT2244 Buffer/inverter/driver Octal buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • • 74LVT240 Buffer/inverter/driver Octal inverter/line driver with bus hold (3-state) • • • 74LVT241 Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • • • 74LVT245B Transceiver Octal transceiver (3-state) • • • • 74LVT245 Transceiver Octal transceiver (3-state) • • • • 74LVT273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger • • • • 74LVT2952 Transceiver Octal registered transceiver with 30 Ω termination resistors (3-state) • • • 74LVT32 OR gate Quad 2-input OR gate • • • 74LVT32374 D-type flip-flop 32-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) 74LVT373 D-type flip-flop Octal D-type transparent latch (3-state) • 74LVT374 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74LVT534 D-type flip-flop Octal D-type flip-flop; inverting; positive-edge trigger (3-state) • • • 74LVT543 Transceiver Octal registered transceiver (3-state) • • • 74LVT573 Latch/registered driver Octal D-type transparent latch (3-state) • • • 74LVT640 Transceiver Octal transceiver with bus hold; inverting (3-state) • • • 74LVT646 Transceiver Octal registered transceiver with bus hold (3-state) • • • 74LVT652 Transceiver Octal registered transceiver with bus hold (3-state) • • • 74LVT74 D-type flip-flop Dual D-type flip-flop with set and reset; positive-edge trigger • • • 74LVTH322245 Transceiver 32-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 74LVTH32245 Transceiver 32-bit transceiver with bus hold (3-state) 74LVTN16244B Buffer/inverter/driver 16-bit buffer/line driver (3-state) • • 74LVTN16245B Transceiver 16-bit transceiver (3-state) • • • • • • • NXP Logic selection guide 2016 57 ALVT LOGIC The ALVT family is a speed upgrade for the LVT family. It combines the low power dissipation and low noise of CMOS with the high speed and high output drive of bipolar products. ALVT devices exhibit highly stable static and dynamic characteristics over a wide temperature range, are specified over 2.7 to 3.6 V, and support live insertion. With output drive as high as 64 mA and typical propagation delay of 2 ns, these devices are well suited for parallel-backplane applications. They are fully specified from -40 °C to 85 °C. Features and benefits 4 Typical propagation delay of 1.5 ns 4 Output drive capability IOH / IOL = -32/+64 mA 4 Supply voltage range VCC = 2.7 to 3.6 V 4 5 V-tolerant I/O 4 Bus hold on data inputs 4 Power-up/power-down 3-state 4 Live insertion 4 Buffers and drivers with 30 Ω integrated series termination (optional) Applications 4Backplane drivers 4Workstations 4Telecom and networking equipment 4Advanced bus interfaces 4Computer peripherals ALVT selection table TSSOP SSOP Suffix DGG Suffix DL Type number Function Description 74ALVT162240 Buffer/inverter/driver 16-bit inverter/line driver with bus hold and 30 Ω termination (3-state) • • 74ALVT162241 Buffer/inverter/driver 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • 74ALVT162244 Buffer/inverter/driver 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • 74ALVT162245 Transceiver 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) • • 74ALVT16240 Buffer/inverter/driver 16-bit inverter/line driver with bus hold (3-state) • • 74ALVT16241 Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • • 74ALVT16244 Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • • 74ALVT16245 Transceiver 16-bit transceiver with bus hold (3-state) • • 74ALVT16260 Latch/registered driver 12-bit to 24-bit multiplexed D-type latch with bus hold (3-state) • • 74ALVT162821 D-type flip-flop 20-bit D-type flip-flop; positive-edge trigger (3-state) • • 74ALVT162823 D-type flip-flop 18-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • 74ALVT162827 Buffer/inverter/driver 20-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • • 74ALVT16373 Latch/registered driver 16-bit D-type transparent latch with bus hold (3-state) • • 74ALVT16374 D-type flip-flop 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • • 74ALVT16501 Transceiver 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) • • 74ALVT16543 Transceiver 16-bit registered transceiver with bus hold (3-state) • • 74ALVT16601 Transceiver 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) • • 74ALVT16652 Transceiver 16-bit registered transceiver with bus hold (3-state) • • 74ALVT16821 D-type flip-flop 20-bit D-type flip-flop; positive-edge trigger (3-state) • • 74ALVT16823 D-type flip-flop 18-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • • 74ALVT16827 Buffer/inverter/driver 20-bit buffer/line driver with bus hold (3-state) • • 58 NXP Logic selection guide 2016 AVC(M) LOGIC AVC and AVCM devices are advanced, very low-voltage CMOS logic. With a typical propagation delay of 1.5 ns, AVC and AVCM devices are some of the fastest logic devices in the industry. To reduce under- and overshoots at outputs, the AVCM has a source-terminated, balanced drive of 12 mA drive. AVCM devices also use dynamically controlled outputs (DCO) to increase output impedance after the output transition is completed. The result is termination with a high signal rate. The parallel-interface products are fully specified from -40 to +85 °C. The dual-supply transceivers for level translation are fully specified from -40 to +125 °C. Features and benefits 4 Typical propagation delay of 1.5 ns 4 Dynamically controlled outputs 4 Wide supply range (1.2 to 3.6 V) 4 3.6 V-tolerant I/O 4 IOFF supports partial power-down mode 4 Buffers and drivers with 15 Ω integrated series termination (optional) 4 Bus hold on data inputs (optional) 4 Dual-supply level translation 4 Bus-interface functions in 16-bit versions Applications 4High-end workstations, servers, and desktop PCs 4High-end telecommunications switching equipment 4Telecommunication basestations 4Memory modules 4Voltage-level translation AVC(M) selection table (cont.) TSSOP VSSOP Suffix DGG, PW Type number Function Description 74AVC16244 Buffer/inverter/driver 16-bit buffer/line driver (3-state) • 74AVC16334A Latch/registered driver 16-bit registered driver (3-state) • 74AVC16373 74AVC16374 16-bit D-type transparent latch Latch/registered driver (3-state) 16-bit D-type flip-flop; positiveD-type flip-flop edge trigger (3-state) • 74AVC16835A Latch/registered driver 18-bit registered driver (3-state) • 74AVC16836A Latch/registered driver 20-bit registered driver (3-state) • Level shifter/translator 74AVC1T45 Level shifter/translator 74AVC20T245 Level shifter/translator 74AVC2T45 Level shifter/translator 74AVC32T245 Level shifter/translator 74AVC4T245 Level shifter/translator 74AVC4TD245 Level shifter/translator 74AVC8T245 Level shifter/translator 74AVCH16244 Buffer/inverter/driver 74AVCH16T245 Level shifter/translator 74AVCH1T45 Level shifter/translator BGA MicroPak PicoGate Suffix Suffix GD, GF, BQ, Suffix GM, GN, BX, EC, EV GS, GT, GU GX Suffix DP, GW, GV • Latch/registered driver 18-bit registered driver (3-state) 74AVC16T245 Suffix D QFN • 74AVC16834A 16-bit dual-supply voltagetranslating transceiver (3-state) Single dual-supply voltagetranslating transceiver (3-state) 20-bit dual-supply voltagetranslating transceiver (3-state) Dual-bit dual-supply voltagetranslating transceiver (3-state) 32-bit dual-supply voltagetranslating transceiver (3-state) 4-bit dual-supply voltagetranslating transceiver (3-state) 4-bit dual-supply voltagetranslating transceiver (3-state) 8-bit dual-supply voltagetranslating transceiver (3-state) 16-bit buffer/line driver with bus hold (3-state) 16-bit dual-supply voltagetranslating transceiver with bus hold (3-state) Single dual-supply voltagetranslating transceiver with bus hold (3-state) Suffix DC SO • • • • • • • • • • • • • • • • • • • • • • • • NXP Logic selection guide 2016 59 AVC(M) selection table (cont.) Type number Function 74AVCH20T245 Level shifter/translator 74AVCH2T45 Level shifter/translator 74AVCH4T245 Level shifter/translator 74AVCH8T245 Level shifter/translator TSSOP VSSOP Suffix DGG, PW Description 20-bit dual-supply voltagetranslating transceiver with bus hold (3-state) Dual-bit dual-supply voltagetranslating transceiver with bus hold (3-state) 4-bit dual-supply voltagetranslating transceiver with bus hold (3-state) 8-bit dual-supply voltagetranslating transceiver with bus hold (3-state) Suffix DC SO Suffix D QFN BGA MicroPak PicoGate Suffix Suffix GD, GF, BQ, Suffix GM, GN, BX, EC, EV GS, GT, GU GX Suffix DP, GW, GV • • • • 74AVCM162834 Latch/registered driver 18-bit registered driver with 30 Ω termination resistors (3-state) • 74AVCM162835 Latch/registered driver 18-bit registered driver with 15 Ω termination resistors (3-state) • 74AVCM162836 Latch/registered driver 20-bit registered driver with 15 Ω termination resistors (3-state) • • • • • • AUP LOGIC The AUP family is the industry standard for portable applications. It is manufactured in a CMOS process that results in lower static and dynamic power dissipation. It’s 3.6 V tolerance, low-threshold inputs (option) and IOFF features make it suitable for use in mixed 1.8/3.3 V and partial powerdown applications. The family is fully specified from 1.1 to 3.6 V and is guaranteed for industrial and automotive operating temperatures. Features and benefits 4 Very low dynamic power dissipation (CPD) 4 Wide supply voltage VCC (0.8 to 3.6 V) 4 Schmitt-trigger action provides high noise immunity 4 Superior ESD protection 4 Wide operating temperature of -40 to +125 °C 4 tPD of 3.2 ns and IOL of 2.2 mA at 1.8 V VCC Applications 4 Mobile phones 4 PDAs 4 Digital cameras 4 Media players 4 Portable medical devices 4 Other handheld, power-sensitive applications AUP selection table (cont.) VSSOP MicroPak PicoGate Suffix DC Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV Type number Function Description 74AUP1G00 NAND gate Single 2-input NAND gate • • 74AUP1G04 Buffer/inverter/driver Single inverter • • 74AUP1G06 Buffer/inverter/driver Single inverter; open drain • • 74AUP1G07 Buffer/inverter/driver Single buffer; open drain • • 74AUP1G08 AND gate Single 2-input AND gate • • 74AUP1G0832 Combination gate Single 3-input AND-OR gate • • 74AUP1G09 AND gate Single 2-input AND gate; open drain • • 60 NXP Logic selection guide 2016 AUP selection table (cont.) VSSOP MicroPak PicoGate Suffix DC Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV Type number Function Description 74AUP1G11 AND gate Single 3-input AND gate • • 74AUP1G125 Buffer/inverter/driver Single buffer/line driver (3-state) • • 74AUP1G126 Buffer/inverter/driver Single buffer/line driver (3-state) • • 74AUP1G132 NAND gate Single 2-input NAND gate Schmitt trigger • • 74AUP1G14 Buffer/inverter/driver Single inverter; Schmitt trigger • • 74AUP1G157 Digital multiplexer Single 2-input multiplexer • • 74AUP1G158 Digital multiplexer Single 2-input multiplexer; inverting • • 74AUP1G17 Schmitt trigger Single buffer Schmitt trigger • • 74AUP1G175 D-type flip-flop Single D flip-flop with reset; positive-edge trigger • • 74AUP1G18 Decoder/demultiplexer 1-to-2 demultiplexer (3-state) • • 74AUP1G19 Decoder/demultiplexer 1-to-2 decoder/demultiplexer • • 74AUP1G240 Buffer/inverter/driver Single inverter/line driver (3-state) • • 74AUP1G32 OR gate Single 2-input OR gate • • 74AUP1G3208 Combination gate Single 3-input OR-AND gate • • 74AUP1G332 OR gate Single 3-input OR gate • • 74AUP1G34 Buffer/inverter/driver Single buffer • • 74AUP1G373 Latch/registered driver Single D-type transparent latch (3-state) • • 74AUP1G374 D-type flip-flop Single D-type flip-flop; positive-edge trigger (3-state) • • 74AUP1G38 NAND gate Single 2-input NAND gate; open drain • • 74AUP1G386 EXCLUSIVE-OR gate Single 3-input EXCLUSIVE-OR gate • • 74AUP1G57 Configurable multifunction gate Configurable gate; Schmitt trigger • • 74AUP1G58 Configurable multifunction gate Configurable gate; Schmitt trigger • • 74AUP1G74 D-type flip-flop Single D-type flip-flop with set and reset; positive-edge trigger • • 74AUP1G79 D-type flip-flop Single D-type flip-flop; positive-edge trigger • • 74AUP1G80 D-type flip-flop Single D-type flip-flop; positive-edge trigger • • 74AUP1G86 EXCLUSIVE-OR gate Single 2-input EXCLUSIVE-OR gate • • 74AUP1G885 Combination gate Dual function gate • • 74AUP1G97 Configurable multifunction gate Configurable gate; Schmitt trigger • • 74AUP1G98 Configurable multifunction gate Configurable gate; Schmitt trigger • • 74AUP1GU04 Buffer/inverter/driver Single inverter; unbuffered • • 74AUP1T34 Level shifter/translator Single dual-supply translating buffer • • 74AUP1T45 Level shifter/translator Single dual-supply voltage-translating transceiver (3-state) • • 74AUP1T57 Configurable multifunction gate Configurable gate with voltage level translation • • NXP Logic selection guide 2016 61 AUP selection table (cont.) VSSOP MicroPak PicoGate Suffix DC Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV Type number Function Description 74AUP1T58 Configurable multifunction gate Configurable gate with voltage level translation • • 74AUP1T97 Configurable multifunction gate Configurable gate with voltage level translation • • 74AUP1T98 Configurable multifunction gate Configurable gate with voltage level translation • • 74AUP1Z04 Combination gate Crystal driver with enable and internal resistor • • 74AUP1Z125 Combination gate Crystal driver with enable and internal resistor (3-state) • • 74AUP2G00 NAND gate Dual 2-input NAND gate • • • 74AUP2G02 NOR gate Dual 2-input NOR gate • • • 74AUP2G04 Buffer/inverter/driver Dual inverter • • 74AUP2G06 Buffer/inverter/driver Dual inverter; open drain • • 74AUP2G0604 Combination gate Inverter with open drain and inverter • • 74AUP2G07 Buffer/inverter/driver Dual buffer; open drain • • 74AUP2G08 AND gate Dual 2-input AND gate • • • 74AUP2G125 Buffer/inverter/driver Dual buffer/line driver (3-state) • • • 74AUP2G126 Buffer/inverter/driver Dual buffer/line driver (3-state) • • • 74AUP2G132 Schmitt trigger Dual 2-input NAND gate Schmitt trigger • • • 74AUP2G14 Buffer/inverter/driver Dual inverter; Schmitt trigger • • • 74AUP2G157 Digital multiplexer Single 2-input multiplexer • • • 74AUP2G17 Schmitt trigger Dual buffer Schmitt trigger • • • 74AUP2G240 Buffer/inverter/driver Dual inverter/line driver (3-state) • • • 74AUP2G241 Buffer/inverter/driver Dual buffer/line driver (3-state) • • • 74AUP2G32 OR gate Dual 2-input OR gate • • • 74AUP2G34 Buffer/inverter/driver Dual buffer • • • 74AUP2G3404 Combination gate Buffer and inverter • • • 74AUP2G3407 Combination gate Buffer and buffer with open drain • • • 74AUP2G38 NAND gate Dual 2-input NAND gate; open drain • • • 74AUP2G79 D-type flip-flop Dual D-type flip-flop; positive-edge trigger • • • 74AUP2G80 D-type flip-flop Dual D-type flip-flop; positive-edge trigger • • • 74AUP2G86 EXCLUSIVE-OR gate Dual 2-input EXCLUSIVE-OR gate • • • 74AUP2GU04 Buffer/inverter/driver Dual inverter; unbuffered • • • 74AUP2T1326 Combination gate Dual supply buffer/line driver; 3-state • • • 74AUP3G04 Buffer/inverter/driver Triple inverter • • • 74AUP3G0434 Combination gate Dual inverter and single buffer • • • 74AUP3G3404 Combination gate Dual buffer and single inverter • • • 62 NXP Logic selection guide 2016 AXP LOGIC As the first logic family fully specified at 0.8 V, the Advanced eXtremely low voltage and Power (AXP) family is a speed upgrade to the 1.8 V AUP family, but without an increase in dynamic power dissipation. These devices are ultra-lowpower, small-footprint solutions for use in 1.2 and 1.2/2.5 V applications. Supporting a supply range from 0.75 to 2.75 V, AXP logic supports the trend toward lower-voltage nodes of 1.2 and 0.8 V. All are fully specified from -40 to 85 °C. Features and benefits 4 Very low dynamic power dissipation (CPD) 4 Wide supply range (0.7 to 2.75 V) 4 Fully specified at 0.8 V 4 Wide operating temperature (-40 to 85 °C) 4 tpd of 4.6 ns and IO of ±4.5 mA at 1.2 V supply Applications 4Smartphones, tablets 4Digital cameras 4Portable medical devices 4Other power-sensitive applications AXP selection table MicroPak MicroPak MicroPak MicroPak Suffix GM Suffix GN Suffix GS Suffix GX Single inverter; open drain • • • • AND gate Single 2-input AND gate • • • • 74AXP1G125 Buffer/inverter/driver Single buffer/line driver (3-state) • • • • 74AXP1G57 Configurable multi-function gate Configurable gate; Schmitt trigger • • • 74AXP1G58 Configurable multi-function gate Configurable gate; Schmitt trigger • • • 74AXP1G97 Configurable multi-function gate Configurable gate; Schmitt trigger • • • • 74AXP1G98 Configurable multi-function gate Configurable gate; Schmitt trigger • • • • 74AXP1G00 NAND Gate 74AXP1G02 NOR Gate 74AXP1G04 Buffer/inverter/driver Type number Function Description 74AXP1G06 Buffer/inverter/driver 74AXP1G08 single 2-input NAND gate, Low-power 2-input NAND gate single 2-input NOR gate, Low-power 2-input NOR gate single inverter, Low-power inverter Low Power Buffer with Open Drain Outputs Low-power 2-input AND gate with opendrain • • • • • • • • • • 74AXP1G07 Buffer/inverter/driver 74AXP1G09 AND Gate 74AXP1G10 NAND Gate Low Power 3-input NAND Gate • 74AXP1G11 AND Gate Low Power 3-input AND Gate • 74AXP1G14 Schmitt Triggers single inverter Schmitt trigger, Low-power Schmitt trigger inverter • 74AXP1G157 Multiplexer Single 2-input Multiplexer • 74AXP1G17 Schmitt Triggers 74AXP1G32 OR Gates 74AXP1G86 EX-OR Gate Low-power Schmitt trigger, Low-power Schmitt trigger Single 2-input OR gate, Low-power 2-input OR gate Low-power 2-input EXCLUSIVE-OR gate Low-power dual buffer with open-drain output, Low-power dual buffer with open-drain output Low-power dual Schmitt trigger inverter, Low-power dual Schmitt Trigger Inverter • • • • • • • • • 74AXP2G07 Buffer/inverter/driver • • • • 74AXP2G14 Buffer/inverter/driver • • • • 74AXP2G17 Buffer/inverter/driver Low-power dual Schmitt trigger • 74AXP2G34 Buffer Low-power dual Buffer • 74AXP2G3404 Buffer and Inverter Low power buffer and inverter • NXP Logic selection guide 2016 63 CBTLV(D) LOGIC CBTLV and CBTLVD bus switches are low-delay, singletransistor or transmission-gate solutions for multiplexing data buses, hot-swapping boards in backplanes, memory interleaving, signal conditioning, or unidirectional level shifting. They are fully specified from either -40 to +85 °C or from -40 to +125 °C. Features and benefits 4 5 -to-3.3 V level shifting 4 3.3-to-1.8 V level shifting 4 Low propagation delay 4 T TL control inputs Applications 4 Telecommunications infrastructure 4 Memory interleaving 4 Industrial control 4 Unidirectional level shifting 4 Cell phones CBTLV(D) selection table TSSOP SSOP SO DQFN Micro PicoGate Suffix DGG, DGV, PW Suffix DK, DS Suffix D Suffix BQ Suffix GF, GM, GN, GS Suffix GV, GW • • Type number Function Description 74CBTLV16211 Bus switch 24-bit bus switch 74CBTLV1G125 Bus switch Single bus switch 74CBTLV3125 Bus switch Quad bus switch • • • 74CBTLV3126 Bus switch Quad bus switch • • • 74CBTLV3244 Bus switch Octal bus switch • • • 74CBTLV3245 Bus switch Octal bus switch • • • 74CBTLV3253 Mux/demux Dual 4:1 mux/demux • • • • 74CBTLV3257 Mux/demux Quad 2:1 mux/demux • • • • 74CBTLV3384 Bus switch 10-bit bus switch • • • 74CBTLV3861 Bus switch 10-bit bus switch • • • 74CBTLVD3244 Bus switch level shifter Octal bus switch level translator • • • 74CBTLVD3245 Bus switch level shifter Octal bus switch level translator • • • 74CBTLVD3384 Bus switch level shifter 10-bit bus switch level translator • • • 74CBTLVD3861 Bus switch level shifter 10-bit bus switch level translator • • • 64 NXP Logic selection guide 2016 • Product listing by function Analog switches Buffers/inverters/drivers Bus switches Counters/frequency dividers Decoders/demultiplexers Digital comparators Digital multiplexers Encoders FIFO registers Flip-flops Full adders Gates AND gates Combination gates EXCLUSIVE-OR gates EXCLUSIVE-NOR gates NAND gates NOR gates OR gates Latches / registered drivers Level shifters/translators Multivibrators Parity generators/checkers Phase-locked loops Schmitt triggers Shift registers/LED drivers Transceivers 66 68 75 76 78 80 80 81 82 82 86 87 87 88 89 89 90 92 93 94 96 98 99 99 100 102 104 NXP Logic selection guide 2016 65 ANALOG SWITCHES Features and benefits 4 Reduced signal attenuation for low switching losses 4 Reduced THD for high-quality audio switching 4 Fewer ADCs with analog sensor multiplexing 4 Integrated level shifting 4 Low ON resistance, ON flatness 4 Low switch leakage 4 Wide supply voltage 4 Options for low input threshold 4 Overvoltage-tolerant options 4 High ESD protection per IEC 61000 standard Applications 4 Audio/video source selection 4 Analog sensor multiplexing 4 GPIO expansion 4 Bus isolation 4 Sample-and-hold circuits Analog switches (cont.) VCC (V) Logic switching levels RON (Ω) RON(FLAT) (Ω) f(-3dB) (MHz) THD (%) Single-pole, single-throw analog switch 2.0 to 5.5 CMOS 40 14 280 0.015 -40 to +125 74AHCT1G66 Single-pole, single-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 40 14 280 0.015 -40 to +125 74HC1G66 Single-pole, single-throw analog switch 2.0 to 9.0 CMOS 105 23 200 0.02 -40 to +125 74HCT1G66 Single-pole, single-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 118 23 180 0.04 -40 to +125 74HC2G66 Dual single-pole, single-throw analog switch 2.0 to 9.0 CMOS 105 23 200 0.02 -60 -40 to +125 74HCT2G66 Dual single-pole, single-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 118 23 180 0.04 -60 -40 to +125 74HC4016 Quad single-pole, single-throw analog switch 2.0 to 10.0 CMOS 300 80 160 0.4 -60 -40 to +125 74HCT4016 Quad single-pole, single-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 400 50 150 0.8 -60 -40 to +125 74HC4051 Single-pole, octal-throw analog switch 2.0 to 10.0 CMOS 200 20 180 0.02 -40 to +125 74HCT4051 Single-pole, octal-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 225 20 170 0.04 -40 to +125 74HC4052 Dual single-pole, quad-throw analog switch 2.0 to 10.0 CMOS 200 20 180 0.02 -60 -40 to +125 74HCT4052 Dual single-pole, quad-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 225 20 170 0.04 -60 -40 to +125 74HC4053 Triple single-pole, double-throw analog switch 2.0 to 10.0 CMOS 200 20 170 0.02 -40 to +125 74HCT4053 Triple single-pole, double-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 225 20 160 0.04 -40 to +125 74HC4066 Quad single-pole, single-throw analog switch 2.0 to 10.0 CMOS 105 23 200 0.02 -60 -40 to +125 74HCT4066 Quad single-pole, single-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 118 23 180 0.04 -60 -40 to +125 74HC4067 Single-pole, 16-throw analog switch 2.0 to 10.0 CMOS 200 25 100 0.02 -40 to +125 74HCT4067 Single-pole, 16-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 225 25 90 0.04 -40 to +125 74HC4316 Quad single-pole, single-throw analog switch with translation 2.0 to 10.0 CMOS 300 80 160 0.4 Type number Description 74AHC1G66 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 66 NXP Logic selection guide 2016 Xtalk (dB) -60 Tamb (°C) -40 to +125 Analog switches (cont.) VCC (V) Logic switching levels RON (Ω) RON(FLAT) (Ω) f(-3dB) (MHz) THD (%) Xtalk (dB) Tamb (°C) Quad single-pole, single-throw analog switch with translation; TTL-enabled 4.5 to 5.5 TTL 400 50 150 0.8 -60 -40 to +125 74HC4351 Single-pole, octal-throw analog switch with latch 2.0 to 10.0 CMOS 200 20 180 0.02 -40 to +125 74HCT4351 Single-pole, octal-throw analog switch with latch; TTL-enabled 4.5 to 5.5 TTL 225 20 170 0.04 -40 to +125 74HC4353 Triple single-pole, double-throw analog switch with latch 4.5 to 5.5 TTL 225 20 160 0.04 -60 -40 to +125 74HCT4353 Triple single-pole, double-throw analog switch with latch; TTL-enabled 4.5 to 5.5 TTL 225 20 160 0.04 -60 -40 to +125 74HC4851 Single-pole, octal-throw analog switch 2.0 to 10.0 CMOS 220 -40 to +125 74HCT4851 Single-pole, octal-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 240 -40 to +125 74HC4852 Dual single-pole, quad-throw analog switch; TTL-enabled 2.0 to 10.0 CMOS 220 -40 to +125 74HCT4852 Dual single-pole, quad-throw analog switch; TTL-enabled 4.5 to 5.5 TTL 240 -40 to +125 74LV4051 Single-pole, octal-throw analog switch 1.0 to 6.0 TTL 135 35 200 0.4 -60 -40 to +125 74LV4052 Dual single-pole, quad-throw analog switch 1.0 to 6.0 TTL 125 15 180 0.4 -60 -40 to +125 74LV4053 Triple single-pole, double-throw analog switch 1.0 to 6.0 TTL 150 30 180 0.4 -60 -40 to +125 74LV4066 Quad single-pole, single-throw analog switch 1.0 to 6.0 TTL 50 3 180 0.02 -60 -40 to +125 74LVC1G3157 Single-pole, double-throw analog switch 1.65 to 5.5 CMOS/ LVTTL 15 1,5 300 0.078 -40 to +125 74LVC1G384 Single-pole, single-throw analog switch 1.65 to 5.5 CMOS/ LVTTL 15 1,5 440 0.001 -40 to +125 74LVC1G53 Single-pole, double-throw analog switch 1.65 to 5.5 CMOS/ LVTTL 15 1,5 300 0.078 -40 to +125 74LVC1G66 Single-pole, single-throw analog switch 1.65 to 5.5 CMOS/ LVTTL 15 1,5 440 0.001 -40 to +125 74LVC2G53 Single-pole, double-throw analog switch 1.65 to 5.5 CMOS/ LVTTL 15 1,5 300 0.078 -40 to +125 74LVC2G66 Dual single-pole, single-throw analog switch 1.65 to 5.5 CMOS/ LVTTL 15 1,5 440 0.005 -40 to +125 74LVC4066 Quad single-pole, single-throw analog switch 1.65 to 5.5 CMOS/ LVTTL 15 1,5 440 0.005 -40 to +125 74LVCV2G66 Dual single-pole, single-throw analog switch; overvoltage tolerant 2.3 to 5.5 CMOS/ LVTTL 15 3 210 0.01 -40 to +125 HEF4016 Quad single-pole, single-throw analog switch 4.5 to 15.5 CMOS 350 65 90 0.04 -50 -40 to +85 HEF4051 Single-pole, octal-throw analog switch 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85 HEF4052 Dual single-pole, quad-throw analog switch 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85 HEF4053 Triple single-pole, double-throw analog switch 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85 HEC4066 Quad single-pole, single-throw analog switch 4.5 to 15.5 CMOS 175 20 90 0.04 -50 -40 to +85 HEF4067 Single-pole, 16-throw analog switch 4.5 to 15.5 CMOS 175 20 13 0.04 -50 -40 to +85 Type number Description 74HCT4316 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 67 BUFFERS/INVERTERS/DRIVERS Features and benefits 4 Improved current drive and signal levels 4 Improved signal integrity in complex layouts 4 Widths from one to 32 bits 4 Inverting, non-inverting variants 4 Mixed 3.3/5 V applications 4 Wide range of supply voltages 4 Low propagation delay 4O ptional TTL inputs, 3-state outputs, overvoltage-tolerant inputs, bus hold Applications 4STBs 4LCD TVs 4Cell phones 4Industrial monitoring Buffers-inverters-drivers (cont.) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) fmax (MHz) Tamb (°C) Type number Description VCC (V) 74AHC04 Hex inverter 2.0 to 5.5 CMOS ±8 50 pF 3 60 -40 to +125 74AHCT04 Hex inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125 74AHC125 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3 60 -40 to +125 74AHCT125 Quad buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125 74AHC126 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.3 60 -40 to +125 74AHCT126 Quad buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125 74AHC1G04 Single inverter 2.0 to 5.5 CMOS ±8 50 pF 3.1 60 -40 to +125 74AHCT1G04 Single inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125 74AHC1G06 Single inverter; open drain 2.0 to 5.5 CMOS 8 50 pF 2.7 60 -40 to +125 74AHCT1G06 Single inverter; open drain; TTL-enabled 4.5 to 5.5 TTL 8 50 pF 3 60 -40 to +125 74AHC1G07 Single buffer; open drain 2.0 to 5.5 CMOS 8 50 pF 2.5 60 -40 to +125 74AHCT1G07 Single buffer; open drain; TTL-enabled 4.5 to 5.5 TTL 8 50 pF 2.8 60 -40 to +125 74AHC1G125 Single buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125 74AHCT1G125 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125 74AHC1G126 Single buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125 74AHCT1G126 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125 74AHC1G17 Single buffer with Schmitt-trigger inputs 2.0 to 5.5 CMOS ±8 50 pF 3.2 60 -40 to +125 74AHCT1G17 Single buffer with Schmitt-trigger inputs; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 4.1 60 -40 to +125 74AHC240 Octal inverter/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 2.8 60 -40 to +125 74AHCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125 74AHC244 Octal buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125 74AHCT244 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125 74AHC2G125 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125 74AHCT2G125 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125 74AHC2G126 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 68 NXP Logic selection guide 2016 Buffers-inverters-drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) fmax (MHz) Tamb (°C) Type number Description 74AHCT2G126 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125 74AHC2G241 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125 74AHCT2G241 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125 74AHC3G04 Triple inverter 2.0 to 5.5 CMOS ±8 50 pF 3.1 60 -40 to +125 74AHCT3G04 Triple inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125 74AHC541 Octal buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125 74AHCT541 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125 74AHC1GU04 Single inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 2.6 60 -40 to +125 74AHC3GU04 Triple inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 2.5 60 -40 to +125 74AHCU04 Hex inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 2.4 60 -40 to +125 74ALVC16244 16-bit buffer/line driver (3-state) 1.2 to 3.6 LVTTL ±24 50 pF 1.9 150 -40 to +85 74ALVCH16244 16-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 LVTTL ±24 30 pF 1.9 150 -40 to +85 74ALVC04 Hex inverter 1.65 to 3.6 LVTTL ±24 30 pF 2 150 -40 to +85 74ALVC125 Quad buffer/line driver (3-state) 1.65 to 3.6 LVTTL ±24 30 pF 1.8 145 -40 to +85 74ALVC244 Octal buffer/line driver (3-state) 1.65 to 3.6 LVTTL ±24 30 pF 2.9 130 -40 to +85 74ALVC541 Octal buffer/line driver (3-state) 1.65 to 3.6 LVTTL ±24 30 pF 2.3 130 -40 to +85 74ALVCH162244 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 LVTTL ±12 30 pF 2.7 150 -40 to +85 74ALVCH162827 20-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 LVTTL ±12 30 pF 2.9 150 -40 to +85 74ALVCH16825 18-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL ±24 30 pF 2 150 -40 to +85 74ALVCH16827 20-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL ±24 30 pF 2 150 -40 to +85 74ALVT162240 16-bit inverter/line driver with bus hold and 30 Ω termination (3-state) 2.3 to 3.6 LVTTL ±12 50 pF 2.6 75 -40 to +85 74ALVT162241 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 LVTTL ±12 50 pF 2.2 75 -40 to +85 74ALVT162244 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 LVTTL ±12 50 pF 2.2 75 -40 to +85 74ALVT16240 16-bit inverter/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.7 200 -40 to +85 74ALVT16241 16-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.3 200 -40 to +85 74ALVT16244 16-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.5 200 -40 to +85 74ALVT162827 20-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 LVTTL ±12 50 pF 2.2 75 -40 to +85 74ALVT16827 20-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.3 200 -40 to +85 74AUP1G04 Single inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125 74AUP1G06 Single inverter; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.5 70 -40 to +125 74AUP1G07 Single buffer; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.4 70 -40 to +125 74AUP1G125 Single buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP1G126 Single buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP1G14 Single inverter; Schmitt trigger 1.1 to 3.6 CMOS ±1.9 30 pF 4.7 70 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 69 Buffers-inverters-drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) fmax (MHz) Tamb (°C) Type number Description 74AUP1G240 Single inverter/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.2 70 -40 to +125 74AUP1G34 Single buffer 1.1 to 3.6 CMOS ±1.9 30 pF 3.9 70 -40 to +125 74AUP1GU04 Single inverter; unbuffered 1.1 to 3.6 CMOS ±1.9 30 pF 2.3 70 -40 to +125 74AUP2G04 Dual inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125 74AUP2G06 Dual inverter; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.5 70 -40 to +125 74AUP2G07 Dual buffer; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.4 70 -40 to +125 74AUP2G125 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP2G126 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP2G14 Dual inverter; Schmitt trigger 1.1 to 3.6 CMOS ±1.9 30 pF 4.7 70 -40 to +125 74AUP2G240 Dual inverter/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.2 70 -40 to +125 74AUP2G241 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP2G34 Dual buffer 1.1 to 3.6 CMOS ±1.9 30 pF 3.9 70 -40 to +125 74AUP2GU04 Dual inverter; unbuffered 1.1 to 3.6 CMOS ±1.9 30 pF 2.3 70 -40 to +125 74AUP3G04 Triple inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125 74AVC16244 16-bit buffer/line driver (3-state) 0.8 to 3.6 CMOS/ LVTTL ±12 30 pF 2 200 -40 to +85 74AVCH16244 16-bit buffer/line driver with bus hold (3-state) 0.8 to 3.6 CMOS/ LVTTL ±12 30 pF 2 200 -40 to +85 74AXP1G06 Single inverter; open drain 0.7 to 2.75 CMOS 4,5 5pF 3.5 70 -40 to +85 74AXP1G125 Single buffer/line driver (3-state) 0.7 to 2.75 CMOS ±4.5 5pF 2.7 70 -40 to +85 74HC04 Hex inverter 2.0 to 6.0 CMOS ±5.2 50 pF 7 36 -40 to +125 74HCT04 Hex inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 8 36 -40 to +125 74HC125 Quad buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT125 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±6 50 pF 12 36 -40 to +125 74HC126 Quad buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT126 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC1G04 Single inverter 2.0 to 6.0 CMOS ±2.6 50 pF 7 36 -40 to +125 74HCT1G04 Single inverter; TTL-enabled 4.5 to 5.5 TTL ±2.0 50 pF 8 36 -40 to +125 74HC1G125 Single buffer/line driver (3-state) 2.0 to 6.0 CMOS ±2.6 50 pF 9 36 -40 to +125 74HCT1G125 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±2.0 50 pF 10 36 -40 to +125 74HC1G126 Single buffer/line driver (3-state) 2.0 to 6.0 CMOS ±2.6 50 pF 9 36 -40 to +125 74HCT1G126 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±2.0 50 pF 10 36 -40 to +125 74HC240 Octal inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125 74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125 74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125 74HC241 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 7 36 -40 to +125 74HCT241 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 70 NXP Logic selection guide 2016 Buffers-inverters-drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) fmax (MHz) Tamb (°C) Type number Description 74HC244 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT244 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC2G04 Dual inverter 2.0 to 6.0 CMOS ±5.2 50 pF 8 36 -40 to +125 74HCT2G04 Dual inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125 74HC2G125 Dual buffer/line driver (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 10 36 -40 to +125 74HCT2G125 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4.0 50 pF 12 36 -40 to +125 74HC2G126 Dual buffer/line driver (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 10 36 -40 to +125 74HC2G34 Dual buffer 2.0 to 6.0 CMOS ±5.2 50 pF 9 36 -40 to +125 74HCT2G34 Dual buffer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 10 32 -40 to +125 74HC365 Hex buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT365 Hex buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC366 Hex inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 10 36 -40 to +125 74HCT366 Hex inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC367 Hex buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 8 36 -40 to +125 74HCT367 Hex buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC368 Hex inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT368 Hex inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC3G04 Triple inverter 2.0 to 6.0 CMOS ±5.2 50 pF 8 36 -40 to +125 74HCT3G04 Triple inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125 74HC3G06 Triple inverter; open drain 2.0 to 6.0 CMOS 5,2 50 pF 9 36 -40 to +125 74HCT3G06 Triple inverter; open drain; TTL-enabled 4.5 to 5.5 TTL 4 50 pF 9 36 -40 to +125 74HC3G07 Triple buffer; open drain 2.0 to 6.0 CMOS 5,2 50 pF 9 36 -40 to +125 74HCT3G07 Triple buffer; open drain; TTL-enabled 4.5 to 5.5 TTL 4 50 pF 9 36 -40 to +125 74HC3G34 Triple buffer 2.0 to 6.0 CMOS ±5.2 50 pF 9 36 -40 to +125 74HCT3G34 Triple buffer; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125 74HC540 Octal inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT540 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC541 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 10 36 -40 to +125 74HCT541 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 12 36 -40 to +125 74HC05 Hex inverter; open drain 2.0 to 6.0 CMOS 5,2 50 pF 11 36 -40 to +125 74HC1GU04 Single inverter; unbuffered 2.0 to 6.0 CMOS ±2.6 50 pF 5 36 -40 to +125 74HC2GU04 Single inverter; unbuffered 2.0 to 6.0 CMOS ±2.6 50 pF 5 36 -40 to +125 74HC3GU04 Triple inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 6 36 -40 to +125 74HC3GU04 Triple inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 6 36 -40 to +125 74HCU04 Hex inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 5 36 -40 to +125 74LV04 Hex inverter 1.0 to 5.5 CMOS ±12 50 pF 6 30 -40 to +125 74LV125 Quad buffer/line driver (3-state) 1.0 to 5.5 CMOS ±16 50 pF 9 30 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 71 Buffers-inverters-drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) fmax (MHz) Tamb (°C) Type number Description 74LV241 Octal buffer/line driver (3-state) 1.0 to 5.5 CMOS ±8 50 pF 8 30 -40 to +125 74LV244 Octal buffer/line driver (3-state) 1.0 to 5.5 CMOS ±16 50 pF 8 30 -40 to +125 74LV365 Hex buffer/line driver (3-state) 1.0 to 3.6 CMOS ±8 50 pF 9 30 -40 to +125 74LV367 Hex buffer/line driver (3-state) 1.0 to 3.6 CMOS ±8 50 pF 8 30 -40 to +125 74LV541 Octal buffer/line driver (3-state) 1.0 to 3.6 CMOS ±8 50 pF 10 30 -40 to +125 74LVC162244 16-bit buffer/line driver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.9 175 -40 to +125 74LVCH162244 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 50 pF 2.9 175 -40 to +125 74LVC16244 16-bit buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 3 175 -40 to +125 74LVCH16244 16-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 3 175 -40 to +125 74LVC244 Octal buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.8 175 -40 to +125 74LVCH244 Octal buffer/line driver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.8 175 -40 to +125 74LVC04 Hex inverter 1.65 to 5.5 CMOS/ LVTTL ±24 50 pF 2 175 -40 to +125 74LVC06 Hex inverter; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2.2 175 -40 to +125 74LVC07 Hex buffer; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2.2 175 -40 to +125 74LVC125 Quad buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.4 175 -40 to +125 74LVC126 Quad buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.4 175 -40 to +125 74LVC16240 16-bit inverter/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.7 175 -40 to +125 74LVC16241 16-bit buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.9 175 -40 to +125 74LVC1G04 Single inverter 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2 175 -40 to +125 74LVC1G06 Single inverter; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2.3 175 -40 to +125 74LVC1G07 Single buffer; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2.2 175 -40 to +125 74LVC1G125 Single buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.1 175 -40 to +125 74LVC1G126 Single buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2 175 -40 to +125 74LVC1G34 Single buffer 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2 175 -40 to +125 74LVC1GU04 Single inverter; unbuffered 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 1.6 175 -40 to +125 74LVC2244 Octal buffer/line driver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 50 pF 3.1 175 -40 to +125 74LVC240 Octal inverter/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 3.5 175 -40 to +125 74LVC241 Octal buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 3.2 175 -40 to +125 74LVC2G04 Dual inverter 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.7 175 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 72 NXP Logic selection guide 2016 Buffers-inverters-drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) fmax (MHz) Tamb (°C) Type number Description 74LVC2G06 Dual inverter; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2.3 175 -40 to +125 74LVC2G07 Dual buffer; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2.6 175 -40 to +125 74LVC2G125 Dual buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.3 175 -40 to +125 74LVC2G126 Dual buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.4 175 -40 to +125 74LVC2G240 Dual inverter/line driver (3-state) 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.5 175 -40 to +125 74LVC2G241 Dual buffer/line driver (3-state) 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.6 175 -40 to +125 74LVC2G34 Dual buffer 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.2 175 -40 to +125 74LVC2GU04 Dual inverter; unbuffered 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.3 175 -40 to +125 74LVC3G04 Triple inverter 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.7 175 -40 to +125 74LVC3G06 Triple inverter; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2 175 -40 to +125 74LVC3G07 Triple buffer; open drain 1.65 to 5.5 CMOS/ LVTTL 32 50 pF 2.1 175 -40 to +125 74LVC3G34 Triple buffer 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.2 175 -40 to +125 74LVC3GU04 Triple inverter; unbuffered 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2.3 175 -40 to +125 74LVC541 Octal buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 3.3 175 -40 to +125 74LVC827 10-bit buffer/line driver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 4 175 -40 to +125 74LVCH16541 16-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2.7 175 -40 to +125 74LVCH322244 32-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 50 pF 2 175 -40 to +125 74LVCH32244 32-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 3 175 -40 to +125 74LVCU04 Hex inverter; unbuffered 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2 175 -40 to +125 74LVT125 Quad buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.9 150 -40 to +85 74LVTH125 Quad buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.9 150 -40 to +85 74LVT16244 16-bit buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 1.8 150 -40 to +85 74LVTH16244 16-bit buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 1.8 150 -40 to +85 74LVT244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.6 150 -40 to +85 74LVTH244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.6 150 -40 to +85 74LVT244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2 150 -40 to +85 74LVTH244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2 150 -40 to +85 74LVT04 Hex inverter 2.7 to 3.6 TTL -20 / +32 50 pF 2.6 150 -40 to +85 74LVT126 Quad buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.4 150 -40 to +85 74LVT162240 16-bit inverter/line driver with bus hold and 30 Ω termination (3-state) 2.7 to 3.6 TTL ±12 50 pF 2.6 150 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 73 Buffers-inverters-drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) fmax (MHz) Tamb (°C) Type number Description 74LVT162244 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL ±12 50 pF 2.8 150 -40 to +85 74LVT16240 16-bit inverter/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2 150 -40 to +85 74LVT2241 Octal buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL ±12 50 pF 3.3 150 -40 to +85 74LVT2244 Octal buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL ±12 50 pF 2.9 150 -40 to +85 74LVT240 Octal inverter/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.5 150 -40 to +85 74LVT241 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.8 150 -40 to +85 74LVTN16244 16-bit buffer/line driver (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 1.8 150 -40 to +85 74LVU04 Hex inverter; unbuffered 1.0 to 5.5 CMOS -12 / +12 50 pF 6 30 -40 to +125 74VHC125 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3 60 -40 to +125 74VHCT125 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125 74VHC126 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.3 60 -40 to +125 74VHCT126 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125 74VHC244 Octal inverter/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125 74VHCT244 Octal inverter/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 5 60 -40 to +125 74VHC541 Octal buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125 74VHCT541 Octal buffer/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125 HEF40098 Hex inverter 3.0 to 15.0 CMOS -10 / +20 50 pF 25 10 -40 to +125 HEF40240 Octal inverter/line driver (3-state) 3.0 to 15.0 CMOS -50 / +45 50 pF 30 10 -40 to +125 HEF40244 Octal buffer/line driver (3-state) 3.0 to 15.0 CMOS -62 / +45 50 pF 30 10 -40 to +125 HEF4049 Hex inverter/line driver 3.0 to 15.0 CMOS -3 / +20 50 pF 20 10 -40 to +125 HEF4050 Hex buffer/line driver 3.0 to 15.0 CMOS -3 / +20 50 pF 40 10 -40 to +125 HEF4069 Hex inverter; unbuffered 3.0 to 15.0 CMOS ±3.4 50 pF 15 10 -40 to +125 XC7SET04 Single inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125 XC7SET125 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125 XC7SH04 Single inverter 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125 XC7SH125 Single buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125 XC7SHU04 Single inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125 XC7WH126 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 74 NXP Logic selection guide 2016 BUS SWITCHES Features and benefits 4 Level shifting (1.8/3.3 or 3.3/5 V) 4 Low propagation delay 4 T TL control inputs Applications 4Telecommunications infrastructure 4Industrial control 4Cell phones 4Unidirectional level shifting 4Backplane hotswap 4Memory interleaving 4Signal conditioning Bus switches VCC (V) VPASS (V) Logic switching levels RON (Ω) f(-3dB) (MHz) Number of bits tpd (ns) Tamb (°C) 74CBTLV16211 24-bit bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 10 0.2 -40 to +125 74CBTLV1G125 Single bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 1 0.2 -40 to +125 74CBTLV3125 Quad bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 4 0.2 -40 to +125 74CBTLV3126 Quad bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 4 0.2 -40 to +125 74CBTLV3244 Octal bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 8 0.2 -40 to +125 74CBTLV3245 Octal bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 8 0.2 -40 to +125 74CBTLV3253 Dual 4:1 mux/demux 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 2 0.2 -40 to +125 74CBTLV3257 Quad 2:1 mux/demux 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 4 0.2 -40 to +125 74CBTLV3384 10-bit bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 10 0.2 -40 to +125 74CBTLV3861 10-bit bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 10 0.2 -40 to +125 74CBTLVD3244 Octal bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 8 0.2 -40 to +125 74CBTLVD3245 Octal bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 8 0.2 -40 to +125 74CBTLVD3384 10-bit bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 10 0.2 -40 to +125 74CBTLVD3861 10-bit bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 10 0.2 -40 to +125 CBT16210 20-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 20 0.25 -40 to +85 CBT16211 24-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 24 0.25 -40 to +85 CBT16212 24-bit bus exchange switch 4.5 to 5.5 3,9 TTL 7 300 24 0.25 -40 to +85 CBT16292 12-bit 2:1 mux/demux 4.5 to 5.5 3,9 TTL 8 300 12 0.4 -40 to +85 CBT3125 Quad bus switch 4.5 to 5.5 3,9 TTL 7 300 4 0.25 -40 to +85 CBT3126 Quad bus switch 4.5 to 5.5 3,9 TTL 7 300 4 0.25 -40 to +85 CBT3244 Octal bus switch 4.5 to 5.5 3,9 TTL 7 300 8 0.25 -40 to +85 CBT3245 Octal bus switch 4.5 to 5.5 3,9 TTL 7 300 8 0.25 -40 to +85 CBT3251 8:1 mux/demux 4.5 to 5.5 3,9 TTL 7 300 8 0.25 -40 to +85 CBT3253 Dual 4:1 mux/demux 4.5 to 5.5 3,9 TTL 7 300 2 0.25 -40 to +85 CBT3257 Quad 2:1 mux/demux 4.5 to 5.5 3,9 TTL 7 300 4 0.25 -40 to +85 CBT3306 Dual bus switch 4.5 to 5.5 3,9 TTL 7 300 2 0.25 -40 to +85 CBT3384 10-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 10 0.25 -40 to +85 CBT3861 10-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 10 0.25 -40 to +85 CBTD16210 20-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 20 0.25 -40 to +85 CBTD16211 24-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 24 0.25 -40 to +85 CBTD3306 Dual bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 2 0.25 -40 to +85 CBTD3384 10-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 10 0.25 -40 to +85 CBTD3861 10-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 10 0,25 -40 to +85 Type number Description Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 75 COUNTERS/FREQUENCY DIVIDERS Features and benefits 4 Integrated oscillator 4 Low-power CMOS 4 T TL-compatible inputs Applications 4Generate clock signals 4Frequency-divide external clock signals 4Initiate events after a pre-set number of clock pulses Counters/frequency dividers (cont.) Output Logic drive switching capability levels (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) CMOS 18 50 pF 55 -40 to +125 ±4.0 TTL 21 50 pF 28 -40 to +125 2.0 to 6.0 ±5.2 CMOS 19 50 pF 48 -40 to +125 Presettable synchronous 4-bit binary counter; asynchronous reset; TTL-enabled 4.5 to 5.5 ±4.0 TTL 20 50 pF 41 -40 to +125 74HC163 Presettable synchronous 4-bit binary counter; synchronous reset 2.0 to 6.0 ±5.2 CMOS 17 50 pF 50 -40 to +125 74HCT163 Presettable synchronous 4-bit binary counter; synchronous reset; TTL-enabled 4.5 to 5.5 ±4.0 TTL 20 50 pF 50 -40 to +125 74HC191 Presettable synchronous 4-bit binary up/down counter 2.0 to 6.0 ±5.2 CMOS 22 50 pF 36 -40 to +125 74HCT191 Presettable synchronous 4-bit binary up/down counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 22 50 pF 39 -40 to +125 74HC193 Presettable synchronous 4-bit binary up/down counter; separate up/down clocks 2.0 to 6.0 ±5.2 CMOS 20 50 pF 49 -40 to +125 74HCT193 Presettable synchronous 4-bit binary up/down counter; separate up/down clocks; TTL-enabled 4.5 to 5.5 ±4.0 TTL 20 50 pF 43 -40 to +125 74HC390 Dual decade ripple counter 2.0 to 6.0 ±5.2 CMOS 14 50 pF 60 -40 to +125 74HCT390 Dual decade ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 18 50 pF 55 -40 to +125 74HC393 Dual 4-bit binary ripple counter 2.0 to 6.0 ±5.2 CMOS 12 50 pF 107 -40 to +125 74HCT393 Dual 4-bit binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 20 50 pF 53 -40 to +125 74HC4017 Johnson decade counter with 10 decoded outputs 2.0 to 6.0 ±5.2 CMOS 18 50 pF 77 -40 to +125 74HCT4017 Johnson decade counter with 10 decoded outputs; TTL-enabled 4.5 to 5.5 ±4.0 TTL 21 50 pF 67 -40 to +125 74HC4020 14-stage binary ripple counter 2.0 to 6.0 ±5.2 CMOS 11 50 pF 52 -40 to +125 74HCT4020 14-stage binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 15 50 pF 52 -40 to +125 74HC4040 12-stage binary ripple counter 2.0 to 6.0 ±5.2 CMOS 14 50 pF 90 -40 to +125 74HCT4040 12-stage binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 16 50 pF 79 -40 to +125 74HC4059 Programmable divide-by-n counter 2.0 to 6.0 ±5.2 CMOS 17 50 pF 43 -40 to +125 74HCT4059 Programmable divide-by-n counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 20 50 pF 40 -40 to +125 74HC4060 14-stage binary ripple counter with oscillator 2.0 to 6.0 ±5.2 CMOS 31 50 pF 95 -40 to +125 74HCT4060 14-stage binary ripple counter with oscillator; TTL-enabled 4.5 to 5.5 ±4.0 TTL 31 50 pF 88 -40 to +125 Type number Description 74HC160 Presettable synchronous BCD decade counter; asynchronous reset 2.0 to 6.0 ±5.2 74HCT160 Presettable synchronous BCD decade counter; asynchronous reset; TTL-enabled 4.5 to 5.5 74HC161 Presettable synchronous 4-bit binary counter; asynchronous reset 74HCT161 VCC (V) Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 76 NXP Logic selection guide 2016 Counters/frequency dividers (cont.) Output Logic drive switching capability levels (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) CMOS 24 50 pF 64 -40 to +125 ±4.0 TTL 24 50 pF 64 -40 to +125 2.0 to 6.0 - 20/ + 25 CMOS 89 50 pF 24 -40 to +125 Programmable delay timer with oscillator; TTL-enabled 4.5 to 5.5 ±20 TTL 75 50 pF 24 -40 to +125 74HC6323 Programmable ripple counter with oscillator (3-state) 2.0 to 6.0 ±7.8 CMOS 17 50 pF 100 -40 to +125 74HCT6323 Programmable ripple counter with oscillator (3-state); TTL-enabled 4.5 to 5.5 ±4.0 TTL 17 50 pF 85 -40 to +125 74HC93 4-bit binary ripple counter 2.0 to 6.0 ±5.2 CMOS 12 50 pF 100 -40 to +125 74HCT93 4-bit binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 15 50 pF 77 -40 to +125 74HC40103 8-bit synchronous binary down counter 2.0 to 6.0 ±5.2 CMOS 15 50 pF 14 -40 to +125 74HC4024 7-stage binary ripple counter 2.0 to 6.0 ±5.2 CMOS 14 50 pF 90 -40 to +125 74HC590 8-bit binary counter with output register (3-state) 2.0 to 6.0 ±5.2 CMOS 19 50 pF 61 -40 to +125 74LV393 Dual 4-bit binary ripple counter 1.0 to 3.6 ±6 TTL 12 50 pF 90 -40 to +125 74LV4020 14-stage binary ripple counter 1.0 to 5.5 ±6 TTL 16 50 pF 100 -40 to +125 74LV4060 14-stage binary ripple counter with oscillator 1.0 to 5.5 ±6 TTL 29 50 pF 100 -40 to +125 74LVC161 Presettable synchronous 4-bit binary counter; asynchronous reset 1.2 to 3.6 ±24 CMOS/ LVTTL 4.9 50 pF 200 -40 to +125 74LVC163 Presettable synchronous 4-bit binary counter; synchronous reset 1.2 to 3.6 ±24 CMOS/ LVTTL 4.9 50 pF 200 -40 to +125 HEF4017 Johnson decade counter with 10 decoded outputs 4.5 to 15 ±2.4 CMOS 40 50 pF 30 -40 to +85 HEF40193 Presettable synchronous 4-bit binary up/down counter; 4.5 to 15.5 separate up/down clocks ±2.4 CMOS 60 50 pF 18 -40 to +85 HEF4020 14-stage binary ripple counter 4.5 to 15.5 ±2.4 CMOS 35 50 pF 35 -40 to +85 HEF4024 7-stage binary ripple counter 4.5 to 15.5 ±2.4 CMOS 30 50 pF 35 -40 to +85 HEF4040 12-stage binary ripple counter 4.5 to 15.5 ±2.4 CMOS 35 50 pF 50 -40 to +85 HEF4059 Programmable divide-by-n counter 4.5 to 15.5 -7/+20 CMOS 40 50 pF 20 -40 to +85 HEF4060 14-stage binary ripple counter with oscillator 4.5 to 15.5 ±2.4 CMOS 50 50 pF 30 -40 to +85 HEF4516 Presettable synchronous 4-bit binary up/down counter 4.5 to 15.5 ±2.4 CMOS 45 50 pF 18 -40 to +85 HEF4518 Dual BCD counter 4.5 to 15 ±2.4 CMOS 40 50 pF 40 -40 to +85 HEF4520 Dual 4-bit synchronous binary counter 4.5 to 15.5 ±2.4 CMOS 15 50 pF 40 -40 to +85 HEF4521 24-stage frequency divider and oscillator 4.5-15.5 V ±2.4 CMOS 220 50 pF 35 -40 to +85 HEF4526 Programmable 4-bit binary down counter 4.5 to 15.5 ±2.4 CMOS 50 50 pF 32 -40 to +85 HEF4541 Programmable timer 4.5 to 15.5 - 4/ + 2.7 CMOS 38 50 pF 150 -40 to +85 Type number Description 74HC4520 Dual 4-bit synchronous binary counter 2.0 to 6.0 ±5.2 74HCT4520 Dual 4-bit synchronous binary counter; TTL-enabled 4.5 to 5.5 74HC5555 Programmable delay timer with oscillator 74HCT5555 VCC (V) Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 77 DECODERS/DEMULTIPLEXERS Features and benefits 4 Multiple input enable for easy expansion, independent controls 4 Integrated input latch for storing decoder-line addresses 4 A synchronous and synchronous load options 4 Can be cascaded 4 High frequency 4 Bus-width reduction 4 Optional overvoltage-tolerant inputs, inverting and noninverting outputs, and 3-stage outputs Applications 4 Selection of memory banks and peripherals 4 I/O expansion 4 Memory addressing in automotive (display clusters, GPS, keyless entry) Decoders demultiplexers (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Tamb (°C) 3-to-8 line decoder/demultiplexer; inverting 2.0 to 5.5 CMOS ±8 4.4 50 pF -40 to +125 74AHCT138 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 to 5.5 TTL ±8 4.4 50 pF -40 to +125 74AHC139 Dual 2-to-4 line decoder/demultiplexer 2.0 to 5.5 CMOS ±8 3.9 50 pF -40 to +125 74AHCT139 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF -40 to +125 74AUP1G18 1-to-2 demultiplexer (3-state) 1.1 to 3.6 CMOS 1.9/-1.9 3.2 30 pF -40 to +125 74AUP1G19 1-to-2 decoder/demultiplexer 1.1 to 3.6 CMOS 1.9/-1.9 3 30 pF -40 to +125 74HC138 3-to-8 line decoder/demultiplexer; inverting 2.0 to 6.0 CMOS ±5.2 12 50 pF -40 to +125 74HCT138 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 to 5.5 TTL ±4 19 50 pF -40 to +125 74HC139 Dual 2-to-4 line decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 14 50 pF -40 to +125 74HCT139 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 16 50 pF -40 to +125 74HC154 4-to-16 line decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 11 50 pF -40 to +125 74HCT154 4-to-16 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 13 50 pF -40 to +125 74HC238 3-to-8 decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 14 50 pF -40 to +125 74HCT238 3-to-8 decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 18 50 pF -40 to +125 74HC42 BCD to decimal decoder (1-of-10) 2.0 to 6.0 CMOS ±5.2 17 50 pF -40 to +125 Type number Description 74AHC138 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 78 NXP Logic selection guide 2016 Decoders demultiplexers (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Tamb (°C) BCD to decimal decoder (1-of-10); TTL-enabled 4.5 to 5.5 TTL ±4 20 50 pF -40 to +125 74HC4511 BCD to 7-segment latch/decoder/driver with lamp test input 2.0 to 6.0 CMOS -10 28 50 pF -40 to +125 74HCT4511 BCD to 7-segment latch/decoder/driver with lamp test input; TTL-enabled 4.5 to 5.5 TTL -10 28 50 pF -40 to +125 74HC4514 4-to-16 decoder/demultiplexer with address latches 2.0 to 6.0 CMOS ±5.2 27 50 pF -40 to +125 74HCT4514 4-to-16 decoder/demultiplexer with address latches; TTL-enabled 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125 74HC4515 4-to-16 decoder/demultiplexer with address latches; inverting 2.0 to 6.0 CMOS ±5.2 29 50 pF -40 to +125 74HCT4515 4-to-16 decoder/demultiplexer with address latches; inverting; TTL-enabled 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125 74HC137 3-to-8 line decoder/demultiplexer with address latches; inverting 2.0 to 6.0 CMOS ±5.2 18 50 pF -40 to +125 74HC237 3-to-8 decoder/demultiplexer with address latches 2.0 to 6.0 CMOS ±5.2 18 50 pF -40 to +125 74LV138 3-to-8 line decoder/demultiplexer; inverting 1.0 to 5.5 TTL ±12 12 50 pF -40 to +125 74LVC138 3-to-8 line decoder/demultiplexer; inverting 1.2 to 3.6 CMOS/ LVTTL ±24 2.7 50 pF -40 to +125 74LV139 Dual 2-to-4 line decoder/demultiplexer 1.0 to 5.5 TTL ±12 11 50 pF -40 to +125 74LVC139 Dual 2-to-4 line decoder/demultiplexer 1.2 to 3.6 CMOS/ LVTTL ±24 2.5 50 pF -40 to +125 74LVC1G18 1-to-2 demultiplexer (3-state) 1.65 to 5.5 CMOS/ LVTTL ±32 2.3 50 pF -40 to +125 HEF4028 1-of-10 decoder 4.5 to 15 CMOS ±2.4 30 50 pF -40 to +85 HEF4511 BCD to 7-segment latch/decoder/driver with lamp test input 4.5 to 15 CMOS -25/2.4 40 50 pF -40 to +85 HEF4514 4-to-16 decoder/demultiplexer with address latches 4.5 to 15 CMOS ±2.4 65 50 pF -40 to +85 HEF4543 BCD to 7-segment latch/decoder/driver with phase input 4.5 to 15 CMOS ±2.4 55 50 pF -40 to +85 HEF4555 Dual 1-to-4 line decoder/demultiplexer 4.5 to 15 CMOS ±2.4 30 50 pF -40 to +85 Type number Description 74HCT42 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 79 DIGITAL COMPARATORS Features and benefits 4 Magnitude comparison of any binary words 4 Serial or parallel expansion without extra gating 4 Low-power CMOS 4 CMOS or TTL inputs Applications 4Process controllers 4Servo-motor control Digital comparators VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Number of bits Tamb (°C) Type number Description 74HC688 8-bit magnitude comparator 2.0 to 6.0 CMOS ±5.2 17 50 pF 8 -40 to +125 74HCT688 8-bit magnitude comparator; TTL-enabled 4.5 to 5.5 TTL ±4.0 17 50 pF 8 -40 to +125 74HC85 4-bit magnitude comparator 2.0 to 6.0 CMOS ±5.2 23 50 pF 4 -40 to +125 74HCT85 4-bit magnitude comparator; TTL-enabled 4.5 to 5.5 TTL ±4.0 26 50 pF 4 -40 to +125 HEF4585 4-bit magnitude comparator 4.5 to 15.5 CMOS ±2.4 65 50 pF 4 -40 to +85 DIGITAL MULTIPLEXERS Features and benefits 4 Mixed 3.3/5 V applications 4 Bus-width reduction 4 High noise immunity 4 Low power consumption 4 Wide range of supply voltages 4 Low propagation delay 4 Optional overvoltage-tolerant inputs, complementary outputs Applications 4Power windows, power locks, power mirror control 4Advanced diagnostics and engine control modules 4Industrial control systems 4Decision-making via voltage sensing in portable electronics 4I/O expansion Digital multiplexers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) Quad 2-input multiplexer 2.0 to 5.5 CMOS ±8 50 pF 3.2 74AHCT157 Quad 2-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3.2 -40 to +125 74AHC257 Quad 2-input multiplexer (3-state) 2.0 to 5.5 CMOS ±8 50 pF 2.9 -40 to +125 74AHCT257 Quad 2-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.7 -40 to +125 74AUP1G157 Single 2-input multiplexer 1.1 to 3.6 CMOS 1.9/-1.9 30 pF 3.2 -40 to +125 74AUP1G158 Single 2-input multiplexer; inverting 1.1 to 3.6 CMOS 1.9/-1.9 30 pF 3.2 -40 to +125 74AUP2G157 Single 2-input multiplexer 1.1 to 3.6 CMOS 1.9/-1.9 30 pF 3.4 -40 to +125 74HC151 8-input multiplexer 2.0 to 6.0 CMOS ±5.2 50 pF 17 -40 to +125 Type number Description 74AHC157 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 80 NXP Logic selection guide 2016 Tamb (°C) Digital multiplexers (cont.) VCC (V) Logic switching levels Output drive capability (mA) Output Load CL (Typ) tpd (ns) Tamb (°C) 8-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 19 -40 to +125 74HC153 Dual 4-input multiplexer 2.0 to 6.0 CMOS ±5.2 50 pF 17 -40 to +125 74HCT153 Dual 4-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 19 -40 to +125 74HC157 Quad 2-input multiplexer 2.0 to 6.0 CMOS ±5.2 50 pF 11 -40 to +125 74HCT157 Quad 2-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 13 -40 to +125 74HC251 8-input multiplexer (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 18 -40 to +125 74HCT251 8-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4 50 pF 22 -40 to +125 74HC253 Dual 4-input multiplexer (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 17 -40 to +125 74HCT253 Dual 4-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 17 -40 to +125 74HC257 Quad 2-input multiplexer (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 11 -40 to +125 74HCT257 Quad 2-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 13 -40 to +125 74HC158 Quad 2-input multiplexer; inverting 2.0 to 6.0 CMOS ±5.2 50 pF 12 -40 to +125 74LV153 Dual 4-input multiplexer 1.0 to 3.6 TTL ±6 50 pF 14 -40 to +125 74LV251 8-input multiplexer (3-state) 1.0 to 3.6 TTL ±6 50 pF 17 -40 to +125 74LVC157 Quad 2-input multiplexer 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2,5 -40 to +125 74LVC1G157 Single 2-input multiplexer 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 2,2 -40 to +125 74LVC257 Quad 2-input multiplexer (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 50 pF 2,4 -40 to +125 Type number Description 74HCT151 ENCODERS Features and benefits 4 Encode 10-line decimal to 4-line BCD 4LED, LCD, incandescent, fluorescent, or gas-discharge displays 4 Standard output capability 4 Applications 410-position switch encoding 4Code converters, generators Encoders Type number Description 74HCT147 10-to-4 line priority encoder; TTL-enabled VCC (V) 4.5 to 5.5 Output Logic drive switching capability levels (mA) TTL ±4 tpd (ns) Number of bits Tamb (°C) Package name 17 10 -40 to +125 SOT109-1 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 81 FIFO REGISTERS Features and benefits 4 Wide range of supply voltages 4 Independent asynchronous and synchronous inputs and outputs 4 Cascadable 4 Optional TTL inputs, 3-state outputs Applications 4 Data buffers FIFO registers Type number Description VCC (V) Output Logic drive switching capability levels (mA) tpd (ns) Output fmax Load (MHz) CL (Typ) Tamb (°C) 74HC40105 4-bit x 16-word FIFO register 2.0 to 6.0 CMOS Low 15 50 pF 30 -40 to +125 74HCT40105 4-bit x 16-word FIFO register; TTL-enabled 4.5 to 5.5 TTL ±4 mA 18 50 pF 28 -40 to +125 74HC7030 9-bit x 64-word FIFO register (3-state) 2.0 to 6.0 CMOS ±5.2 mA 36 50 pF 33 -40 to +125 74HCT7030 9-bit x 64-word FIFO register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4 mA 26 50 pF 29 -40 to +125 74HC7403 4-bit x 16-word FIFO register (3-state) 2.0 to 6.0 CMOS ±5.2 mA 15 50 pF 30 -40 to +125 74HCT7403 4-bit x 16-word FIFO register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 mA 17 50 pF 30 -40 to +125 FLIP-FLOPS Features and benefits 4 Mixed 3.3/5 V applications 4Improved signal integrity with integrated termination resistors 4 Flow-through pinout for easy layout 4 Wide range of supply voltage 4 Low propagation delay 4 Optional overvoltage-tolerant inputs, integrated sourcetermination resistors, bus hold Applications 4 Frequency division 4 Controlled delays 4 Interface between asynchronous and synchronous systems Flip-flops (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) Type number Description 74AHC1G79 Single D-type flip-flop; positive-edge trigger 2.0 to 5.5 CMOS ±8 3,5 50 pF 90 -40 to +125 74AHCT1G79 Single D-type flip-flop; positive-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±8 3,5 50 pF 90 -40 to +125 74AHC273 Octal D-type flip-flop with reset; positive-edge trigger 2.0 to 5.5 CMOS ±8 4,2 50 pF 165 -40 to +125 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4 50 pF 120 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 82 NXP Logic selection guide 2016 Flip-flops (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) Type number Description 74AHC374 Octal D-type flip-flop; positive-edge trigger (3-state) 2.0 to 5.5 CMOS ±8 4,4 50 pF 185 -40 to +125 74AHCT374 Octal D-type flip-flop; positive-edge trigger (3-state) 4.5 to 5.5 TTL ±8 4,3 50 pF 140 -40 to +125 74AHC377 Octal D-type flip-flop with data enable; positiveedge trigger 2.0 to 5.5 CMOS ±8 3,9 50 pF 175 -40 to +125 74AHCT377 Octal D-type flip-flop with data enable; positiveedge trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4 50 pF 140 -40 to +125 74AHC574 Octal D-type flip-flop; positive-edge trigger (3-state) 2.0 to 5.5 CMOS ±8 4,4 50 pF 130 -40 to +125 74AHCT574 Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 4,4 50 pF 130 -40 to +125 74AHC74 Dual D-type flip-flop with set and reset; positiveedge trigger 2.0 to 5.5 CMOS ±8 3,7 50 pF 170 -40 to +125 74AHCT74 Dual D-type flip-flop with set and reset; positiveedge trigger; TTL-enabled 4.5 to 5.5 TTL ±8 3,3 50 pF 160 -40 to +125 74ALVC374 Octal D-type flip-flop; positive-edge trigger (3-state) 1.65 to 3.6 TTL ±24 2,5 50 pF 300 -40 to +85 74ALVC574 Octal D-type flip-flop; positive-edge trigger (3-state) 1.65 to 3.6 TTL ±24 2,5 50 pF 300 -40 to +85 74ALVC74 Dual D-type flip-flop with set and reset; positiveedge trigger 1.65 to 3.6 TTL ±24 2,3 50 pF 425 -40 to +85 74ALVCH16374 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 1.2 to 3.6 TTL ±24 2,3 50 pF 350 -40 to +85 74ALVCH16821 20-bit D-type flip-flop; positive-edge trigger (3-state) 2.3 to 3.6 TTL ±24 2,5 50 pF 350 -40 to +85 74ALVCH16823 18-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 1.2 to 3.6 TTL ±24 2,1 50 pF 350 -40 to +85 74ALVT162821 20-bit D-type flip-flop; positive-edge trigger (3-state) 2.3 to 3.6 TTL ±12 3,2 50 pF 150 -40 to +85 74ALVT162823 18-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 TTL ±12 3 50 pF 150 -40 to +85 74ALVT16374 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 2.3 to 3.6 TTL -32/+64 2,3 50 pF 250 -40 to +85 74ALVT16821 20-bit D-type flip-flop; positive-edge trigger (3-state) 2.3 to 3.6 TTL -32/+64 1,8 50 pF 150 -40 to +85 74ALVT16823 18-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 2.3 to 3.6 TTL -32/+64 1,9 50 pF 250 -40 to +85 74AUP1G175 Single D flip-flop with reset; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 7,4 30 pF 70 -40 to +125 74AUP1G374 Single D-type flip-flop; positive-edge trigger (3-state) 1.1 to 3.6 CMOS ±1.9 7,9 30 pF 400 -40 to +125 74AUP1G74 Single D-type flip-flop with set and reset; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,2 30 pF 400 -40 to +125 74AUP1G79 Single D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125 74AUP1G80 Single D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125 74AUP2G79 Dual D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 8,5 30 pF 400 -40 to +125 74AUP2G80 Dual D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125 74AVC16374 16-bit D-type flip-flop; positive-edge trigger (3-state) 1.2 to 3.6 CMOS ±12 1,5 30 pF 350 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 83 Flip-flops (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) Type number Description 74HC107 Dual JK-type flip-flop with reset; negative-edge trigger 2.0 to 6.0 CMOS ±5.2 16 50 pF 78 -40 to +125 74HCT107 Dual JK-type flip-flop with reset; negative-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±4 16 50 pF 73 -40 to +125 74HC109 Dual JK-type flip-flop with set and reset; positive-edge trigger 2.0 to 6.0 CMOS ±5.2 15 50 pF 75 -40 to +125 74HCT109 Dual JK-type flip-flop with set and reset; positive-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±4 17 50 pF 61 -40 to +125 74HC112 Dual JK-type flip-flop with set and reset; negative-edge trigger 2.0 to 6.0 CMOS ±5.2 15 50 pF 66 -40 to +125 74HCT112 Dual JK-type flip-flop with set and reset; negative-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±4 19 50 pF 70 -40 to +125 74HC173 Quad D-type flip-flop; positive-edge trigger (3-state) 2.0 to 6.0 CMOS ±7.8 17 50 pF 88 -40 to +125 74HCT173 Quad D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 17 50 pF 88 -40 to +125 74HC174 Hex D-type flip-flop with reset; positive-edge trigger 2.0 to 6.0 CMOS ±5.2 17 50 pF 99 -40 to +125 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±4 18 50 pF 69 -40 to +125 74HC175 Quad D-type flip-flop with reset; positive-edge trigger 2.0 to 6.0 CMOS ±5.2 17 50 pF 83 -40 to +125 74HCT175 Quad D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±4 16 50 pF 54 -40 to +125 74HC273 Octal D-type flip-flop with reset; positive-edge trigger 2.0 to 6.0 CMOS ±5.2 15 50 pF 122 -40 to +125 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±4 15 50 pF 36 -40 to +125 74HC374 Octal D-type flip-flop; positive-edge trigger (3-state) 2.0 to 6.0 CMOS ±7.8 14 50 pF 83 -40 to +125 74HCT374 Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 13 50 pF 48 -40 to +125 74HC377 Octal D-type flip-flop with data enable; positiveedge trigger 2.0 to 6.0 CMOS ±7.8 13 50 pF 83 -40 to +125 74HCT377 Octal D-type flip-flop with data enable; positiveedge trigger; TTL-enabled 4.5 to 5.5 TTL ±6 14 50 pF 53 -40 to +125 74HC574 Octal D-type flip-flop; positive-edge trigger (3-state) 2.0 to 6.0 CMOS ±7.8 14 50 pF 133 -40 to +125 74HCT574 Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 15 50 pF 76 -40 to +125 74HC74 Dual D-type flip-flop with set and reset; positiveedge trigger 2.0 to 6.0 CMOS ±5.2 14 50 pF 82 -40 to +125 74HCT74 Dual D-type flip-flop with set and reset; positiveedge trigger; TTL-enabled 4.5 to 5.5 TTL ±4 15 50 pF 59 -40 to +125 74HC73 Dual JK-type flip-flop with reset; negative-edge trigger 2.0 to 6.0 CMOS ±5.2 16 50 pF 77 -40 to +125 74HCT534 Octal D-type flip-flop; inverting; positive-edge trigger; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 13 50 pF 40 -40 to +125 74HCT7273 Octal D-type flip-flop with reset; positive edgetrigger; open drain outputs; TTL-enabled 4.5 to 5.5 TTL 4 16 50 pF 56 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 84 NXP Logic selection guide 2016 Flip-flops (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) Type number Description 74LV174 Hex D-type flip-flop with reset; positive-edge trigger 1.0 to 5.5 TTL ±12 16 50 pF 77 -40 to +125 74LV273 Octal D-type flip-flop with reset; positive-edge trigger 1.0 to 5.5 TTL ±12 12 50 pF 110 -40 to +125 74LV374 Octal D-type flip-flop; positive-edge trigger (3-state) 1.0 to 5.5 TTL ±16 14 50 pF 77 -40 to +125 74LV377 Octal D-type flip-flop with data enable; positiveedge trigger 1.0 to 3.6 TTL ±6 13 50 pF 77 -40 to +125 74LV574 Octal D-type flip-flop; positive-edge trigger (3-state) 1.0 to 5.5 TTL ±16 13 50 pF 77 -40 to +125 74LV74 Dual D-type flip-flop with set and reset; positiveedge trigger 1.0 to 5.5 TTL ±12 11 50 pF 75 -40 to +125 74LVC16374 16-bit D-type flip-flop; positive-edge trigger (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3,8 50 pF 150 -40 to +125 74LVCH16374 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3,8 50 pF 150 -40 to +125 74LVC109 Dual JK-type flip-flop with set and reset; positive-edge trigger 1.2 to 3.6 CMOS/ LVTTL ±24 4 50 pF 330 -40 to +125 74LVC1G175 Single D flip-flop with reset; positive-edge trigger 1.65 to 5.5 CMOS/ LVTTL ±32 3,1 50 pF 300 -40 to +125 74LVC1G74 Single D-type flip-flop with set and reset; positive-edge trigger 1.65 to 5.5 CMOS/ LVTTL ±32 3,5 50 pF 280 -40 to +125 74LVC1G79 Single D-type flip-flop; positive-edge trigger 1.65 to 5.5 CMOS/ LVTTL ±32 2,2 50 pF 450 -40 to +125 74LVC1G80 Single D-type flip-flop; positive-edge trigger 1.65 to 5.5 CMOS/ LVTTL ±32 2,4 50 pF 450 -40 to +125 74LVC273 Octal D-type flip-flop with reset; positive-edge trigger 1.2 to 3.6 CMOS/ LVTTL ±24 6 50 pF 230 -40 to +125 74LVC2G74 Single D-type flip-flop with set and reset; positive-edge trigger 1.65 to 5.5 CMOS/ LVTTL ±32 3,5 50 pF 280 -40 to +125 74LVC374 Octal D-type flip-flop; positive-edge trigger (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 2,7 50 pF 100 -40 to +125 74LVC377 Octal D-type flip-flop with data enable; positiveedge trigger 1.2 to 3.6 CMOS/ LVTTL ±24 6 50 pF 230 -40 to +125 74LVC574 Octal D-type flip-flop; positive-edge trigger (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3,2 50 pF 150 -40 to +125 74LVC74 Dual D-type flip-flop with set and reset; positiveedge trigger 1.2 to 3.6 CMOS/ LVTTL ±24 2,5 50 pF 250 -40 to +125 74LVC821 10-bit D-type flip-flop; positive-edge trigger (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 5,4 50 pF 150 -40 to +125 74LVC823 9-bit D-type flip-flop; positive-edge trigger (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 5,4 50 pF 150 -40 to +125 1.2 to 3.6 CMOS/ LVTTL ±24 3,8 50 pF 150 -40 to +125 16-bit D-type flip-flop with bus hold and 74LVCH162374 30 Ω termination resistors; positive-edge trigger (3-state) 74LVCH32374 32-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3,8 50 pF 150 -40 to +125 74LVT16374 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85 74LVTH16374 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 85 Flip-flops (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) Type number Description 74LVT574 Octal D-type flip-flop; positive-edge trigger (3-state) 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85 74LVTH57 Octal D-type flip-flop; positive-edge trigger (3-state) 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85 74LVTH574 Octal D-type flip-flop; positive-edge trigger (3-state) 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85 74LVT162374 16-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) 2.7 to 3.6 TTL ±12 3 50 pF 150 -40 to +85 74LVT273 Octal D-type flip-flop with reset; positive-edge trigger 2.7 to 3.6 TTL -32/+64 3,5 50 pF 150 -40 to +85 74LVT32374 32-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85 74LVT373 Octal D-type transparent latch (3-state) 2.7 to 3.6 TTL -32/+64 3 50 pF 74LVT374 Octal D-type flip-flop; positive-edge trigger (3-state) 2.7 to 3.6 TTL -32/+64 3,5 50 pF 200 -40 to +85 74LVT534 Octal D-type flip-flop; inverting; positive-edge trigger (3-state) 2.7 to 3.6 TTL -32/+64 3,5 50 pF 150 -40 to +85 74LVT74 Dual D-type flip-flop with set and reset; positiveedge trigger 2.7 to 3.6 TTL -20/+32 3,6 50 pF 345 -40 to +85 HEF4013 Dual D-type flip-flop with set and reset; positiveedge trigger 4.5 to 15.5 CMOS ±2.4 30 50 pF 40 -40 to +85 HEF40174 Hex D-type flip-flop with reset; positive-edge trigger 4.5 to 15.5 CMOS ±2.4 20 50 pF 45 -40 to +85 HEF40175 Quad D-type flip-flop with reset; positive-edge trigger 4.5 to 15.5 CMOS ±2.4 25 50 pF 45 -40 to +85 HEF4027 Dual JK-type flip-flop 4.5 to 15.5 CMOS ±2.4 30 50 pF 30 -40 to +85 HEF40374 Octal D-type flip-flop; positive-edge trigger (3-state) 4.5 to 15.5 CMOS -50/+62 40 50 pF 17 -40 to +85 -40 to +85 FULL ADDERS Features and benefits 4 Cascadable 4 Low power dissipation 4 Positive or negative logic 4 Wide range of supply voltages Applications 4 High-speed 4-bit binary addition Full adders Type number Description 74HC283 4-bit binary full adder with fast carry VCC (V) Logic switching levels Output drive capability (mA) 2.0 to 6.0 CMOS ±5.2 tpd (ns) Output drive capability (mA) Number of bits Tamb (°C) 21 50 pF 4 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 86 NXP Logic selection guide 2016 GATES This section includes AND gates, combination gates (one package, two or more different functions), configurable multi-function gates (one package, nine or more functions), EXCLUSIVE-NOR gates, EXCLUSIVE-OR gates, NOR gates, and OR gates. Features and benefits 4 Mixed 3.3/5 V applications 4 Reduced time-to-market for complex designs 4 Reduced board space 4 Improved signal integrity in complex layouts 4 Wide range of supply voltages 4 Low propagation delay 4 Low-power CMOS 4 Optional overvoltage-tolerant inputs, low input threshold 4 Comprehensive range: AND, EXCLUSIVE-NOR, EXCLUSIVE-OR, NAND, NOR, OR 4 Combination gates and configurable multi-function gates for lower pincount, device count, system cost, assemblyrelated expenses Applications 4 Control/glue logic 4PCB miniaturization 4Routing simplification 4Discrete replacement Gates - AND (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Quad 2-input AND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 -40 to +125 74AHC1G08 Single 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 74AHC1G09 Single 2-input AND gate; open drain 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 74AHC2G08 Dual 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 2 -40 to +125 4.5 to 5.5 TTL ±8 5 50 pF 60 4 -40 to +125 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125 4.5 to 5.5 TTL ±8 3.6 50 pF 60 2 -40 to +125 Type number Description 74AHC08 74AHCT08 74AHCT1G08 74AHCT2G08 Quad 2-input AND gate; TTL-enabled Single 2-input AND gate; TTL-enabled Dual 2-Input AND gate; TTL-enabled 74ALVC08 Quad 2-input AND gate 1.65 to 3.6 TTL ±24 2 50 pF 145 4 -40 to +85 74AUP1G08 Single 2-input AND gate 1.1 to 3.6 CMOS ±1.9 8.2 30 pF 70 1 -40 to +125 74AUP1G09 Single 2-input AND gate; open drain 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 1 -40 to +125 74AUP1G11 Single 3-input AND gate 1.1 to 3.6 CMOS ±1.9 6.9 30 pF 70 1 -40 to +125 74AUP2G08 Dual 2-input AND gate 1.1 to 3.6 CMOS ±1.9 8.2 30 pF 70 2 -40 to +125 74AXP1G08 Single 2-input AND gate 0.7 to 2.75 CMOS ±4.5 2.6 5pF 70 1 -40 to +85 74HC08 Quad 2-input AND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125 74HC11 Triple 3-input AND gate 2.0 to 6.0 CMOS ±5.2 10 50 pF 36 3 -40 to +125 74HC1G08 Single 2-input AND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 1 -40 to +125 74HC21 Dual 4-input AND gate 2.0 to 6.0 CMOS ±5.2 10 50 pF 36 2 -40 to +125 74HC2G08 Dual 2-input AND gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125 74HCT08 Quad 2-input AND gate; TTL-enabled 4.5 to 5.5 TTL ±4 11 50 pF 36 4 -40 to +125 74HCT11 Triple 3-input AND gate 4.5 to 5.5 TTL ±4 11 50 pF 36 3 -40 to +125 4.5 to 5.5 TTL ±2 11 50 pF 36 1 -40 to +125 4.5 to 5.5 TTL ±2 11 50 pF 36 1 -40 to +125 74HCT1G08 74HCT1G08 Single 2-input AND gate; TTL-enabled Single 2-input AND gate; TTL-enabled Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 87 Gates - AND (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Dual 2-Input AND gate; TTL-enabled 4.5 to 5.5 TTL ±4 14 50 pF 36 2 -40 to +125 74LV08 Quad 2-input AND gate 1.0 to 5.5 TTL ±12 7 50 pF 30 4 -40 to +125 74LVC08 Quad 2-input AND gate 1.2 to 3.6 TTL ±24 2.1 50 pF 150 4 -40 to +125 74LVC11 Triple 3-input AND gate 1.2 to 3.6 TTL ±24 3.7 50 pF 150 3 -40 to +125 ±24 2.1 50 pF 150 1 -40 to +125 ±24 2.6 50 pF 150 1 -40 to +125 ±24 2.1 50 pF 150 2 -40 to +125 Type number Description 74HCT2G08 CMOS / LVTTL CMOS / LVTTL CMOS / LVTTL 74LVC1G08 Single 2-input AND gate 1.65 to 5.5 74LVC1G11 Single 3-input AND gate 1.65 to 5.5 74LVC2G08 Dual 2-input AND gate 1.65 to 5.5 74LVT08 Quad 2-input AND gate 2.7 to 3.6 TTL -32/+64 3.4 50 pF 150 4 -40 to +85 74VHC08 Quad 2-input AND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 -40 to +125 74VHCT08 Quad 2-input AND gate; TTL-enabled 4.5 to 5.5 TTL ±8 5 50 pF 60 4 -40 to +125 HEF4073 Triple 3-input AND gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 3 -40 to +85 HEF4081 Quad 2-input AND gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85 HEF4082 Dual 4-input AND gate 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 2 -40 to +85 XC7SET08 Single 2-input AND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125 XC7SH08 Single 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 Gates - Combination VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Type number Description 74AUP1G0832 Single 3-input AND-OR gate 1.1 to 3.6 CMOS ±1.9 6.7 30 pF 70 1 -40 to +125 74AUP1G3208 Single 3-input OR-AND gate 1.1 to 3.6 CMOS ±1.9 7.4 30 pF 70 1 -40 to +125 74AUP1G885 Dual function gate 1.1 to 3.6 CMOS ±1.9 7.6 30 pF 70 1 -40 to +125 1.1 to 3.6 CMOS ±1.9 5.6 30 pF 70 1 -40 to +125 1.1 to 3.6 CMOS ±1.9 4.7 30 pF 70 1 -40 to +125 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 2 -40 to +125 74AUP1Z04 74AUP1Z125 74AUP2G0604 Crystal driver with enable and internal resistor Crystal driver with enable and internal resistor (3-state) Inverter with open drain and inverter 74AUP2G3404 Buffer and inverter 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 2 -40 to +125 74AUP2G3407 Buffer and buffer with open drain 1.1 to 3.6 CMOS ±1.9 4.1 30 pF 70 2 -40 to +125 74AUP2T1326 Dual supply buffer/line driver; 3-state 1.1 to 3.6 CMOS ±1.9 3.8 30 pF 70 2 -40 to +125 74AUP3G0434 Dual inverter and single buffer 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 3 -40 to +125 74AUP3G3404 Dual buffer and single inverter 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 3 -40 to +125 74HC58 Dual AND-OR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125 74LVC1GX04 Crystal driver 1.65 to 5.5 CMOS / LVTTL ±24 2.8 50 pF 150 1 -40 to +125 HEF4000 Dual 3-input NOR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 2 -40 to +85 HEF4007 Dual complementary pair and inverter 4.5 to 15.5 CMOS ±3.4 15 50 pF 10 2 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 88 NXP Logic selection guide 2016 Gates - Configurable VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Type number Description 74AUP1G57 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125 74AUP1G58 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125 74AUP1G97 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125 74AUP1G98 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.9 30 pF 70 1 -40 to +125 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125 74AUP1T57 74AUP1T58 74AUP1T97 74AUP1T98 Configurable gate with voltagelevel translation Configurable gate with voltagelevel translation Configurable gate with voltagelevel translation Configurable gate with voltagelevel translation 74AXP1G57 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.6 5pF 70 1 -40 to +85 74AXP1G58 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85 74AXP1G97 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85 74AXP1G98 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85 74LVC1G57 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125 74LVC1G58 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125 74LVC1G97 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125 74LVC1G98 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125 74LVC1G99 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 8.4 50 pF 150 1 -40 to +125 Gates - EXCLUSIVE-NOR VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Tamb (°C) Quad 2-input EXCLUSIVE-NOR gate 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 -40 to +125 Quad 2-input EXCLUSIVE-NOR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 -40 to +85 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Type number Description 74HC7266 HEF4077 Gates - EXCLUSIVE-OR (cont.) Type number Description 74AHC1G86 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3.4 50 pF 60 1 -40 to +125 74AHCT1G86 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125 74AHC86 Quad 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3.4 50 pF 60 4 -40 to +125 74AHCT86 Quad 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.4 50 pF 60 4 -40 to +125 74AUP1G386 Single 3-input EXCLUSIVE-OR gate 1.1 to 3.6 CMOS 1.9/-1.9 8.6 30 pF 70 1 -40 to +125 74AUP2G86 Dual 2-input EXCLUSIVE-OR gate 1.1 to 3.6 CMOS 1.9/-1.9 9 30 pF 70 2 -40 to +125 74HC1G86 Single 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±2.6 9 50 pF 36 1 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 89 Gates - EXCLUSIVE-OR (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Single 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±2.0 10 50 pF 36 1 -40 to +125 74HC2G86 Dual 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±4.0 11 50 pF 36 2 -40 to +125 74HC86 Quad 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 4 -40 to +125 74HCT86 Quad 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±4 14 50 pF 36 4 -40 to +125 74LV86 Quad 2-input EXCLUSIVE-OR gate 1.0 to 5.5 TTL ±12 11 50 pF 30 4 -40 to +125 74LVC1G386 Single 3-Input EXCLUSIVE-OR gate 1.65 to 5.5 ±32 4.5 50 pF 150 1 -40 to +125 74LVC1G86 Single 2-input EXCLUSIVE-OR gate 1.65 to 5.5 ±32 2.4 50 pF 150 1 -40 to +125 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 1.65 to 5.5 ±32 2.3 50 pF 150 2 -40 to +125 74LVC86 Quad 2-input EXCLUSIVE-OR gate 1.2 to 3.6 ±24 3 50 pF 150 4 -40 to +125 HEF4030 Quad 2-input EXCLUSIVE-OR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +85 HEF4070 Quad 2-input EXCLUSIVE-OR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +85 XC7SET86 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125 XC7SH86 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3,4 50 pF 60 1 -40 to +125 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Type number Description 74HCT1G86 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL Gates - NAND (cont.) Type number Description 74AHC00 Quad 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 4 -40 to +125 74AHCT00 Quad 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.3 50 pF 60 4 -40 to +125 74AHC1G00 Single 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 1 -40 to +125 74AHCT1G00 Single 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125 74AHC2G00 Dual 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 2 -40 to +125 74AHCT2G00 Dual 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF 60 2 -40 to +125 74AHC30 8-input NAND gate 2.0 to 5.5 CMOS ±8 3.6 50 pF 60 1 -40 to +125 74AHCT30 8-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 -40 to +125 74ALVC00 Quad 2-input NAND gate 1.65-3.6 TTL ±24 2.1 50 pF 145 4 -40 to +85 74AUP1G00 Single 2-input NAND gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 1 -40 to +125 1.1 to 3.6 CMOS 1.9/-1.9 10 30 pF 70 1 -40 to +125 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 1 -40 to +125 74AUP1G132 74AUP1G38 Single 2-input NAND gate Schmitt trigger Single 2-input NAND gate; open drain 74AUP2G00 Dual 2-input NAND gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 2 -40 to +125 74AUP2G38 Dual 2-input NAND gate; open drain 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 2 -40 to +125 74HC00 Quad 2-input NAND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125 74HCT00 Quad 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 10 50 pF 36 4 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 90 NXP Logic selection guide 2016 Gates - NAND (cont.) Type number 74HC03 74HCT03 Description Quad 2-input NAND gate; open drain Quad 2-input NAND gate; open drain; TTL-enabled VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) 2.0 to 6.0 CMOS 5,2 8 50 pF 36 4 -40 to +125 4.5 to 5.5 TTL ±4 10 50 pF 36 4 -40 to +125 74HC10 Triple 3-input NAND gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 3 -40 to +125 74HCT10 Triple 3-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 11 50 pF 36 3 -40 to +125 74HC1G00 Single 2-input NAND gate 2.0 to 6.0 CMOS ±2.6 7 50 pF 36 1 -40 to +125 74HCT1G00 Single 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±2 10 50 pF 36 1 -40 to +125 74HC20 Dual 4-input NAND gate 2.0 to 6.0 CMOS ±5.2 8 50 pF 36 2 -40 to +125 74HCT20 Dual 4-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 13 50 pF 36 2 -40 to +125 74HC2G00 Dual 2-input NAND gate 2.0 to 6.0 CMOS ±5.6 9 50 pF 36 2 -40 to +125 74HCT2G00 Dual 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 12 50 pF 36 2 -40 to +125 74HC30 8-input NAND gate 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 1 -40 to +125 74HCT30 8-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 12 50 pF 36 1 -40 to +125 74LV00 Quad 2-input NAND gate 1.0 to 5.5 TTL ±12 7 50 pF 30 4 -40 to +125 74LV03 Quad 2-input NAND gate; open drain 1.0 to 5.5 TTL ±12 8 50 pF 30 4 -40 to +125 74LVC00 Quad 2-input NAND gate 1.2 to 3.6 ±24 2.1 50 pF 150 4 -40 to +125 74LVC10 Triple 3-input NAND gate 1.2 to 3.6 ±24 3.9 50 pF 150 3 -40 to +125 74LVC1G00 Single 2-input NAND gate 1.65 to 5.5 ±32 2.2 50 pF 175 1 -40 to +125 74LVC1G10 Single 3-input NAND gate 1.65 to 5.5 ±32 2.6 50 pF 175 1 -40 to +125 74LVC1G38 Single 2-input NAND gate; open drain 1.65 to 5.5 32 2.3 50 pF 175 1 -40 to +125 74LVC2G00 Dual 2-input NAND gate 1.65 to 5.5 ±32 2.2 50 pF 175 2 -40 to +125 74LVC2G38 Dual 2-input NAND gate; open drain 1.65 to 5.5 32 2.1 50 pF 175 2 -40 to +125 74LVC30 8-input NAND gate 1.65 to 5.6 24 3.6 50 pF 175 1 -40 to +125 74LVC38 Quad 2-input NAND gate; open drain 1.2 to 3.6 24 2.2 50 pF 175 4 -40 to +125 74LVT00 Quad 2-input NAND gate 2.7 to 3.6 TTL -32/+64 2.7 50 pF 150 4 -40 to +85 74LVT10 Triple 3-input NAND gate 2.7 to 3.6 TTL -32/+64 3.8 50 pF 150 3 -40 to +85 HEF4011 Quad 2-input NAND gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85 HEF4023 Triple 3-input NAND gate 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 3 -40 to +85 HEF4068 8-input NAND gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 1 -40 to +85 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 91 Gates - NOR VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) Quad 2-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.8 50 pF 60 4 -40 to +125 74AHC1G02 Single 2-input NOR gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 74AHCT1G02 Single 2-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125 74ALVC02 Quad 2-input NOR gate 1.65 to 3.6 TTL ±24 2.2 50 pF 150 4 -40 to +85 74AUP1G02 Single 2-input NOR gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 1 -40 to +125 74AUP2G02 Dual 2-input NOR gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 2 -40 to +125 74HC02 Quad 2-input NOR gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125 74HCT02 Quad 2-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±4 9 50 pF 36 4 -40 to +125 74HC1G02 Single 2-input NOR gate 2.0 to 6.0 CMOS ±2.6 7 50 pF 36 1 -40 to +125 74HCT1G02 Single 2-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±2.0 9 50 pF 36 1 -40 to +125 74HC27 Triple 3-input NOR gate 2.0 to 6.0 CMOS ±5.2 8 50 pF 36 3 -40 to +125 74HCT27 Triple 3-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±4 10 50 pF 36 3 -40 to +125 74HC2G02 Dual 2-input NOR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125 74HCT2G02 Dual 2-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±4 12 50 pF 36 2 -40 to +125 74HC4002 Dual 4-input NOR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125 4.5 to 5.5 TTL ±4 11 50 pF 36 2 -40 to +125 4.5 to 5.5 TTL ±4 12 50 pF 36 2 -40 to +125 Type number Description 74AHCT02 74HCT4002 74HCT2G02 Dual 4-input NOR gate; TTL-enabled Dual 2-input NOR gate; TTL-enabled 74LV02 Quad 2-input NOR gate 1.0 to 5.5 TTL ±12 6 50 pF 30 4 -40 to +125 74LV27 Triple 3-input NOR gate 1.0 to 5.5 TTL ±12 8 50 pF 30 3 -40 to +125 74LVC02 Quad 2-input NOR gate 1.2 to 3.6 TTL ±24 2.1 50 pF 150 4 -40 to +125 74LVC1G02 Single 2-input NOR gate 1.65 to 5.5 ±32 2.1 50 pF 150 1 -40 to +125 74LVC1G27 Single 3-input NOR gate 1.65 to 5.5 ±32 2.6 50 pF 150 1 -40 to +125 74LVC27 Triple 3-input NOR gate 1.2 to 3.6 TTL ±24 3.4 50 pF 150 3 -40 to +125 74LVC2G02 Dual 2-input NOR gate 1.65 to 5.5 CMOS/ LVTTL ±32 2.4 50 pF 150 2 -40 to +125 74LVT02 Quad 2-input NOR gate 2.7 to 3.6 TTL -32/+64 2.8 50 pF 4 -40 to +85 74VHC02 Quad 2-input NOR gate 2.0 to 5.5 CMOS ±8 2.9 50 pF 60 4 -40 to +125 74VHCT02 Quad 2-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.8 50 pF 60 4 -40 to +125 HEF4001 Quad 2-input NOR gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85 HEF4002 Dual 4-input NOR gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85 HEF4025 Triple 3-input NOR gate 4.5 to 15.5 CMOS ±2.4 40 50 pF 10 3 -40 to +85 XC7SET02 Single 2-input NOR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125 XC7SH02 Single 2-input NOR gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 CMOS/ LVTTL CMOS/ LVTTL Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 92 NXP Logic selection guide 2016 Gates - OR (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Power dissipation considerations Tamb (°C) Type number Description 74AHC1G32 Single 2-input OR gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 low -40 to +125 74AHCT1G32 Single 2-input OR gate 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 low -40 to +125 74AHC2G32 Dual 2-input OR gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 2 low -40 to +125 74AHCT2G32 Dual 2-input OR gate 4.5 to 5.5 TTL ±8 3.3 50 pF 60 2 low -40 to +125 74AHC32 Quad 2-input OR gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 low -40 to +125 74AHCT32 Quad 2-input OR gate; TTL-enabled 4.5 to 5.5 TTL ±8 5 50 pF 60 4 low -40 to +125 74ALVC32 Quad 2-input OR gate 1.65 to 3.6 TTL ±24 2 50 pF 150 4 low -40 to +125 74AUP1G32 Single 2-input OR gate 1.1 to 3.6 CMOS 1.9/-1.9 7.9 30 pF 70 1 ultra low -40 to +125 74AUP1G332 Single 3-input OR gate 1.1 to 3.6 CMOS 1.9/-1.9 6.8 30 pF 70 1 ultra low -40 to +125 74AUP2G32 Dual 2-input OR gate 1.1 to 3.6 CMOS 1.9/-1.9 7.9 30 pF 70 2 ultra low -40 to +125 74HC1G32 Single 2-input OR gate 2.0 to 6.0 CMOS ±2.6 8 50 pF 36 1 low -40 to +125 74HCT1G32 Single 2-input OR gate; TTL-enabled 4.5 to 5.5 TTL ±2.0 10 50 pF 36 1 low -40 to +125 74HC2G32 Dual 2-input OR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 low -40 to +125 74HCT2G32 Dual 2-input OR gate; TTL-enabled 4.5 to 5.5 TTL ±4.0 13 50 pF 36 2 low -40 to +125 74HC32 Quad 2-input OR gate 2.0 to 6.0 CMOS ±5.2 6 50 pF 36 4 low -40 to +125 74HCT32 Quad 2-input OR gate 4.5 to 5.5 TTL ±4.0 9 50 pF 36 4 low -40 to +125 74HC4075 Triple 3-input OR gate 2.0 to 6.0 CMOS ±5.2 8 50 pF 36 3 low -40 to +125 74HCT4075 Triple 3-input OR gate; TTL-enabled 4.5 to 5.5 TTL ±4 10 50 pF 36 3 low -40 to +125 74LV32 Quad 2-input OR gate 1.0 to 5.5 TTL ±12 6 50 pF 30 4 low -40 to +125 74LVC1G32 Single 2-input OR gate 1.65 to 5.5 CMOS/ LVTTL ±32 2.1 50 pF 150 1 low -40 to +125 74LVC1G332 Single 3-input OR gate 1.65 to 5.5 CMOS/ LVTTL ±32 50 pF 150 1 low -40 to +125 74LVC2G32 Dual 2-input OR gate 1.65 to 5.5 CMOS/ LVTTL ±32 2.2 50 pF 150 2 low -40 to +125 74LVC32 Quad 2-input OR gate 1.2 to 3.6 CMOS/ LVTTL ±24 2.1 50 pF 150 4 low -40 to +125 74LVC332 Triple 3-input OR gate 1.2 to 3.6 CMOS/ LVTTL ±24 2.4 50 pF 150 3 low -40 to +125 74LVT32 Quad 2-input OR gate 2.7 to 3.6 TTL -20/+32 3.2 50 pF 4 medium -40 to +125 74VHC32 Quad 2-input OR gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 low -40 to +125 74VHCT32 Quad 2-input OR gate; TTL-enabled 4.5 to 5.5 TTL ±8 5 50 pF 60 4 low -40 to +125 HEF4071 Quad 2-input OR gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 low -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 93 Gates - OR (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Power dissipation considerations Tamb (°C) Type number Description HEF4072 Dual 4-input OR gate 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 2 low -40 to +85 HEF4075 Triple 3-input OR gate 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 3 low -40 to +85 XC7SET32 Single 2-input OR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 low -40 to +125 XC7SH32 Single 2-input OR gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 low -40 to +125 LATCHES / REGISTERED DRIVERS Features and benefits 4Low propagation delay 4 Improved synchronous operation, with reduced signal loads, elimination of timing delays and waveform distortion 4Mixed 3.3/5 V applications 4 Reduced board space 4 Low-cost interface solutions 4 Improved signal integrity in complex layouts 4 Wide range of supply voltages 4 Low-power CMOS 4 Optional overvoltage-tolerant inputs, source termination, low input threshold Applications 4 Memory controllers 4 Backplane interfaces Latches-registered drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Number of bits Tamb (°C) 8-bit addressable latch 2.0 to 5.5 CMOS ±8 4.1 50 pF 8 -40 to +125 74AHCT259 8-bit addressable latch; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 8 -40 to +125 74AHC373 Octal D-type transparent latch (3-state) 2.0 to 5.5 CMOS ±8 4.3 50 pF 8 -40 to +125 74AHCT373 Octal D-type transparent latch; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 4.3 50 pF 8 -40 to +125 74AHC573 Octal D-type transparent latch (3-state) 2.0 to 5.5 CMOS ±8 4.2 50 pF 8 -40 to +125 4.5 to 5.5 TTL ±8 3.9 50 pF 8 -40 to +125 1.65 to 3.6 LVTTL ±24 6 50 pF 16 -40 to +85 1.65 to 3.6 LVTTL ±24 6 50 pF 18 -40 to +85 1.65 to 3.6 LVTTL ±24 6 50 pF 18 -40 to +85 1.65 to 3.6 LVTTL ±24 6 50 pF 20 -40 to +85 Type number Description 74AHC259 74AHCT573 74ALVC162334 74ALVC162834 74ALVC162835 74ALVC162836 Octal D-type transparent latch; TTL-enabled (3-state) 16-bit registered driver with 30 Ω termination resistors (3-state) 18-bit registered driver with 30 Ω termination resistors (3-state) 18-bit registered driver with 30 Ω termination resistors (3-state) 20-bit registered driver with 30 Ω termination resistors (3-state) 74ALVC16834 18-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 18 -40 to +85 74ALVC16835 18-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 18 -40 to +85 74ALVC16836 20-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 20 -40 to +85 74ALVC373 Octal D-type transparent latch (3-state) 1.65 to 3.6 LVTTL ±24 2.2 50 pF 8 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 94 NXP Logic selection guide 2016 Latches-registered drivers (cont.) Type number Description 74ALVC573 Octal D-type transparent latch (3-state) 74ALVCH16373 74ALVCH16832 74ALVCH16841 74ALVCH16843 74ALVCH32973 74ALVT16260 74ALVT16373 16-bit D-type transparent latch with bus hold (3-state) 7-bit to 28-bit address register/driver (3-state) 20-bit D-type transparent latch with bus hold (3-state) 18-bit D-type transparent latch with bus hold (3-state) 16-bit transceiver and transparent D-type latch with 8 independent buffers 12-bit to 24-bit multiplexed D-type latch with bus hold (3-state) 16-bit D-type transparent latch with bus hold (3-state) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Number of bits Tamb (°C) 1.65 to 3.6 LVTTL ±24 2.2 50 pF 8 -40 to +85 2.3 to 3.6 LVTTL ±24 2.1 50 pF 16 -40 to +85 2.3 to 3.6 LVTTL ±24 4 50 pF 7 -40 to +85 2.3 to 3.6 LVTTL ±24 2.4 50 pF 20 -40 to +85 2.3 to 3.6 LVTTL ±24 2.1 50 pF 18 -40 to +85 1.8 to 3.6 LVTTL ±24 2.5 50 pF 16 -40 to +85 2.3 to 3.6 TTL -32 / +64 2.8 50 pF 12 -40 to +85 2.3 to 3.6 TTL -32 / +64 1.8 50 pF 16 -40 to +85 74AUP1G373 Single D-type transparent latch (3-state) 1.1 to 3.6 CMOS 1.9 / -1.9 8.5 30 pF 1 -40 to +125 74AVC16334 16-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 16 -40 to +85 74AVC16373 16-bit D-type transparent latch (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 16 -40 to +85 74AVC16834 18-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 74AVC16835 18-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 74AVC16836 20-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 20 -40 to +85 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 1.2 to 3.6 CMOS ±12 2 30 pF 20 -40 to +85 18-bit registered driver with 30 Ω 74AVCM162834 termination resistors (3-state) 18-bit registered driver with 15 Ω 74AVCM162835 termination resistors (3-state) 20-bit registered driver with 15 Ω 74AVCM162836 termination resistors (3-state) 74HC259 8-bit addressable latch 2.0 to 6.0 CMOS ±5.2 18 50 pF 8 -40 to +125 74HCT259 8-bit addressable latch; TTL-enabled 4.5 to 5.5 TTL ±4 20 50 pF 8 -40 to +125 74HC373 Octal D-type transparent latch (3-state) 2.0 to 6.0 CMOS ±7.8 12 50 pF 8 -40 to +125 4.5 to 5.5 TTL ±6 14 50 pF 8 -40 to +125 4.5 to 5.5 TTL ±6 16 50 pF 8 -40 to +125 74HCT373 74HCT563 Octal D-type transparent latch; TTL-enabled (3-state) Octal D-type transparent latch; inverting; TTL-enabled (3-state) 74HC573 Octal D-type transparent latch (3-state) 2.0 to 6.0 CMOS ±7.8 14 50 pF 8 -40 to +125 74HCT573 Octal D-type transparent latch; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 17 50 pF 8 -40 to +125 74HC670 4-bit x 4-word register (3-state) 2.0 to 6.0 CMOS ±7.8 17 50 pF 4 -40 to +125 74HCT670 4-bit x 4-word register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 23 50 pF 4 -40 to +125 74HC75 Quad bistable transparent latch 2.0 to 6.0 CMOS ±5.2 11 50 pF 4 -40 to +125 74HC75 Quad bistable transparent latch 2.0 to 6.0 CMOS ±5.2 11 50 pF 4 -40 to +125 74LV259 8-bit addressable latch 1.0 to 3.6 CMOS ±6 17 50 pF 8 -40 to +125 74LV373 Octal D-type transparent latch (3-state) 1.0 to 5.5 CMOS ±16 10 50 pF 8 -40 to +125 74LV573 Octal D-type transparent latch (3-state) 1.0 to 5.5 CMOS ±16 12 50 pF 8 -40 to +125 1.2 to 3.6 TTL ±12 3.2 50 pF 16 -40 to +125 1.2 to 3.6 TTL ±24 3.2 50 pF 16 -40 to +125 74LVC162373 74LVCH162373 16-bit D-type transparent latch with 30 Ω termination resistors (3-state) 16-bit D-type transparent latch with bus hold and 30 Ω termination resistors (3-state) Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 95 Latches-registered drivers (cont.) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Number of bits Tamb (°C) 16-bit D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3 50 pF 16 -40 to +125 74LVCH16373 16-bit D-type transparent latch with bus hold (3-state) 1.2 to 3.6 TTL ±24 3 50 pF 16 -40 to +125 74LVC373 Octal D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3 50 pF 8 -40 to +125 74LVC573 Octal D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3.4 50 pF 8 -40 to +125 74LVC841 10-bit D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 4.5 50 pF 10 -40 to +125 74LVCH32373 32-bit D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3 50 pF 32 -40 to +125 2.7 to 3.6 TTL ±12 2.5 50 pF 16 -40 to +85 2.7 to 3.6 TTL -32 / +64 1.9 50 pF 16 -40 to +85 Type number Description 74LVC16373 74LVT162373 74LVT16373 16-bit D-type transparent latch with bus hold and 30 Ω termination resistors (3-state) 16-bit D-type transparent latch with bus hold (3-state) 74LVT573 Octal D-type transparent latch (3-state) 2.7 to 3.6 TTL -32 / +64 2.7 50 pF 8 -40 to +85 HEF40373 Octal D-type transparent latch (3-state) 4.5 to 15.5 CMOS -50 / +62 40 50 pF 8 -40 to +85 HEF4043 Quad R/S latch with set and reset (3-state) 4.5 to 15 CMOS ±2.4 25 50 pF 4 -40 to +85 HEF4044 Quad R/S latch with set and reset (3-state) 4.5 to 15 CMOS ±2.4 30 50 pF 4 -40 to +85 LEVEL SHIFTERS/TRANSLATORS Features and benefits 4 Bidirectional operation 4 Widths from 1 to 32 bits 4 Wide range of supply voltages 4 Low propagation delay 4 Low-power suspend mode 4 Auto-direction sensing 4 Optional overvoltage-tolerant inputs, 3-state outputs Applications 4 Mixed-voltage systems 4 I2C bus 4 Mobile, portable 4 Industrial 4 Consumer entertainment 4 Computing Level shifters-translators (cont.) Type number Description 74ALVC164245 Output Logic drive switching capability levels (mA) tpd (ns) Output Number Load of bits CL (Typ) VCC(A) (V) VCC(B) (V) 16-bit dual-supply voltagetranslating transceiver (3-state) 1.5 to 5.5 1.5 to 3.6 CMOS/ LVTTL ±24 2.9 50 16 -40 to +85 74AUP1T34 Single dual-supply translating buffer 1.1 to 3.6 1.1 to 3.6 CMOS ±1.9 15.2 30 1 -40 to +125 74AUP1T45 Single dual-supply voltagetranslating transceiver (3-state) 1.1 to 3.6 1.1 to 3.6 CMOS ±1.9 15.6 30 1 -40 to +125 74AVC16T245 16-bit dual-supply voltagetranslating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 16 -40 to +125 74AVC1T45 Single dual-supply voltagetranslating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 1 -40 to +125 74AVC20T245 20-bit dual-supply voltagetranslating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 3.5 30 20 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 96 NXP Logic selection guide 2016 Tamb (°C) Level shifters-translators (cont.) Type number Description 74AVC2T45 Output Logic drive switching capability levels (mA) tpd (ns) Output Number Load of bits CL (Typ) VCC(A) (V) VCC(B) (V) Tamb (°C) Dual-bit dual-supply voltagetranslating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 2 -40 to +125 74AVC32T245 32-bit dual-supply voltagetranslating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 32 -40 to +125 74AVC4T245 4-bit dual-supply voltage-translating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 4 -40 to +125 74AVC4TD245 4-bit dual-supply voltage-translating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 4 -40 to +125 74AVC8T245 8-bit dual-supply voltage-translating transceiver (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 8 -40 to +125 74AVCH16T245 16-bit dual-supply voltagetranslating transceiver with bus hold (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 16 -40 to +125 74AVCH1T45 Single dual-supply voltagetranslating transceiver with bus hold (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 1 -40 to +125 74AVCH20T245 20-bit dual-supply voltagetranslating transceiver with bus hold (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 3.5 30 20 -40 to +125 74AVCH2T45 Dual-bit dual-supply voltagetranslating transceiver with bus hold (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 2 -40 to +125 74AVCH4T245 4-bit dual-supply voltage-translating transceiver with bus hold (3-state) 0.8 to 3.6 0.8 to 3.6 CMOS/ LVTTL ±12 2.1 30 4 -40 to +125 74HC4049 Hex inverter with 15 V-tolerant inputs 2.0 to 6.0 N/A CMOS ±5.2 8 50 6 -40 to +125 74HC4050 Hex buffer with 15 V-tolerant inputs 2.0 to 6.0 N/A CMOS ±5.2 7 50 6 -40 to +125 74LVC1T45 Single dual-supply voltagetranslating transceiver (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL ±24 2.5 50 1 -40 to +125 74LVCH1T45 Single dual-supply voltagetranslating transceiver with bus hold (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL ±24 2.5 50 1 -40 to +125 74LVC2T45 Dual-bit dual-supply voltagetranslating transceiver (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL ±24 2.5 50 2 -40 to +125 74LVCH2T45 Dual-bit dual-supply voltagetranslating transceiver with bus hold (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL ±24 2.5 50 2 -40 to +125 74LVC8T245 8-bit dual-supply voltage-translating transceiver (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL ±24 3.5 50 8 -40 to +125 74LVCH8T245 8-bit dual-supply voltage-translating transceiver with bus hold (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL ±24 3.5 50 8 -40 to +125 74LVC4245 8-bit dual-supply voltage-translating transceiver (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL ±24 3.5 50 8 -40 to +125 HEF4104 Quad low-to-high voltage translator (3-state) 3.0 to 15.0 3.0 to 15.0 CMOS ±2.4 340 50 16 -40 to +85 74AXP1T57 Schmitt-trigger inputs, Dual supply configurable multiple function gate 0.7 to 2.75 1.2 to 5.5 1.2 to 5.5 CMOS ±12 4.8 1 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 97 MULTIVIBRATORS Features and benefits 4Simple control interface 4 Power-on reset 4 Dual devices with separate reset inputs 4 Negative or positive edge triggered 4 Low-power CMOS Applications 4 Timing delays in synchronous control circuits Multivibrators Type number Description VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Tamb (°C) 74AHC123 Dual retriggerable monostable multivibrator with reset 2.0 to 5.5 CMOS ±8 5.1 50 pF -40 to +125 74AHCT123 Dual retriggerable monostable multivibrator with reset; TTL-enabled 4.5 to 5.5 TTL ±8 5 50 pF -40 to +125 74HC123 Dual retriggerable monostable multivibrator with reset 2.0 to 6.0 CMOS ±7.8 9 50 pF -40 to +125 74HCT123 Dual retriggerable monostable multivibrator with reset; TTL-enabled 4.5 to 5.5 TTL ±4 26 50 pF -40 to +125 74HC221 dual non-retriggerable monostable multivibrator with reset 2.0 to 6.0 CMOS ±5.2 29 50 pF -40 to +125 74HCT221 dual non-retriggerable monostable multivibrator with reset; TTL-enabled 4.5 to 5.5 TTL ±4 32 50 pF -40 to +125 74HC423 Dual retriggerable monostable multivibrator with reset 2.0 to 6.0 CMOS ±5.2 23 50 pF -40 to +125 74HCT423 Dual retriggerable monostable multivibrator with reset; TTL-enabled 4.5 to 5.5 TTL ±4 26 50 pF -40 to +125 74HC4538 Dual retriggerable precision monostable multivibrator 2.0 to 6.0 CMOS ±5.2 27 50 pF -40 to +125 74HCT4538 Dual retriggerable precision monostable multivibrator; TTL-enabled 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125 74LV123 Dual retriggerable monostable multivibrator with reset 1.0 to 5.5 TTL ±12 20 50 pF -40 to +125 74LVC1G123 Single retriggerable monostable multivibrator 1.65 to 5.5 CMOS/ LVTTL ±32 3.5 50 pF -40 to +125 HEF4047 Monostable/astable multivibrator 4.5 to 15.5 CMOS ±2.4 50 50 pF -40 to +85 HEF4528 Dual retriggerable monostable multivibrator with reset 4.5 to 15.5 CMOS ±2.4 40 50 pF -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 98 NXP Logic selection guide 2016 PARITY GENERATORS/CHECKERS Features and benefits 4 Simple control interface 4 Power-on reset 4 Dual devices with separate reset inputs 4 Negative or positive edge triggered 4 Low-power CMOS Applications 4 Error detection Parity generators-checkers Output Logic drive switching capability levels (mA) Type number Description VCC (V) 74HC280 9-bit odd/even parity generator/checker 2.0 to 6.0 CMOS 74HCT280 9-bit odd/even parity generator/checker; TTL-enabled 4.5 to 5.5 TTL tpd (ns) Output Load CL (Typ) Tamb (°C) ±5.2 17 50 pF -40 to +125 ±4 18 50 pF -40 to +125 PHASE-LOCKED LOOPS Features and benefits 4 Phase comparator, loop filter, and VCO 4 Wide range of supply voltages 4 Maximum frequency to 17 MHz (typ) 4 Low power consumption 4 E xcellent VCO frequency linearity 4 Choice of phase comparators 4 User configurable Applications 4 FM modulation and demodulation 4Frequency synthesis and multiplication 4Clock recovery 4Data synchronization and conditioning 4Voltage-to-frequency conversion 4Motor-speed control interface Phase-locked loops VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Tamb (°C) Phase-locked loop with VCO 3.0 to 6.0 CMOS ±5.2 18 50 pF 21 74HCT4046 Phase-locked loop with VCO; TTL-enabled 4.5 to 5.5 TTL ±4 23 50 pF 19 74HC7046 Phase-locked loop with lock detector 3.0 to 6.0 CMOS ±5.2 17 50 pF 19 74HCT7046 Phase-locked loop with lock detector; TTL-enabled 4.5 to 5.5 TTL ±4 21 50 pF 19 74HCT9046 Phase-locked loop with bandgap controlled VCO; TTL-enabled 4.5 to 5.5 TTL ±4 23 50 pF 19 HEF4046 Phase-locked loop with VCO 4.5 to 15.5 CMOS ±2.4 50 pF 2.7 Type number Description 74HC4046 Printer interfaces Type number Description PDI1284P11 Parallel interface transceiver/buffer VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) Tamb (°C) 3.0 to 3.6 LVTTL - 14 / 14 13.9 50 pF 0 to +70 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 99 SCHMITT TRIGGERS Features and benefits 4 Transform slowly changing input signals into sharply defined, jitter-free output signals 4 Improve noisy signals 4 Reshape signals in complex layouts 4 Mixed 3.3/5 V applications 4 Wide range of supply voltages 4 Input hysteresis 4 CMOS and TTL variants 4 Optional open-drain outputs, overvoltage-tolerant inputs Applications 4Convert sine waves to square waves 4Interface between analog and digital environments 4Invoice noise immunity 4Relaxation oscillators Schmitt triggers (cont.) Type number 74AHC132 74AHCT132 Description Quad 2-input NAND gate Schmitt trigger Quad 2-input NAND gate Schmitt trigger; TTL-enabled VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) 2.0 to 5.5 CMOS ±8 3.3 50 pF 60 4 -40 to +125 4.5 to 5.5 TTL ±8 3.5 50 pF 60 4 -40 to +125 74AHC14 Hex inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 6 -40 to +125 74AHCT14 Hex inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4 50 pF 60 6 -40 to +125 74AHC1G14 Single inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 74AHCT1G14 Single inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 1 -40 to +125 74AHC3G14 Triple inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 3 -40 to +125 74AHCT3G14 Triple inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 3 -40 to +125 74ALVC14 Hex inverter Schmitt trigger 1.65 to 3.6 TTL ±24 2.4 50 pF 150 6 -40 to +85 74AUP1G17 Single buffer Schmitt trigger 1.1 to 3.6 CMOS ±1.9 7.8 30 pF 70 1 -40 to +125 74AUP2G132 dual 2-input NAND gate Schmitt trigger 1.1 to 3.6 CMOS ±1.9 10 30 pF 70 2 -40 to +125 74AUP2G14 dual inverter Schmitt trigger 1.1 to 3.6 CMOS ±1.9 4.7 30 pF 70 2 -40 to +125 74AUP2G17 dual buffer Schmitt trigger 1.1 to 3.6 CMOS ±1.9 7.8 30 pF 70 2 -40 to +125 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 4 -40 to +125 4.5 to 5.5 TTL ±4 17 50 pF 36 4 -40 to +125 74HC132 74HCT132 Quad 2-input NAND gate Schmitt trigger Quad 2-input NAND gate Schmitt trigger; TTL-enabled 74HC14 Hex inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 6 -40 to +125 74HCT14 Hex inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±4 17 50 pF 36 6 -40 to +125 74HC1G14 Single inverter Schmitt trigger 2.0 to 6.0 CMOS ±2.6 10 50 pF 36 1 -40 to +125 74HCT1G14 Single inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±2.0 15 50 pF 36 1 -40 to +125 74HC2G14 Dual inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 16 50 pF 36 2 -40 to +125 74HCT2G14 Dual inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±4.0 21 50 pF 36 2 -40 to +125 74HC2G17 Dual buffer Schmitt trigger 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 2 -40 to +125 74HCT2G17 Dual buffer Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±4.0 21 50 pF 36 2 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 100 NXP Logic selection guide 2016 Schmitt triggers (cont.) Type number Description 74HC3G14 Triple inverter Schmitt trigger 74HCT3G14 74HC7540 74HCT7540 74HC7541 74HCT7541 74HC9114 74HCT9114 74HC9115 74HCT9115 Triple inverter Schmitt trigger; TTL-enabled Octal inverter/line driver Schmitt trigger (3-state) Octal inverter/line driver Schmitt trigger; TTL-enabled (3-state) Octal buffer/line driver Schmitt trigger (3-state) Octal buffer/line driver Schmitt trigger; TTL-enabled (3-state) 9-bit inverter Schmitt trigger; open drain (3-state) 9-bit inverter Schmitt trigger; open drain; TTL-enabled (3-state) 9-bit buffer Schmitt trigger; open drain (3-state) 9-bit buffer Schmitt trigger; open drain; TTL-enabled (3-state) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) 2.0 to 6.0 CMOS ±5.2 16 50 pF 36 3 -40 to +125 4.5 to 5.5 TTL ±4.0 21 50 pF 36 3 -40 to +125 2.0 to 6.0 CMOS ±7.8 11 50 pF 36 8 -40 to +125 4.5 to 5.5 TTL ±6 16 50 pF 36 8 -40 to +125 2.0 to 6.0 CMOS ±7.8 11 50 pF 36 8 -40 to +125 4.5 to 5.5 TTL ±6 16 50 pF 36 8 -40 to +125 2.0 to 6.0 CMOS 5,2 12 50 pF 36 9 -40 to +125 4.5 to 5.5 TTL 4 13 50 pF 36 9 -40 to +125 2.0 to 6.0 CMOS 5,2 12 50 pF 36 9 -40 to +125 4.5 to 5.5 TTL 4 13 50 pF 36 9 -40 to +125 74HC7014 Hex buffer precision Schmitt trigger 2.0 to 6.0 CMOS ±5.2 27 50 pF 36 6 -40 to +125 74LV132 Quad 2-input NAND gate Schmitt trigger 1.0 to 5.5 TTL ±12 10 50 pF 30 4 -40 to +125 74LV14 Hex inverter Schmitt trigger 1.0 to 5.5 TTL ±12 13 50 pF 30 6 -40 to +125 74LVC132 Quad 2-input NAND gate Schmitt trigger 1.2 to 3.6 ±24 3.4 50 pF 175 4 -40 to +125 74LVC14 Hex inverter Schmitt trigger 1.2 to 3.6 ±24 3.2 50 pF 175 6 -40 to +125 74LVC1G14 Single inverter Schmitt trigger 1.65 to 5.5 ±32 3 50 pF 175 1 -40 to +125 74LVC1G17 Single buffer Schmitt trigger 1.65 to 5.5 ±32 3 50 pF 175 1 -40 to +125 74LVC2G14 Dual inverter Schmitt trigger 1.65 to 5.5 ±32 3.9 50 pF 175 2 -40 to +125 74LVC2G17 Dual buffer Schmitt trigger 1.65 to 5.5 ±32 3.6 50 pF 175 2 -40 to +125 74LVC3G14 Triple inverter Schmitt trigger 1.65 to 5.5 ±32 3.2 50 pF 175 3 -40 to +125 74LVC3G17 Triple buffer Schmitt trigger 1.65 to 5.5 ±32 3.6 50 pF 175 3 -40 to +125 74LVT14 Hex inverter Schmitt trigger 2.7 to 3.6 TTL -32 / +64 3.8 50 pF 150 6 -40 to +125 74VHCT14 Hex inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 6 -40 to +125 HEF40106 Hex inverter Schmitt trigger 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 6 -40 to +85 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +125 4.5 to 5.5 TTL ±8 4.1 50 pF 60 1 -40 to +125 HEF4093 XC7SET14 Quad 2-input NAND gate Schmitt trigger Single inverter Schmitt trigger; TTL-enabled CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL XC7SH14 Single inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 XC7WH14 Triple inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 3 -40 to +125 XC7WT14 Triple inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 3 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 101 SHIFT REGISTERS/LED DRIVERS Features and benefits 4 Simple control interface 4 A synchronous and synchronous load options 4 High frequency 4 Cascadable Applications 4 LED displays 4Control units 4I/O expansion Shift registers - LED drivers (cont.) Type number Description 74AHC164 74AHCT164 74AHC594 74AHCT594 74AHC595 74AHCT595 74HC164 74HCT164 74HC165 74HCT165 74HC166 74HCT166 74HC194 74HCT194 74HC299 74HCT299 74HC4015 74HCT4015 74HC4094 74HCT4094 74HC594 74HCT594 8-bit serial-in/parallel-out shift register 8-bit serial-in/parallel-out shift register; TTL-enabled 8-bit serial-in/parallel-out shift register with output storage register 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) 8-bit serial-in/parallel-out shift register 8-bit serial-in/parallel-out shift register; TTL-enabled 8-bit parallel or serial-in/serial-out shift register 8-bit parallel or serial-in/serial-out shift register; TTL-enabled 8-bit parallel or serial-in/serial-out shift register 8-bit parallel or serial-in/serial-out shift register; TTL-enabled 4-bit bidirectional parallel or serial-in/ parallel-out shift register 4-bit bidirectional parallel or serial-in/ parallel-out shift register; TTL-enabled 8-bit universal shift register (3-state) 8-bit universal shift register; TTL-enabled (3-state) Dual 4-bit serial-in/parallel-out shift register Dual 4-bit serial-in/parallel-out shift register; TTL-enabled 8-bit serial-in/serial or parallel-out shift register with output register (3-state) 8-bit serial-in/serial or parallel-out shift register with output register; TTL-enabled (3-state) 8-bit serial-in/parallel-out shift register with output storage register 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) 2.0 to 5.5 CMOS ±8 4.5 50 pF 115 8 -40 to +125 4.5 to 5.5 TTL ±8 3.4 50 pF 115 8 -40 to +125 2.0 to 5.5 CMOS ±8 4.1 50 pF 160 8 -40 to +125 4.5 to 5.5 TTL ±8 3.8 50 pF 160 8 -40 to +125 2.0 to 5.5 CMOS ±8 4 50 pF 170 8 -40 to +125 4.5 to 5.5 TTL ±8 3.8 50 pF 170 8 -40 to +125 2.0 to 6.0 CMOS ±5.2 12 50 pF 78 8 -40 to +125 2.0 to 6.0 CMOS ±5.2 12 50 pF 78 8 -40 to +125 2.0 to 6.0 CMOS ±5.2 16 50 pF 56 8 -40 to +125 4.5 to 5.5 TTL ±4 14 50 pF 48 8 -40 to +125 2.0 to 6.0 CMOS ±5.2 15 50 pF 63 8 -40 to +125 4.5 to 5.5 TTL ±4.0 23 50 pF 50 8 -40 to +125 2.0 to 6.0 CMOS ±5.2 14 50 pF 102 4 -40 to +125 4.5 to 5.5 TTL ±4 15 50 pF 77 4 -40 to +125 2.0 to 6.0 CMOS ±7.8 19 50 pF 54 8 -40 to +125 4.5 to 5.5 TTL ±6 19 50 pF 46 8 -40 to +125 2.0 to 6.0 CMOS ±5.2 15 50 pF 85 4 -40 to +125 4.5 to 5.5 TTL ±4 18 50 pF 74 4 -40 to +125 2.0 to 6.0 CMOS ±5.2 15 50 pF 95 8 -40 to +125 4.5 to 5.5 TTL ±4 19 50 pF 86 8 -40 to +125 2.0 to 6.0 CMOS ±7.8 14 50 pF 109 8 -40 to +125 4.5 to 5.5 TTL ±6 15 50 pF 100 8 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 102 NXP Logic selection guide 2016 Shift registers - LED drivers (cont.) Type number Description 74HC595 74HCT595 74HC597 74HCT597 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) 8-bit parallel or serial-in/parallelout shift register with parallel input storage register 8-bit parallel or serial-in/parallelout shift register with parallel input storage register; TTL-enabled VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Output Load CL (Typ) fmax (MHz) Number of bits Tamb (°C) 2.0 to 6.0 CMOS ±7.8 16 50 pF 108 8 -40 to +125 4.5 to 5.5 TTL ±6 25 50 pF 57 8 -40 to +125 2.0 to 6.0 CMOS ±5.2 16 50 pF 108 8 -40 to +125 4.5 to 5.5 TTL ±4 20 50 pF 83 8 -40 to +125 74HC7731 Quad 64-bit shift register 2.0 to 6.0 CMOS ±5.2 15 50 pF 100 64 -40 to +125 74HCT7731 Quad 64-bit shift register; TTL-enabled 4.5 to 5.5 TTL ±4 20 50 pF 100 64 -40 to +125 74LV164 8-bit serial-in/parallel-out shift register 1.0 to 5.5 TTL ±12 12 50 pF 78 8 -40 to +125 1.0 to 5.5 TTL ±12 18 50 pF 78 8 -40 to +125 1.0 to 3.6 TTL ±6 14 50 pF 95 8 -40 to +125 1.0 to 3.6 TTL ±8 15 50 pF 77 8 -40 to +125 ±24 3.1 50 pF 180 8 -40 to +125 ±24 4 50 pF 180 8 -40 to +125 74LV165 74LV4094 74LV595 74LVC594 74LVC595 74VHC595 74VHCT595 HEF4014 HEF4015 HEF4021 HEF4094 HEF4517 HEF4557 HEF4794 HEF4894 NPIC6C4894 NPIC6C595 NPIC6C596 8-bit parallel or serial-in/serial-out shift register 8-bit serial-in/serial or parallel-out shift register with output register (3-state) 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) 8-bit shift register with synchronous parallel enable dual 4-bit serial-in/parallel-out shift register 8-bit shift register with asynchronous parallel load 8-bit serial-in/serial or parallel-out shift register with output register (3-state) Dual 64-bit serial-in/parallel-out shift register 1-to-64-bit shift register with variable length 8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) 12-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) 12-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) 1.2 to 5.5 1.2 to 5.5 CMOS/ LVTTL CMOS/ LVTTL 2.0 to 5.5 CMOS ±8 4 50 pF 170 8 -40 to +125 4.5 to 5.5 TTL ±8 3.8 50 pF 170 8 -40 to +125 4.5 to 15 CMOS ±2.4 40 50 pF 40 8 -40 to +85 4.5 to 15 CMOS ±2.4 40 50 pF 44 4 -40 to +85 4.5 to 15 CMOS ±2.4 40 50 pF 40 8 -40 to +85 4.5 to 15 CMOS ±2.4 50 50 pF 28 8 -40 to +85 4.5 to 15 CMOS ±2.4 60 50 pF 16 64 -40 to +85 4.5 to 15 CMOS ±2.4 65 50 pF 20 64 -40 to +85 4.5 to 15 CMOS -20 45 50 pF 28 8 -40 to +85 4.5 to 15 CMOS 20 45 50 pF 28 12 -40 to +85 4.5 to 5.5 CMOS 100 90 30 pF 10 12 -40 to +125 4.5 to 5.5 CMOS 100 90 30 pF 10 8 -40 to +125 4.5 to 5.5 CMOS 100 90 30 pF 10 8 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 103 TRANSCEIVERS Features and benefits 4 Bidirectional operation 4 Mixed 3.3/5 V applications 4 Widths from 4 to 32 bits 4 Improve the current drive and signal levels 4 Improve signal integrity in complex layouts 4 Wide range of supply voltages 4 Low propagation delay 4 Registered options 4 Optional TTL inputs, source-termination resistors, overvoltage-tolerant inputs, bus hold Applications 4 Parallel backplanes 4Telecommunications infrastructure 4Industrial control 4Test systems Transceivers (cont.) tpd (ns) Number of bits fmax (MHz) Output Load CL (Typ) ±8 3.5 8 60 50 pF TTL ±8 5 8 60 50 pF 1.65 to 3.6 TTL ±24 1.9 16 150 50 pF 16-bit transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 1.9 16 150 50 pF 74ALVC245 Octal transceiver (3-state) 1.65 to 3.6 TTL ±24 2.3 8 130 50 pF 74ALVCH162245 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 1.65 to 3.6 TTL ±12 2.4 16 150 50 pF 1.65 to 3.6 TTL ±12 3.1 18 150 50 pF Description 74AHC245 Octal transceiver (3-state) 2.0 to 5.5 CMOS 74AHCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 74ALVC16245 16-bit transceiver (3-state) 74ALVCH16245 18-bit universal bus transceiver with bus hold and 74ALVCH162601 30 Ω termination resistors; positive-edge trigger (3-state) VCC (V) Logic Output switching drive levels capability Type number 74ALVCH16500 18-bit universal bus transceiver with bus hold; negative edge trigger (3-state) 1.65 to 3.6 TTL ±24 2.9 18 150 50 pF 74ALVCH16501 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF 74ALVCH16543 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 3.8 16 150 50 pF 74ALVCH16600 18-bit universal bus transceiver with bus hold; negative edge trigger (3-state) 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF 74ALVCH16601 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF 74ALVCH16646 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 2.6 16 150 50 pF 74ALVCH16952 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 3.2 16 150 50 pF 74ALVT162245 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 TTL ±12 2.3 16 75 50 pF 74ALVT16245 16-bit transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 1.5 16 200 50 pF 74ALVT16501 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 2.3 to 3.6 TTL -32 / +64 1.8 18 150 50 pF 74ALVT16543 16-bit registered transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 1.8 16 200 50 pF 74ALVT16601 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 2.3 to 3.6 TTL -32 / +64 1.9 18 200 50 pF 74ALVT16652 16-bit registered transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 2.4 16 150 50 pF Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 104 NXP Logic selection guide 2016 Transceivers (cont.) tpd (ns) Number of bits fmax (MHz) Output Load CL (Typ) ±12 2 16 200 30 pF CMOS ±12 2 16 200 30 pF 2.0 to 6.0 CMOS ±7.8 7 8 36 50 pF Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 10 8 36 50 pF 74HC640 Octal transceiver; inverting (3-state) 2.0 to 6.0 CMOS ±7.8 9 8 36 50 pF 74HCT640 Octal transceiver; inverting; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 9 8 36 50 pF 74HC652 Octal registered transceiver (3-state) 2.0 to 6.0 CMOS ±7.8 13 8 36 50 pF 74HCT652 Octal registered transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 13 8 36 50 pF 74LV245 Octal transceiver (3-state) 1.0 to 5.5 TTL ±16 7 8 30 50 pF 74LVC162245 16-bit transceiver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 16 175 50 pF 74LVCH162245 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 16 175 50 pF 74LVC16245 16-bit transceiver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3 16 175 50 pF 74LVCH16245 16-bit transceiver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3 16 175 50 pF 74LVC245 Octal transceiver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 2.9 8 175 50 pF 74LVCH245 Octal transceiver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 2.9 8 175 50 pF 74LVC2245 Octal transceiver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 8 175 50 pF 74LVC2952 Octal registered transceiver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 4.3 8 175 50 pF 74LVC32245 32-bit transceiver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 2.2 32 175 50 pF 74LVC543 Octal registered transceiver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3.3 8 175 50 pF 74LVC544 Octal registered transceiver; inverting (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 4 8 175 50 pF 74LVC623 Octal transceiver with dual enable (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3.3 8 175 50 pF 74LVC646 Octal registered transceiver (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3.9 8 175 50 pF 74LVCH322245 32-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 32 175 50 pF 74LVCH32245 32-bit transceiver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3 32 175 50 pF 74LVT16245 16-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVTH16245 16-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVT2245 Octal transceiver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL ±12 3.2 8 150 50 pF VCC (V) Logic Output switching drive levels capability Type number Description 74AVC16245 16-bit transceiver (3-state) 1.2 to 3.6 CMOS 74AVCH16245 16-bit transceiver with bus hold (3-state) 1.2 to 3.6 74HC245 Octal transceiver (3-state) 74HCT245 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 105 Transceivers (cont.) tpd (ns) Number of bits fmax (MHz) Output Load CL (Typ) ±12 3.2 8 150 50 pF TTL ±12 2.5 16 150 50 pF 2.7 to 3.6 TTL -32 / +64 1.9 18 150 50 pF 18-bit universal bus transceiver with bus hold; positive-edge trigger (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 18 150 50 pF 74LVT16543 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 2.2 16 150 50 pF 74LVT16646 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVT16652 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVT245 Octal transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 2.4 8 150 50 pF 74LVT2952 Octal registered transceiver with 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL -32 / +64 3.8 8 150 50 pF 74LVT543 Octal registered transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 3 8 150 50 pF 74LVT543 Octal registered transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 3 8 150 50 pF 74LVT640 Octal transceiver with bus hold; inverting (3-state) 2.7 to 3.6 TTL -32 / +64 2.4 8 150 50 pF 74LVT646 Octal registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 3.8 8 150 50 pF 74LVT652 Octal registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 3.7 8 150 50 pF 74LVTH322245 32-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL ±12 2.5 32 150 50 pF 74LVTH32245 32-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 32 150 50 pF 74LVTN16245 16-bit transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74VHC245 Octal transceiver (3-state) 2.0 to 5.5 CMOS ±8 3.5 8 60 50 pF 74VHCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 5 8 60 50 pF VCC (V) Logic Output switching drive levels capability Type number Description 74LVTH2245 Octal transceiver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL 74LVT162245 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 74LVT16500 18-bit universal bus transceiver with bus hold; negative-edge trigger (3-state) 74LVT16501 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 106 NXP Logic selection guide 2016 Q100 Standard Logic functions & packages Standard logic functions include options suitable for use at supply voltage between 1.0 V and 15 V. They provide a wide range of functions such as analog switches, buffers/inverters, bus switches, counters, decoders/de-multiplexers, multiplexers, flip-flops, gates, latches, level shifters, multivibrators, Schmitt triggers, shift registers and transceivers. Q100 Standard logic is available in leaded SO and TSSOP packages as well as the innovative leadless DQFN package. NXP’s DQFN packages include side-wettable flanks, making them suitable for automated optical inspection. The package suffixes used in the tables are for all logic families with the exception of HEF4000B. The suffixes for HEF4000B can be found under Standard Logic Packages. Analog switches SOT403-1 (PW) SOT763-1 (BQ) 20 -40~125 • • • 74HCT4051-Q100 Single-pole, octal-throw analog switch; TTL-enabled SP8T-Z 4.5 - 5.5 225 20 -40~125 • • • 74HC4052-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 2.0 - 10.0 200 20 -40~125 • • • 74HCT4052-Q100 Dual single-pole, quad-throw analog switch; TTL-enabled SP4T-Z 4.5 - 5.5 200 20 -40~125 • • • 74HC4053-Q100 Triple single-pole, double-throw analog switch SP8T-Z 2.0 - 10.0 200 20 -40~125 • • • 74HCT4053-Q100 Triple single-pole, double-throw analog switch; TTL-enabled SP8T-Z 4.5 - 5.5 200 20 -40~125 • • • 74HC4066-Q100 Quad single-pole, single-throw analog switch SPST-NO 2.0 - 10.0 105 23 -40~125 • • • 74HCT4066-Q100 Quad single-pole, single-throw analog switch; TTL-enabled SPST-NO 23 -40~125 • • • 74HC4851-Q100 Single-pole, octal-throw analog switch SP8T-Z 2.0 - 10.0 220 - -40~125 • • • 74HCT4851-Q100 Single-pole, octal-throw analog switch; TTL-enabled SP8T-Z 4.5 - 5.5 240 - -40~125 • • • 74HC4852-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 2.0 - 10.0 220 - -40~125 • • • 74HCT4852-Q100 Dual single-pole, quad-throw analog switch; TTL-enabled SP4T-Z 4.5 - 5.5 240 - -40~125 • • • 74LV4052-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 1.0 - 6.0 125 15 -40~125 • • 74LV4053-Q100 Triple single-pole, double-throw analog switch SPDT-Z 1.0 - 6.0 150 30 -40~125 • • 74LVC4066-Q100 Quad single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 HEF4051B-Q100 Single-pole, octal-throw analog switch SP8T-Z 4.5 - 15.5 175 30 -40~85 • • HEF4052B-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 4.5 - 15.5 175 30 -40~85 • • HEF4053B-Q100 Triple single-pole, double-throw analog switch SPDT-Z 4.5 - 15.5 175 30 -40~85 • • HEF4066B-Q100 Quad single-pole, single-throw analog switch SPST-NO 4.5 - 15.5 175 20 -40~85 HEF4067B-Q100 Single-pole, 16-throw analog switch 20 -40~85 SP16T-Z 118 4.5 - 15.5 175 • • SOT137-1 (D) SOT109-1 (D) 2.0 - 10.0 200 SOT762-1 (BQ) SP8T-Z 4.5 - 5.5 SOT402-1 (PW) Single-pole, octal-throw analog switch SOT108-1 (D) Tamb (°C) 74HC4051-Q100 VCC (V) Description Configuration Type number RON (FLAT) (W) Package (suffix) RON (W) Features • • • NXP Logic selection guide 2016 • 107 Buffers/inverters (cont.) SOT762-1 (BQ) SOT360-1 (PW) SOT764-1 (BQ) ±8 3 -40~125 • • • 74AHCT04-Q100 Hex inverter; TTL-enabled 4.5 - 5.5 ±8 3 -40~125 • • • 74AHC125-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ±8 3 -40~125 • • • 74AHCT125-Q100 Quad buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3 -40~125 • • • 74AHC126-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ±8 3.3 -40~125 • • • 74AHCT126-Q100 Quad buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3 -40~125 • • • 74AHC240-Q100 Octal inverter/line driver (3-state) 2.0 - 5.5 ±8 2.8 -40~125 • • • 74AHCT240-Q100 Octal inverter/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3 -40~125 • • • 74AHC244-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • • 74AHCT244-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.5 -40~125 • • • 74AHC541-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • • 74AHCT541-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.5 -40~125 • • • 74AHCU04-Q100 Hex inverter; unbuffered 2.0 - 5.5 ±8 2.4 -40~125 • • • 74ALVC125-Q100 Quad buffer/line driver (3-state) 1.65 - 3.6 ± 24 1.8 -40~85 • • • 74ALVC541-Q100 Octal buffer/line driver (3-state) 1.65 - 3.6 ± 24 2.3 -40~85 • • • 74HC05-Q100 Hex inverter; open-drain 2.0 - 6.0 5.2 11 -40~125 • 74HC04-Q100 Hex inverter 2.0 - 6.0 ± 5.2 7 -40~125 • 74HCT04-Q100 Hex inverter; TTL-enabled 4.5 - 5.5 ± 4.0 8 -40~125 74HC125-Q100 Quad buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 74HCT125-Q100 Quad buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±6 74HC126-Q100 Quad buffer/line driver (3-state) 2.0 - 6.0 74HCT126-Q100 Quad buffer/line driver; TTL-enabled (3-state) 74HC240-Q100 • • • • • • • -40~125 • • 12 -40~125 • • ± 7.8 9 -40~125 • • 4.5 - 5.5 ±6 11 -40~125 • • Octal inverter/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • • 74HCT240-Q100 Octal inverter/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±6 9 -40~125 • • • 74HC244-Q100 Octal buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • • 74HCT244-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±6 11 -40~125 • • • 74HC365-Q100 Hex buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • 74HCT365-Q100 Hex buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±6 11 -40~125 • • 74HC366-Q100 Hex inverter/line driver (3-state) 2.0 - 6.0 ± 7.8 10 -40~125 • • 74HCT366-Q100 Hex inverter/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±6 11 -40~125 • • 108 NXP Logic selection guide 2016 • SOT362-1 (DGG) SOT402-1 (PW) 2.0 - 5.5 SOT339-1 (DB) SOT108-1 (D) Hex inverter SOT163-1 (D) Tamb (°C) SOT403-1 (PW) tpd (ns) 74AHC04-Q100 SOT109-1 (D) Description SOT337-1 (DB) Type number IO (mA) Package (suffix) VCC (V) Features Buffers/inverters (cont.) Octal inverter/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • 74HCT540-Q100 Octal inverter/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±6 11 -40~125 • 74HC541-Q100 Octal buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 10 -40~125 • • 74HCT541-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±6 12 -40~125 • • 74HCU04-Q100 Hex inverter; unbuffered 2.0 - 6.0 ± 5.2 5 -40~125 74LV244-Q100 Octal buffer/line driver (3-state) 1.0 - 5.5 ± 16 8 -40~125 • • 74LVC04A-Q100 Hex inverter 1.65 - 5.5 ± 24 2 74LVC06A-Q100 Hex inverter; open-drain 1.65 - 5.5 32 74LVC07A-Q100 Hex buffer; open-drain 1.65 - 5.5 74LVC125A-Q100 Quad buffer/line driver (3-state) 74LVC126A-Q100 • • SOT362-1 (DGG) 74HC540-Q100 SOT764-1 (BQ) SOT360-1 (PW) SOT339-1 (DB) SOT163-1 (D) SOT403-1 (PW) SOT109-1 (D) SOT762-1 (BQ) Tamb (°C) SOT402-1 (PW) Description tpd (ns) SOT337-1 (DB) Type number IO (mA) SOT108-1 (D) Package (suffix) VCC (V) Features • • • -40~125 • • • 2.2 -40~125 • • • 32 2.2 -40~125 • • • 1.2 - 3.6 ± 24 2.4 -40~125 • • • Quad buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 • • • 74LVC541A-Q100 Octal buffer/line driver (3-state) 1.2 - 3.6 ± 24 3.3 -40~125 74LVC16240A-Q100 16-bit inverter/line driver (3-state) 1.2 - 3.6 ± 24 2.7 -40~125 74LVC244A-Q100 Octal buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.8 -40~125 • 74LVCH244A-Q100 Octal buffer/line driver with bus hold (3-state) 1.2 - 3.6 ± 24 2.8 -40~125 • 74LVC16244A-Q100 16-bit buffer/line driver (3-state) 1.2 - 3.6 ± 24 3 -40~125 • 74LVCH16244A-Q100 16-bit buffer/line driver with bus hold (3-state) 1.2 - 3.6 ± 24 3 -40~125 • 74LVT04-Q100 Hex inverter 2.7 - 3.6 -20 / +32 2.6 -40~85 74LVT244A-Q100 Octal buffer/line driver with bus hold (3-state) 2.7 - 3.6 -32 / +64 2.6 -40~85 • • 74LVTH244A-Q100 Octal buffer/line driver with bus hold (3-state) 2.7 - 3.6 -32 / +64 2.6 -40~85 • • 74VHC126-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ±8 3.3 -40~125 • • • 74VHCT126-Q100 Quad buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3 -40~125 • • • 74VHC541-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • • 74VHCT541-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.5 -40~125 • • • HEF4049B-Q100 Hex inverter/line driver 3.0 - 15.0 -3 / +20 20 -40~85 • HEF4050B-Q100 Hex buffer/line driver 3.0 - 15.0 -3 / +20 40 -40~85 • HEF4069UB-Q100 Hex inverter; unbuffered 3.0 - 15.0 ± 3.4 15 -40~85 • • • • • • • • • • • • NXP Logic selection guide 2016 109 Bus switches SOT403-1 (PW) -40~125 • • 74CBTLV3253-Q100 Dual 4:1 mux/demux 2.3 - 3.6 3.3 7 -40~125 • • 74CBTLV3257-Q100 Quad 2:1 mux/demux 2.3 - 3.6 3.3 7 -40~125 • • CBT3245A-Q100 Octal bus switch 4.5 - 5.5 3.9 7 -40~85 SOT764-1 (BQ) SOT109-1 (D) 7 • • • SOT763-1 (BQ) SOT762-1 (BQ) 3.3 SOT360-1 (PW) SOT402-1 (PW) 2.3 - 3.6 SOT403-1 (PW) Tamb (°C) Quad bus switch SOT163-1 (D) RON (W) 74CBTLV3126-Q100 SOT763-1 (BQ) Description SOT519-1 (DS) Type number VPASS (V) Package (suffix) VCC (V) Features • • • Counters/frequency dividers (cont.) Tamb (°C) SOT108-1 (D) SOT402-1 (PW) 7-stage binary ripple counter 2.0 - 6.0 ± 5.2 14 -40~125 • • 74HC163-Q100 Presettable synchronous 4-bit binary counter; synchronous reset 2.0 - 6.0 ± 5.2 17 -40~125 • • 74HCT163-Q100 Presettable synchronous 4-bit binary counter; synchronous reset; TTL-enabled 4.5 - 5.5 ± 4.0 20 -40~125 • • 74HC193-Q100 Presettable synchronous 4-bit binary up/down counter 2.0 - 6.0 ± 5.2 20 -40~125 • • • 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter; TTL-enabled 4.5 - 5.5 ± 4.0 20 -40~125 • • • 74HC393-Q100 Dual 4-bit binary ripple counter 2.0 - 6.0 ± 5.2 12 -40~125 • • • 74HCT393-Q100 Dual 4-bit binary ripple counter; TTL-enabled 4.5 - 5.5 ± 4.0 20 -40~125 • • • 74HC4017-Q100 Johnson decade counter with 10 decoded outputs 2.0 - 6.0 ± 5.2 18 -40~125 • 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs; TTL-enabled 4.5 - 5.5 ± 4.0 21 -40~125 • 74HC4020-Q100 14-stage binary ripple counter 2.0 - 6.0 ± 5.2 11 -40~125 • • • 74HCT4020-Q100 14-stage binary ripple counter; TTL-enabled 4.5 - 5.5 ± 4.0 15 -40~125 • • • 74HC4040-Q100 12-stage binary ripple counter 2.0 - 6.0 ± 5.2 14 -40~125 • • • • 74HCT4040-Q100 12-stage binary ripple counter; TTL-enabled 4.5 - 5.5 ± 4.0 16 -40~125 • • • • 74HC4060-Q100 14-stage binary ripple counter with oscillator 2.0 - 6.0 ± 5.2 31 -40~125 • • • 74HCT4060-Q100 14-stage binary ripple counter with oscillator; TTL-enabled 4.5 - 5.5 ± 4.0 31 -40~125 • 74HC4520-Q100 Dual 4-bit synchronous binary counter 2.0 - 6.0 ± 5.2 24 -40~125 • 74HCT4520-Q100 Dual 4-bit synchronous binary counter; TTL-enabled 4.5 - 5.5 ± 4.0 24 -40~125 • 74LV393-Q100 Dual 4-bit binary ripple counter 1.0 - 3.6 ±6 12 -40~125 110 NXP Logic selection guide 2016 • • SOT338-1 (DB) tpd (ns) 74HC4024-Q100 SOT109-1 (D) Description SOT762-1 (BQ) Type number IO (mA) Package (suffix) VCC (V) Features • • • • • Counters/frequency dividers (cont.) 4.5 - 15.5 ± 2.4 40 -40~85 • HEF4020B-Q100 14-stage binary ripple counter 4.5 - 15.5 ± 2.4 30 -40~85 • HEF4040B-Q100 12-stage binary ripple counter 4.5 - 15.5 ± 2.4 35 -40~85 • HEF4060B-Q100 14-stage binary ripple counter with oscillator 4.5 - 15.5 ± 2.4 50 -40~85 • HEF4541B-Q100 programmable timer 4.5 - 15.5 - 4/ + 2.7 38 -40~85 SOT763-1 (BQ) 5-stage Johnson decade counter SOT403-1 (PW) Tamb (°C) HEF4017B-Q100 SOT338-1 (DB) tpd (ns) SOT109-1 (D) Description IO (mA) SOT762-1 (BQ) Type number VCC (V) SOT402-1 (PW) Package (suffix) SOT108-1 (D) Features • Digital decoders/demultiplexers Description tpd (ns) Tamb (°C) SOT109-1 (D) SOT403-1 (PW) SOT763-1 (BQ) 74AHC138-Q100 3-to-8 line decoder/demultiplexer; inverting 2.0 - 5.5 ±8 4.4 -40~125 • • • 74AHCT138-Q100 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 - 5.5 ±8 4.4 -40~125 • • • 74AHC139-Q100 Dual 2-to-4 line decoder/demultiplexer 2.0 - 5.5 ±8 3.9 -40~125 • • 74AHCT139-Q100 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • • 74HC237-Q100 3-to-8 decoder/demultiplexer with address latches 2.0 - 6.0 ± 5.2 18 -40~125 • 74HC138-Q100 3-to-8 line decoder/demultiplexer; inverting 2.0 - 6.0 ± 5.2 12 -40~125 • • • 74HCT138-Q100 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 - 5.5 ±4 19 -40~125 • • • 74HC139-Q100 Dual 2-to-4 line decoder/demultiplexer 2.0 - 6.0 ± 5.2 14 -40~125 • • • 74HCT139-Q100 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 - 5.5 ±4 16 -40~125 • • • 74HC238-Q100 3-to-8 decoder/demultiplexer 2.0 - 6.0 ± 5.2 14 -40~125 • • • 74HCT238-Q100 3-to-8 decoder/demultiplexer; TTL-enabled 4.5 - 5.5 ±4 18 -40~125 • • • 74LVC138A-Q100 3-to-8 line decoder/demultiplexer; inverting 1.2 - 3.6 ± 24 2.7 -40~125 • • • HEF4555B-Q100 Dual 1-to-4 line decoder/demultiplexer 4.5 - 15 ± 2.4 30 -40~85 • SOT338-1 (DB) Type number IO (mA) Package (suffix) VCC (V) Features NXP Logic selection guide 2016 111 Digital multiplexers Description tpd (ns) Tamb (°C) SOT109-1 (D) SOT403-1 (PW) SOT763-1 (BQ) 74AHC157-Q100 Quad 2-input multiplexer 2.0 - 5.5 ±8 3.2 -40~125 • • • 74AHCT157-Q100 Quad 2-input multiplexer; TTL-enabled 4.5 - 5.5 ±8 3.2 -40~125 • • • 74AHC257-Q100 Quad 2-input multiplexer (3-State) 2.0 - 5.5 ±8 2.9 -40~125 • • 74AHCT257-Q100 Quad 2-input multiplexer; TTL-enabled (3-State) 4.5 - 5.5 ±8 3.7 -40~125 • • 74HC151-Q100 8-input multiplexer 2.0 - 6.0 ± 5.2 17 -40~125 • • 74HCT151-Q100 8-input multiplexer; TTL-enabled 4.5 - 5.5 ±4 19 -40~125 • • 74HC153-Q100 Dual 4-input multiplexer 2.0 - 6.0 ± 5.2 17 -40~125 • • 74HCT153-Q100 Dual 4-input multiplexer; TTL-enabled 4.5 - 5.5 ±4 19 -40~125 • • 74HC157-Q100 Quad 2-input multiplexer 2.0 - 6.0 ± 5.2 11 -40~125 • • • 74HCT157-Q100 Quad 2-input multiplexer; TTL-enabled 4.5 - 5.5 ±4 13 -40~125 • • • 74HC251-Q100 8-input multiplexer (3-State) 2.0 - 6.0 ± 5.2 18 -40~125 • • 74HCT251-Q100 8-input multiplexer; TTL-enabled (3-State) 4.5 - 5.5 ±4 22 -40~125 • • 74HC253-Q100 Dual 4-input multiplexer (3-State) 2.0 - 6.0 ± 7.8 17 -40~125 • 74HCT253-Q100 Dual 4-input multiplexer; TTL-enabled (3-State) 4.5 - 5.5 ±6 17 -40~125 • 74LVC157A-Q100 Quad 2-input multiplexer 1.2 - 3.6 ± 24 2.5 -40~125 • • • • SOT339-1 (DB) SOT362-1 (DGG) SOT338-1 (DB) Type number IO (mA) Package (suffix) VCC (V) Features Flip-flops (cont.) • 74AHCT74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • • • 74AHC273-Q100 Octal D-type flip-flop with reset; positive-edge trigger 2.0 - 5.5 ±8 4.2 -40~125 74AHCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±8 74AHC374-Q100 Octal D-type flip-flop; positiveedge trigger 2.0 - 5.5 74AHCT374-Q100 Octal D-type flip-flop; positiveedge trigger (3-state); TTL-enabled (3-state) 74AHC377-Q100 Octal D-type flip-flop with data enable; positive-edge trigger NXP Logic selection guide 2016 SOT764-1 (BQ) • 112 SOT360-1 (PW) • • • • -40~125 • • • ±8 4.4 -40~125 • • 4.5 - 5.5 ±8 4.3 -40~125 • • 2.0 - 5.5 ±8 3.9 -40~125 4 SOT163-1 (D) 3.7 -40~125 SOT403-1 (PW) ±8 SOT162-1 (D) SOT762-1 (BQ) 2.0 - 5.5 SOT109-1 (D) SOT402-1 (PW) Dual D-type flip-flop with set and reset; positive-edge trigger SOT337-1 (DB) tpd (ns) 74AHC74-Q100 SOT108-1 (D) Description Tamb (°C) Type number IO (mA) Package (suffix) VCC (V) Features • Flip-flops (cont.) 74AHCT377-Q100 Octal D-type flip-flop with data enable; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±8 4 -40~125 74AVC16374-Q100 16-bit D-type flip-flop; positive-edge trigger (3-state) 1.2 - 3.6 ± 12 1.5 -40~85 74HC74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger 2.0 - 6.0 ± 5.2 14 -40~125 • • • 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±4 15 -40~125 • • • 74HC107-Q100 Dual J-K flip-flop with reset; negative-edge trigger 2.0 - 6.0 ± 5.2 16 -40~125 • • 74HCT107-Q100 Dual J-K flip-flop with reset; negative-edge trigger; TTL-enabled 4.5 - 5.5 ±4 16 -40~125 • 74HC174-Q100 Hex D-type flip-flop with reset; positive-edge trigger 2.0 - 6.0 ± 5.2 17 -40~125 • • 74HCT174-Q100 Hex D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±4 18 -40~125 • • 74HC175-Q100 Quad D-type flip-flop with reset; positive-edge trigger 2.0 - 6.0 ± 5.2 17 -40~125 • • 74HCT175-Q100 Quad D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±4 16 -40~125 • • 74HC273-Q100 Octal D-type flip-flop with reset; positive-edge trigger 2.0 - 6.0 ± 5.2 15 -40~125 • • • 74HCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±4 15 -40~125 • • • 74HC377-Q100 Octal D-type flip-flop with data enable; positive-edge trigger 2.0 - 6.0 ± 7.8 13 -40~125 • • • 74HCT377-Q100 Octal D-type flip-flop with data enable; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±6 14 -40~125 • • • 74HC574-Q100 Octal D-type flip-flop; positiveedge trigger (3-state) 2.0 - 6.0 ± 7.8 14 -40~125 • • 74HCT574-Q100 Octal D-type flip-flop; positiveedge trigger; TTL-enabled (3-state) 4.5 - 5.5 ±6 15 -40~125 • • 74LV74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger 1.0 - 5.5 ± 12 11 -40~125 • SOT362-1 (DGG) SOT764-1 (BQ) SOT360-1 (PW) SOT339-1 (DB) SOT163-1 (D) SOT403-1 (PW) SOT162-1 (D) Tamb (°C) SOT109-1 (D) tpd (ns) SOT762-1 (BQ) Description IO (mA) SOT402-1 (PW) Type number VCC (V) SOT337-1 (DB) Package (suffix) SOT108-1 (D) Features • • • • NXP Logic selection guide 2016 113 Flip-flops (cont.) SOT764-1 (BQ) SOT362-1 (DGG) SOT360-1 (PW) 3.4 -40~125 • • • 1.2 - 3.6 ± 24 3.8 -40~125 • 1.2 - 3.6 ± 24 3.8 -40~125 • Octal D-type flip-flop; positiveedge trigger (3-state) 1.2 - 3.6 74LVC573A-Q100 Octal D-type transparent latch (3-state) 74LVC16374A-Q100 16-bit D-type flip-flop; positive-edge trigger (3-state) HEF4013B-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger 4.5 - 15.5 ± 2.4 30 -40~85 HEF4027B-Q100 Dual J-K flip-flop 4.5 - 15.5 ± 2.4 30 -40~85 • SOT163-1 (D) 74LVC374A-Q100 6 SOT339-1 (DB) ± 24 ± 24 • SOT403-1 (PW) 1.2 - 3.6 1.2 - 3.6 • SOT162-1 (D) • Octal D-type flip-flop with reset; positive-edge trigger • SOT109-1 (D) • 74LVC273-Q100 2.5 -40~125 SOT762-1 (BQ) • ± 24 SOT337-1 (DB) 2.7 -40~125 1.2 - 3.6 SOT108-1 (D) ± 24 Dual D-type flip-flop with set and reset; positive-edge trigger Tamb (°C) • 74LVC74A-Q100 tpd (ns) • IO (mA) • Description VCC (V) -40~125 Type number 16-bit D-type flip-flop with bus 74LVCH16374A-Q100 hold; positive-edge trigger (3-state) Package (suffix) SOT402-1 (PW) Features • • Gates (cont.) Description tpd (ns) Tamb (°C) SOT108-1 (D) SOT402-1 (PW) SOT762-1 (BQ) 74AHC00-Q100 Quad 2-input NAND gate 2.0 - 5.5 ±8 3.2 -40~125 • • • 74AHCT00-Q100 Quad 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • • • 74AHC02-Q100 Quad 2-input NOR gate 2.0 - 5.5 ±8 2.9 -40~125 • • • 74AHCT02-Q100 Quad 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±8 3.8 -40~125 • • • 74AHC08-Q100 Quad 2-input AND gate 2.0 - 5.5 ±8 3.5 -40~125 • • • 74AHCT08-Q100 Quad 2-input AND gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • • 74AHC30-Q100 8-input NAND gate 2.0 - 5.5 ±8 3.6 -40~125 • • • 74AHCT30-Q100 8-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • • • 74AHC32-Q100 Quad 2-input OR gate 2.0 - 5.5 ±8 3.5 -40~125 • • • 74AHCT32-Q100 Quad 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • • 74AHC86-Q100 Quad 2-input EXCLUSIVE-OR gate 2.0 - 5.5 ±8 3.4 -40~125 • • • 74AHCT86-Q100 Quad 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ±8 3.4 -40~125 • • • 114 NXP Logic selection guide 2016 SOT337-1 (DB) Type number IO (mA) Package (suffix) VCC (V) Features Gates (cont.) Description tpd (ns) Tamb (°C) SOT108-1 (D) SOT402-1 (PW) SOT762-1 (BQ) 74ALVC00-Q100 Quad 2-input NAND gate 1.65-3.6 ± 24 2.1 -40~85 • • • 74ALVC32-Q100 Quad 2-input OR gate 1.65 - 3.6 ± 24 2 -40~125 • • • 74HC00-Q100 Quad 2-input NAND gate 2.0 - 6.0 ± 5.2 7 -40~125 • • • 74HCT00-Q100 Quad 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 10 -40~125 • • • 74HC02-Q100 Quad 2-input NOR gate 2.0 - 6.0 ± 5.2 7 -40~125 • • • 74HCT02-Q100 Quad 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±4 9 -40~125 • • • 74HC03-Q100 Quad 2-input NAND gate; open-drain 2.0 - 6.0 5.2 8 -40~125 • 74HCT03-Q100 Quad 2-input NAND gate; open-drain; TTL-enabled 4.5 - 5.5 ±4 10 -40~125 • • 74HC08-Q100 Quad 2-input AND gate 2.0 - 6.0 ± 5.2 7 -40~125 • • • 74HCT08-Q100 Quad 2-input AND gate; TTL-enabled 4.5 - 5.5 ±4 11 -40~125 • • • 74HC10-Q100 Triple 3-input NAND gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT10-Q100 Triple 3-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 11 -40~125 • • 74HC11-Q100 Triple 3-input AND gate 2.0 - 6.0 ± 5.2 10 -40~125 • • 74HCT11-Q100 Triple 3-input AND gate; TTL-enabled 4.5 - 5.5 ±4 11 -40~125 • • 74HC20-Q100 Dual 4-input NAND gate 2.0 - 6.0 ± 5.2 8 -40~125 • • 74HCT20-Q100 Dual 4-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 13 -40~125 • 74HC27-Q100 Triple 3-input NOR gate 2.0 - 6.0 ± 5.2 8 -40~125 • • • 74HCT27-Q100 Triple 3-input NOR gate; TTL-enabled 4.5 - 5.5 ±4 10 -40~125 • • • 74HC30-Q100 8-input NAND gate 2.0 - 6.0 ± 5.2 12 -40~125 • • 74HCT30-Q100 8-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 12 -40~125 • • 74HC32-Q100 Quad 2-input OR gate 2.0 - 6.0 ± 5.2 6 -40~125 • • • 74HCT32-Q100 Quad 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 4.0 9 -40~125 • • • 74HC86-Q100 Quad 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 5.2 11 -40~125 • • 74HCT86-Q100 Quad 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ±4 14 -40~125 • • 74HC4002-Q100 Dual 4-input NOR gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HC4075-Q100 Triple 3-input OR gate 2.0 - 6.0 ± 5.2 8 -40~125 • • 74HCT4075-Q100 Triple 3-input OR gate; TTL-enabled 4.5 - 5.5 ±4 10 -40~125 • • 74LV08-Q100 Quad 2-input AND gate 1.0 - 5.5 ± 12 7 -40~125 • • 74LVC00A-Q100 Quad 2-input NAND gate 1.2 - 3.6 ± 24 2.1 -40~125 • • • 74LVC02A-Q100 Quad 2-input NOR gate 1.2 - 3.6 ± 24 2.1 -40~125 • • • 74LVC08A-Q100 Quad 2-input AND gate 1.2 - 3.6 ± 24 2.1 -40~125 • • • 74LVC32A-Q100 Quad 2-input OR gate 1.2 - 3.6 ± 24 2.1 -40~125 • • • 74VHC02-Q100 Quad 2-input NOR gate 2.0 - 5.5 ±8 2.9 -40~125 • • • 74VHCT02-Q100 Quad 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±8 3.8 -40~125 • • • SOT337-1 (DB) Type number IO (mA) Package (suffix) VCC (V) Features • • • • NXP Logic selection guide 2016 115 Gates (cont.) Tamb (°C) SOT108-1 (D) 74VHC08-Q100 Quad 2-input AND gate 2.0 - 5.5 ±8 3.5 -40~125 • • 74VHCT08-Q100 Quad 2-input AND gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • 74VHC32-Q100 Quad 2-input OR gate 2.0 - 5.5 ±8 3.5 -40~125 • • 74VHCT32-Q100 Quad 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • • HEF4001B-Q100 Quad 2-input NOR gate 4.5 - 15.5 ± 2.4 20 -40~85 • HEF4011B-Q100 Quad 2-input NAND gate 4.5 - 15.5 ± 2.4 20 -40~85 • HEF4030B-Q100 Quad 2-input EXCLUSIVE-OR gate 4.5 - 15.5 ± 2.4 30 -40~85 • HEF4070B-Q100 Quad 2-input EXCLUSIVE-OR gate 4.5 - 15.5 ± 2.4 30 -40~85 • HEF4081B-Q100 Quad 2-input AND gate 4.5 - 15.5 ± 2.4 20 -40~85 • SOT362-1 (DGG) SOT762-1 (BQ) Description tpd (ns) SOT402-1 (PW) Type number IO (mA) SOT337-1 (DB) Package (suffix) VCC (V) Features • Latches/registered drivers SOT360-1 (PW) SOT764-1 (BQ) ±8 4.2 -40~125 • • • 74AHCT573-Q100 Octal D-type transparent latch; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.9 -40~125 • • • 74HC4060-Q100 14-stage binary ripple counter with oscillator 2.0 - 6.0 ± 5.2 31 -40~125 • 74HC259-Q100 8 bit addressable latch 2.0 - 6.0 ± 5.2 18 -40~125 • • • 74HCT259-Q100 8-Bit addressable latch; TTL-enabled 4.5 - 5.5 ±4 20 -40~125 • • • 74HC373-Q100 Octal D-type transparent latch (3-state) 2.0 - 6.0 ± 7.8 12 -40~125 • • • 74HCT373-Q100 Octal D-type transparent latch; TTL-enabled (3-state) 4.5 - 5.5 ±6 14 -40~125 • • • 74HC573-Q100 Octal D-type transparent latch (3-state) 2.0 - 6.0 ± 7.8 14 -40~125 • • • 74HCT573-Q100 Octal D-type transparent latch; TTL-enabled (3-state) 4.5 - 5.5 ±6 17 -40~125 • • • 74LVC373A-Q100 Octal D-type transparent latch (3-state) 1.2 - 3.6 ± 24 3 -40~125 • • • 74LVC16373A-Q100 16-bit D-type transparent latch (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 • 74LVCH16373A-Q100 16-bit D-type transparent latch with bushold (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 • HEF4043B-Q100 Quad R/S latch with set and reset (3-state) 4.5 - 15 ± 2.4 25 -40~85 116 NXP Logic selection guide 2016 SOT339-1 (DB) 2.0 - 5.5 SOT163-1 (D) Tamb (°C) Octal D-type transparent latch (3-state) SOT763-1 (BQ) tpd (ns) 74AHC573-Q100 • SOT403-1 (PW) Description SOT109-1 (D) Type number IO (mA) Package (suffix) VCC (V) Features • • Level shifters/translators -40~125 74AVC4T245-Q100 4-bit dual-supply voltage level translating transceiver (3-state) 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 74AVC8T245-Q100 8-bit dual-supply voltage level translating transceiver (3-state) 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 74AVC16T245-Q100 16-bit dual-supply voltage level translating transceiver (3-state) 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 74AVCH4T245-Q100 4-bit dual-supply voltage translating transceiver with bus hold (3-state) 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 • • 74HC4050-Q100 Hex buffer with 15V tolerant inputs 2.0 - 6.0 ± 5.2 -40~125 • • 74LVC4245A-Q100 8-bit dual-supply voltage translating transceiver (3-state) 1.5 - 5.5 1.5 - 3.6 ± 24 -40~125 74LVC8T245-Q100 8-bit dual-supply voltage translating transceiver (3-state) 1.2 - 5.5 1.2 - 5.5 ± 24 74LVCH8T245-Q100 8-bit dual-supply voltage translating transceiver with bus hold (3-state) 1.2 - 5.5 1.2 - 5.5 HEF4104B-Q100 Quad low-to-high voltage translator (3-state) 3.0 15.0 n.a 3.0 15.0 SOT480-1 (DGV) ± 24 SOT362-1 (DGG) 1.5 - 3.6 1.5 - 5.5 SOT815-1 (BQ) 16-bit dual-supply voltage level translating transceiver (3-state) SOT355-1 (PW) 74ALVC164245-Q100 SOT137-1 (D) Description SOT763-1 (BQ) SOT403-1 (PW) Type number Tamb (°C) SOT109-1 (D) Package (suffix) IO (mA) VCC(B) (V) VCC(A) (V) Features • • • • • • • • • • • -40~125 • • ± 24 -40~125 • • ± 2.4 -40~85 • Multivibrators Type number Description IO (mA) tpd (ns) Tamb (°C) SOT109-1 (D) SOT403-1 (PW) SOT763-1 (BQ) Package (suffix) VCC (V) Features 74AHC123A-Q100 Dual retriggerable monostable multivibrator with reset 2.0 - 5.5 ±8 5.1 -40~125 • • • 74AHCT123A-Q100 Dual retriggerable monostable multivibrator with reset; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • • 74HC123-Q100 Dual retriggerable monostable multivibrator with reset 2.0 - 6.0 ± 7.8 9 -40~125 • • • 74HCT123-Q100 Dual retriggerable monostable multivibrator with reset; TTL-enabled 4.5 - 5.5 ±4 26 -40~125 • • 74HC4538-Q100 Dual retriggerable precision monostable multivibrator 2.0 - 6.0 ± 5.2 27 -40~125 • • 74HCT4538-Q100 Dual retriggerable precision monostable multivibrator; TTL-enabled 4.5 - 5.5 ±4 30 -40~125 • • HEF4538B-Q100 Dual retriggerable precision monostable multivibrator 4.5 - 15.5 ± 2.4 60 -40~85 • NXP Logic selection guide 2016 117 Schmitt triggers Type number Description IO (mA) tpd (ns) Tamb (°C) SOT108-1 (D) SOT402-1 (PW) SOT762-1 (BQ) SOT163-1 (D) SOT360-1 (PW) 74AHC14-Q100 Hex inverter Schmitt trigger 2.0 - 5.5 ±8 3.2 -40~125 • • • 74AHCT14-Q100 Hex inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 4 -40~125 • • • 74AHC132-Q100 Quad 2-input NAND gate Schmitt trigger 2.0 - 5.5 ±8 3.3 -40~125 • • • 74AHCT132-Q100 Quad 2-input NAND gate Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 3.5 -40~125 • • • 74HC7014-Q100 Hex buffer precision Schmitt trigger 2.0 - 6.0 ± 5.2 27 -40~125 • 74HC14-Q100 Hex inverter Schmitt trigger 2.0 - 6.0 ± 5.2 12 -40~125 • • • 74HCT14-Q100 Hex inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±4 17 -40~125 • • • 74HC132-Q100 Quad 2-input NAND gate Schmitt trigger 2.0 - 6.0 ± 5.2 11 -40~125 • • 74HCT132-Q100 Quad 2-input NAND gate Schmitt trigger; TTL-enabled 4.5 - 5.5 ±4 17 -40~125 • • 74HC7541-Q100 Octal buffer/line driver Schmitt trigger (3-State) 2.0 - 6.0 ± 7.8 11 -40~125 • • 74HCT7541-Q100 Octal buffer/line driver Schmitt trigger; TTL-enabled (3-State) 4.5 - 5.5 ±6 16 -40~125 • • 74LV132-Q100 Quad 2-input NAND gate Schmitt trigger 1.0 - 5.5 ± 12 10 -40~125 • • • 74LVC14A-Q100 Hex inverter Schmitt trigger 1.2 - 3.6 ± 24 3.2 -40~125 • • • 74LVC132A-Q100 Quad 2-input NAND gate Schmitt trigger 1.2 - 3.6 ± 24 3.4 -40~125 • • • HEF40106B-Q100 Hex inverter Schmitt trigger 4.5 - 15.5 ± 2.4 30 -40~85 • • SOT163-1 (D) SOT360-1 (PW) Package (suffix) VCC (V) Features Shift registers (cont.) Type number Description IO (mA) tpd (ns) Tamb (°C) SOT108-1 (D) SOT402-1 (PW) SOT762-1 (BQ) SOT109-1 (D) SOT338-1 (DB) SOT403-1 (PW) SOT763-1 (BQ) Package (suffix) VCC (V) Features 74AHC164-Q100 8-bit serial-in/parallel-out shift register 2.0 - 5.5 ±8 4.5 -40~125 • • • 74AHCT164-Q100 8-bit serial-in/parallel-out shift register; TTL-enabled 4.5 - 5.5 ±8 3.4 -40~125 • • • 74AHC594-Q100 8-bit serial-in/parallel-out shift register with output register 2.0 - 5.5 ±8 4.1 -40~125 • • • • 74AHCT594-Q100 8-bit serial-in/parallel-out shift register with output register; TTL-enabled 4.5 - 5.5 ±8 3.8 -40~125 • • • • 74AHC595-Q100 8-bit serial-in/parallel-out shift register with output register (3-state) 2.0 - 5.5 ±8 4 -40~125 • • • 74AHCT595-Q100 8-bit serial-in/parallel-out shift register with output storage; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.8 -40~125 • • • 74HC164-Q100 8-bit serial-in/parallel-out shift register 2.0 - 6.0 ± 5.2 12 -40~125 118 NXP Logic selection guide 2016 • • • Shift registers (cont.) SOT108-1 (D) SOT402-1 (PW) SOT762-1 (BQ) SOT403-1 (PW) SOT763-1 (BQ) 4.5 - 5.5 ±4 12 -40~125 • • • 74HC165-Q100 8-bit parallel or serial-in/serial-out shift register 2.0 - 6.0 ± 5.2 16 -40~125 • • • 74HCT165-Q100 8-bit parallel or serial-in/serial-out shift register; TTL-enabled 4.5 - 5.5 ±4 14 -40~125 • • • 74HC166-Q100 8-bit parallel or serial-in/serial-out shift register 2.0 - 6.0 ± 5.2 15 -40~125 • • 74HCT166-Q100 8-bit parallel or serial-in/serial-out shift register; TTL-enabled 4.5 - 5.5 ±4 23 -40~125 • 74HC594-Q100 8-bit serial-in/parallel-out shift register with output storage register 2.0 - 6.0 ± 7.8 14 -40~125 • 74HCT594-Q100 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled 4.5 - 5.5 ±6 15 -40~125 • 74HC595-Q100 8-bit serial-in/parallel-out shift register with output storage register (3-state) 2.0 - 6.0 ± 7.8 16 -40~125 • 74HCT595-Q100 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) 4.5 - 5.5 ±6 25 -40~125 74HC597-Q100 8-bit parallel or serial-in/parallel-out shift register with parallel input register 2.0 - 6.0 ± 5.2 16 74HCT597-Q100 8-bit parallel or serial-in/parallel-out shift register with parallel input register; TTL-enabled 4.5 - 5.5 ±4 74HC4094-Q100 8-bit serial-in/serial or parallel-out shift register with output register (3-state) 2.0 - 6.0 74HCT4094-Q100 8-bit serial-in/serial or parallel-out shift register with output register; TTL-enabled (3-state) 74LV164-Q100 • • • • • -40~125 • • 20 -40~125 • ± 5.2 15 -40~125 • • 4.5 - 5.5 ±4 19 -40~125 • • 8-bit serial-in/parallel-out shift register 1.0 - 5.5 ± 12 12 -40~125 74LV165-Q100 8-bit parallel or serial-in/serial-out shift register 1.0 - 5.5 ± 12 18 -40~125 • • 74LV165A-Q100 8-bit parallel or serial-in/serial-out shift register 1.0 - 5.5 ± 12 7.5 -40~125 • • 74LV4060-Q100 14-stage binary ripple counter with oscillator 1.0 - 5.5 ±6 29 -40~125 • • 74LVC594A-Q100 8-bit serial-in/parallel-out shift register with output storage register 1.2 - 5.5 ± 24 3.1 -40~125 • • • 74VHC595-Q100 8-bit serial-in/parallel-out shift register with output storage register (3-state) 2.0 - 5.5 ±8 4 -40~125 • • • 74VHCT595-Q100 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.8 -40~125 • • • HEF4014B-Q100 8-bit shift register with synchronous parallel enable 4.5 - 15 ± 2.4 40 -40~85 • • • • SOT360-1 (PW) Tamb (°C) 8-bit serial-in/parallel-out shift register; TTL-enabled SOT163-1 (D) tpd (ns) 74HCT164-Q100 SOT338-1 (DB) Description SOT109-1 (D) Type number IO (mA) Package (suffix) VCC (V) Features • • NXP Logic selection guide 2016 119 Shift registers (cont.) 8-bit shift register with asynchronous parallel 4.5 - 15 load ± 2.4 40 -40~85 • • HEF4094B-Q100 8-bit serial-in/serial or parallel-out shift register with output register (3-state) 4.5 - 15 ± 2.4 50 -40~85 • • HEF4794B-Q100 8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) 4.5 - 15 -20 45 -40~85 • HEF4894B-Q100 12-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) 4.5 - 15 -20 45 -40~85 NPIC6C595-Q100 8-bit serial-in/parallel-out shift register with output storage register (3-state) 4.5 - 5.5 -100 90 -40~125 • • • NPIC6C596-Q100 8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state) 4.5 - 5.5 -100 90 -40~125 • • • 8-bit serial-in/serial or parallel-out shift NPIC6C596A-Q100 register with output register LED driver (3-state) 2.3 - 5.5 -100 90 -40~125 • • • 12-bit serial-in/serial or parallel-out shift NPIC6C4894-Q100 register with output register LED driver (3-state) 4.5 - 5.5 -100 105 -40~125 SOT360-1 (PW) HEF4021B-Q100 SOT163-1 (D) SOT763-1 (BQ) SOT403-1 (PW) SOT338-1 (DB) Tamb (°C) SOT109-1 (D) tpd (ns) SOT762-1 (BQ) Description VCC (V) Type number IO (mA) SOT402-1 (PW) Package (suffix) SOT108-1 (D) Features • • • • Transceivers Description tpd (ns) Tamb (°C) SOT163-1 (D) SOT360-1 (PW) SOT764-1 (BQ) 74AHC245-Q100 Octal transceiver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • • 74AHCT245-Q100 Octal transceiver; TTL-enabled (3-state) 4.5 - 5.5 ±8 5 -40~125 • • • 74AVC16245-Q100 16-bit transceiver (3-state) 1.2 - 3.6 ± 12 2 -40~85 74HC245-Q100 Octal transceiver (3-state) 2.0 - 6.0 ± 7.8 7 -40~125 • • • 74HCT245-Q100 Octal transceiver; TTL-enabled (3-state) 4.5 - 5.5 ±6 10 -40~125 • • • 74LVC245A-Q100 Octal transceiver (3-state) 1.2 - 3.6 ± 24 2.9 -40~125 • • • 74LVCH245A-Q100 Octal transceiver with bus hold (3-state) 1.2 - 3.6 ± 24 2.9 -40~125 • • • 74LVC16245A-Q100 16-bit transceiver (3-state) 1.2 - 3.6 ± 24 3 -40~125 • • 74LVCH16245A-Q100 16-bit transceiver with bus hold (3-state) 1.2 - 3.6 ± 24 3 -40~125 • • 120 NXP Logic selection guide 2016 SOT702-1 (EV) Type number IO (mA) SOT362-1 (DGG) Package (suffix) VCC (V) Features • Standard logic packages Package suffix D DB PW BQ D DB PW BQ 14-pin 14-pin 14-pin 14-pin 16-pin 16-pin 16-pin 16-pin SOT108-1 SOT337-1 SOT402-1 SOT762-1 SOT109-1 SOT338-1 SOT403-1 SOT763-1 Width (mm) 6.00 7.75 6.40 2.50 6.00 7.75 6.40 2.50 Length (mm) 8.65 6.20 5.00 3.00 9.90 6.20 5.00 3.50 Height (mm) 1.75 2.00 1.10 1.00 1.75 2.00 1.10 1.00 Pitch (mm) 1.27 0.65 0.65 0.50 1.27 0.65 0.65 0.50 D DB PW BQ D PW DGG EV 20-pin 20-pin 20-pin 20-pin 24-pin 24-pin 48-pin 56-pin SOT163-1 SOT339-1 SOT360-1 SOT764-1 SOT137-1 SOT355-1 SOT362-1 SOT702-1 Width (mm) 10.30 7.75 6.40 2.50 10.30 6.40 8.10 4.50 Length (mm) 12.80 7.20 6.50 4.50 15.40 7.80 12.50 7.00 Height (mm) 2.65 2.00 1.10 1.00 2.65 1.10 1.20 1.00 Pitch (mm) 1.27 0.65 0.65 0.5 1.27 0.65 0.50 0.65 Package Package suffix Package Note: The HEF4000B family uses different package suffixes than the other families. Package suffix D corresponds to HEF4000B package suffix T, DB to TS and PW to TT. NXP Logic selection guide 2016 121 Q100 Mini Logic functions & packages Mini logic functions are small footprint logic devices with 10 pins or less suitable for use at supply voltage between 1.1 V to 6.0 V. They provide a wide range of functions including analog switches, buffers/inverters, bus switches, decoders/demultiplexers, multiplexers, flip-flops, gates, configurable logic and level shifters. Q100 Mini logic functions are available in leaded TSSOP and VSSOP packages as well as innovative leadless XSON packages. Analog switches Description RON (W) RON(FLAT) (W) Tamb (°C) SOT353-1 (GW) SOT753 (GV) SOT505-2 (DP) SOT765-1 (DC) 74AHC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 2.0 - 5.5 40 5 -40~125 • • 74AHCT1G66-Q100 Single-pole, single-throw analog switch; TTL-enabled SPST-NO 4.5 - 5.5 40 5 -40~125 • • 74HC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 2.0 - 9.0 105 23 -40~125 • • 74HCT1G66-Q100 Single-pole, single-throw analog switch; TTL-enabled SPST-NO 4.5 - 5.5 118 23 -40~125 • • 74HC2G66-Q100 Dual single-pole, single-throw analog switch SPST-NO 2.0 - 9.0 105 23 -40~125 • • 74HCT2G66-Q100 Dual single-pole, single-throw analog switch; TTL-enabled SPST-NO 4.5 - 5.5 118 23 -40~125 • • 74LVC1G53-Q100 Single-pole, double-throw analog switch SPDT-Z 1.65 - 5.5 15 1.5 -40~125 • • 74LVC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • • 74LVC1G384-Q100 Single-pole, single-throw analog switch SPST-NC 1.65 - 5.5 15 1.5 -40~125 • • 74LVC1G3157-Q100 Single-pole, double-throw analog switch 1.65 - 5.5 15 1.5 -40~125 74LVC2G66-Q100 Dual single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • • SPDT SOT457 (GV) SOT363 (GW) Type number VCC (V) Package (suffix) Configuration Features • • Bus switches 122 NXP Logic selection guide 2016 SOT96-1 (D) SOT530-1 (PW) Dual bus switch Tamb (°C) CBT3306-Q100 RON (W) Description VPASS (V) Type number Package (suffix) VCC (V) Features 4.5 - 5.5 3.9 7 -40~85 • • Buffers/inverters (cont.) Tamb (°C) SOT353-1 (GW) SOT753 (GV) Single inverter; unbuffered 2.0 - 5.5 ±8 2.6 -40~125 • • 74AHC3GU04-Q100 Triple inverter; unbuffered 2.0 - 5.5 ±8 2.5 -40~125 74AHC1G04-Q100 Single inverter 2.0 - 5.5 ±8 3.1 -40~125 • • 74AHCT1G04-Q100 Single inverter; TTL-enabled 4.5 - 5.5 ±8 3.4 -40~125 • • 74AHC1G07-Q100 Single buffer; open-drain 2.0 - 5.5 8 4.2 -40~125 • • 74AHC1G125-Q100 Single buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • • 74AHCT1G125-Q100 Single buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.4 -40~125 • • 74AHC1G126-Q100 Single buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • • 74AHCT1G126-Q100 Single buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.4 -40~125 • • 74AHC2G125-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 74AHCT2G125-Q100 Dual buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 74AHC2G126-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 74AHCT2G126-Q100 Dual buffer/line driver; TTL-enabled (3-state) 74AHC2G241-Q100 -40~125 • • 3.4 -40~125 • • ±8 3.4 -40~125 • • 4.5 - 5.5 ±8 3.4 -40~125 • • Dual buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • • 74AHCT2G241-Q100 Dual buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ±8 3.4 -40~125 • • 74AHC3G04-Q100 Triple inverter 2.0 - 5.5 ±8 3.1 -40~125 • • 74AHCT3G04-Q100 Triple inverter; TTL-enabled 4.5 - 5.5 ±8 3 -40~125 • • 74AUP1G04-Q100 Single inverter 1.1 - 3.6 ± 1.9 4 -40~125 • 74AUP1G06-Q100 Single inverter; open-drain 1.1 - 3.6 1.9 4.5 -40~125 • 74AUP1G34-Q100 Single buffer 1.1 - 3.6 ± 1.9 3.9 -40~125 • 74AUP1G125-Q100 Single buffer/line driver (3-state) 1.1 - 3.6 ± 1.9 4.3 -40~125 • 74AUP2GU04-Q100 Dual inverter; unbuffered 1.1 - 3.6 ± 1.9 2.3 -40~125 74HC1GU04-Q100 Single inverter; unbuffered 2.0 - 6.0 ± 2.6 5 -40~125 74HC2GU04-Q100 Dual inverter; unbuffered 2.0 - 6.0 ± 5.2 5 -40~125 74HC3GU04-Q100 Triple inverter; unbuffered 2.0 - 6.0 ± 5.2 6 -40~125 • • 74HC1G04-Q100 Single inverter 2.0 - 6.0 ± 2.6 7 -40~125 • • 74HCT1G04-Q100 Single inverter; TTL-enabled 4.5 - 5.5 ± 2.0 8 -40~125 • • 74HC1G125-Q100 Single buffer/line driver (3-state) 2.0 - 6.0 ± 2.6 9 -40~125 • • 74HCT1G125-Q100 Single buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 2.0 10 -40~125 • • 74HC2G04-Q100 Dual inverter 2.0 - 6.0 ± 5.2 8 -40~125 • • 74HCT2G04-Q100 Dual inverter; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • • 74HC2G34-Q100 Dual buffer 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G34-Q100 Dual buffer; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • • 74HC2G125-Q100 Dual buffer/line driver (3-state) 2.0 - 6.0 ± 5.2 10 -40~125 • • SOT457 (GV) • SOT363 (GW) • SOT996-2 (GD) tpd (ns) 74AHC1GU04-Q100 SOT765-1 (DC) Description SOT505-2 (DP) Type number IO (mA) Package (suffix) VCC (V) Features • • • • • • NXP Logic selection guide 2016 123 Buffers/inverters (cont.) tpd (ns) Tamb (°C) SOT505-2 (DP) SOT765-1 (DC) Dual buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 4.0 12 -40~125 • • 74HC3G04-Q100 Triple inverter 2.0 - 6.0 ± 5.2 8 -40~125 • • • 74HCT3G04-Q100 Triple inverter; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • • • 74HC3G07-Q100 Triple buffer; open-drain 2.0 - 6.0 5.2 9 -40~125 • • 74HCT3G07-Q100 Triple buffer; open-drain; TTL-enabled 4.5 - 5.5 4 9 -40~125 • • 74HC3G34-Q100 Triple buffer 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT3G34-Q100 Triple buffer; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 74LVC1G04-Q100 Single inverter 1.65 5.5 ± 32 2 -40~125 • • 74LVC1G06-Q100 Single inverter; open-drain 1.65 5.5 32 2.3 -40~125 • • 74LVC1G07-Q100 Single buffer; open-drain 1.65 5.5 32 2.2 -40~125 • • 74LVC1G34-Q100 Single buffer 1.65 5.5 ± 32 2 -40~125 • • 74LVC1G125-Q100 Single buffer/line driver (3-state) 1.65 5.5 ± 32 2.1 -40~125 • • 74LVC1G126-Q100 Single buffer/line driver (3-state) 1.65 5.5 ± 32 2 -40~125 • • 74LVC1GU04-Q100 Single inverter; unbuffered 1.65 5.5 ± 32 1.6 -40~125 • • 74LVC2G04-Q100 Dual inverter 1.65 5.5 ± 32 2.7 -40~125 • • 74LVC2G06-Q100 Dual inverter; open-drain 1.65 5.5 32 2.3 -40~125 • • 74LVC2G07-Q100 Dual buffer; open-drain 1.65 5.5 32 2.6 -40~125 • • 74LVC2G125-Q100 Dual buffer/line driver (3-state) 1.65 5.5 ± 32 2.3 -40~125 • • 74LVC2G240-Q100 Dual inverter/line driver (3-state) 1.65 5.5 ± 32 2.5 -40~125 • • 74LVC2G241-Q100 Dual buffer/line driver (3-state) 1.65 5.5 ± 32 2.6 -40~125 • • 74LVC2GU04-Q100 Dual inverter; unbuffered 1.65 5.5 ± 32 2.3 -40~125 74LVC3G04-Q100 Triple inverter 1.65 5.5 ± 32 2.7 -40~125 • • 74LVC3G07-Q100 Triple buffer; open-drain 1.65 5.5 32 2.1 -40~125 • • 74LVC3G34-Q100 Triple buffer 1.65 5.5 ± 32 2.2 -40~125 • • 124 NXP Logic selection guide 2016 SOT457 (GV) IO (mA) 74HCT2G125-Q100 SOT363 (GW) Description SOT753 (GV) Type number VCC (V) SOT996-2 (GD) Package (suffix) SOT353-1 (GW) Features • • • Digital decoders/demultiplexers Package (suffix) SOT363 (GW) SOT457 (GV) 1-to-2 demultiplexer (3-state) Tamb (°C) 74LVC1G18-Q100 tpd (ns) Description IO (mA) Type number VCC (V) Features 1.65 - 5.5 ± 32 2.3 -40~125 • • Digital multiplexers SOT363 (GW) SOT457 (GV) Single 2-input multiplexer Tamb (°C) 74LVC1G157-Q100 tpd (ns) Description IO (mA) Type number Package (suffix) VCC (V) Features 1.65 - 5.5 ± 32 2.2 -40~125 • • Flip-flops SOT753 (GV) ±8 3.5 -40~125 • • 74AHCT1G79-Q100 Single D-type flip-flop; positive-edge trigger; TTL-enabled 4.5 - 5.5 ±8 3.5 -40~125 • • 74AUP1G175-Q100 Single D flip-flop with reset; positive-edge trigger 1.1 - 3.6 ± 1.9 7.4 -40~125 • 74AUP1G374-Q100 Single D-type flip-flop; positive-edge trigger (3-state) 1.1 - 3.6 ± 1.9 7.9 -40~125 • 74AUP2G79-Q100 Dual D-type flip-flop; positive-edge trigger 1.1 - 3.6 ± 1.9 8.5 -40~125 74LVC1G74-Q100 Single D-type flip-flop with set and reset; positiveedge trigger 1.65 - 5.5 ± 32 3.5 -40~125 74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger 1.65 - 5.5 ± 32 2.4 -40~125 74LVC1G175-Q100 Single D flip-flop with reset; positive-edge trigger 1.65 - 5.5 ± 32 3.1 -40~125 74LVC2G74-Q100 Single D-type flip-flop with set and reset; positiveedge trigger 1.65 - 5.5 ± 32 3.5 -40~125 SOT996-2 (GD) SOT353-1 (GW) 2.0 - 5.5 SOT765-1 (DC) Tamb (°C) Single D-type flip-flop; positive-edge trigger SOT505-2 (DP) tpd (ns) 74AHC1G79-Q100 SOT457 (GV) Description SOT363 (GW) Type number IO (mA) Package (suffix) VCC (V) Features • • • • • • • • • • NXP Logic selection guide 2016 125 Gates (cont.) tpd (ns) Tamb (°C) SOT353-1 (GW) SOT753 (GV) SOT505-2 (DP) SOT765-1 (DC) 74AHC1G09-Q100 Single 2-input AND gate; open-drain 2.0 - 5.5 ±8 3.2 -40~125 • • 74AHC1G00-Q100 Single 2-input NAND gate 2.0 - 5.5 ±8 3.5 -40~125 • • 74AHCT1G00-Q100 Single 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • • 74AHC1G02-Q100 Single 2-input NOR gate 2.0 - 5.5 ±8 3.2 -40~125 • • 74AHCT1G02-Q100 Single 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±8 3.5 -40~125 • • 74AHC1G08-Q100 Single 2-input AND gate 2.0 - 5.5 ±8 3.2 -40~125 • • 74AHCT1G08-Q100 Single 2-input AND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • • 74AHC1G32-Q100 Single 2-input OR gate 2.0 - 5.5 ±8 3.2 -40~125 • • 74AHCT1G32-Q100 Single 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • • 74AHC1G86-Q100 2-input EXCLUSIVE-OR gate 2.0 - 5.5 ±8 3.4 -40~125 • • 74AHCT1G86-Q100 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ±8 3.5 -40~125 • • 74AHC2G00-Q100 Dual 2-input NAND gate 2.0 - 5.5 ±8 3.5 -40~125 • • 74AHCT2G00-Q100 Dual 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • • 74AHC2G08-Q100 Dual 2-input AND gate 2.0 - 5.5 ±8 3.2 -40~125 • • 74AHCT2G08-Q100 Dual 2-Input AND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • • 74AHC2G32-Q100 Dual 2-input OR gate 2.0 - 5.5 ±8 3.2 -40~125 • • 74AHCT2G32-Q100 Dual 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • • 74AUP1G02-Q100 Single 2-input NOR gate 1.1 - 3.6 ± 1.9 8.2 -40~125 • 74AUP1G08-Q100 Single 2-input AND gate 1.1 - 3.6 ± 1.9 8.2 -40~125 • 74AUP1G32-Q100 Single 2-input OR gate 1.1 - 3.6 ±1.9 7.9 -40~125 • 74AUP1G86-Q100 Single 2-input EXCLUSIVE-OR gate 1.1 - 3.6 ± 1.9 3.3 -40~125 • 74AUP1T98-Q100 Configurable gate with voltage level translation 2.3-3.6 V ±1.9 8.7 -40~125 74HC1G86-Q100 Single 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 2.6 9 -40~125 • 74HC1GU04-Q100 Single inverter; unbuffered 2.0 - 6.0 ± 2.6 5 -40~125 • 74HC1G00-Q100 Single 2-input NAND gate 2.0 - 6.0 ± 2.6 7 -40~125 • 74HCT1G00-Q100 Single 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±2 10 -40~125 • • 74HC1G02-Q100 Single 2-input NOR gate 2.0 - 6.0 ± 2.6 7 -40~125 • • 74HCT1G02-Q100 Single 2-input NOR gate; TTL-enabled 4.5 - 5.5 ± 2.0 9 -40~125 • • 74HC1G08-Q100 Single 2-input AND gate 2.0 - 6.0 ± 5.2 7 -40~125 • • 74HCT1G08-Q100 Single 2-input AND gate; TTL-enabled 4.5 - 5.5 ±2 11 -40~125 • • 74HC1G32-Q100 Single 2-input OR gate 2.0 - 6.0 ± 2.6 8 -40~125 • • 74HCT1G32-Q100 Single 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 2.0 10 -40~125 • • 74HC2G00-Q100 Dual 2-input NAND gate 2.0 - 6.0 ± 5.6 9 -40~125 • • 126 NXP Logic selection guide 2016 SOT457 (GV) Description SOT363 (GW) Type number IO (mA) Package (suffix) VCC (V) Features • • Gates (cont.) Package (suffix) tpd (ns) Tamb (°C) SOT505-2 (DP) SOT765-1 (DC) Dual 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 12 -40~125 • • 74HC2G02-Q100 Dual 2-input NOR gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G02-Q100 Dual 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±4 12 -40~125 • • 74HC2G08-Q100 Dual 2-input AND gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G08-Q100 Dual 2-Input AND gate; TTL-enabled 4.5 - 5.5 ±4 14 -40~125 • • 74HC2G32-Q100 Dual 2-input OR gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G32-Q100 Dual 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 4.0 13 -40~125 • • 74HC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G86-Q100 Dual 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ± 4.0 11 -40~125 • • 74HCT1G86-Q100 Single 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ± 2.0 10 -40~125 • • 74LVC1G00-Q100 Single 2-input NAND gate 1.65 - 5.5 ± 32 2.2 -40~125 • • 74LVC1G02-Q100 Single 2-input NOR gate 1.65 - 5.5 ± 32 2.1 -40~125 • • 74LVC1G08-Q100 Single 2-input AND gate 1.65 - 5.5 ± 32 2.1 -40~125 • • 74LVC1G11-Q100 Single 3-input AND gate 1.65 - 5.5 ± 32 2.6 -40~125 74LVC1G32-Q100 Single 2-input OR gate 1.65 - 5.5 ± 32 2.1 -40~125 • • 74LVC1G38-Q100 Single 2-input NAND gate; open-drain 1.65 - 5.5 32 2.3 -40~125 • • 74LVC1G57-Q100 Configurable gate; Schmitt trigger 1.65 - 5.5 ± 32 3.8 74LVC1G58-Q100 Configurable gate; Schmitt trigger 1.65 - 5.5 ± 32 74LVC1G86-Q100 Single 2-input EXCLUSIVE-OR gate 1.65 - 5.5 74LVC1G332-Q100 Single 3-input OR gate 74LVC1GX04-Q100 SOT457 (GV) IO (mA) 74HCT2G00-Q100 SOT363 (GW) Description SOT753 (GV) Type number VCC (V) SOT353-1 (GW) Features • • -40~125 • • 3.8 -40~125 • • ± 32 2.4 -40~125 1.65 - 5.5 ± 32 2.6 -40~125 • • Crystal driver 1.65 - 5.5 ± 24 2.8 -40~125 • • 74LVC2G02-Q100 Dual 2-input NOR gate 1.65 - 5.5 ± 32 2.4 -40~125 • • 74LVC2G08-Q100 Dual 2-input AND gate 1.65 - 5.5 ± 24 2.1 -40~125 • • 74LVC2G32-Q100 Dual 2-input OR gate 1.65 - 5.5 ± 32 2.2 -40~125 • • 74LVC2G34-Q100 Dual buffer 1.65 - 5.5 ± 32 2.2 -40~125 74LVC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate 1.65 - 5.5 ± 32 2.3 -40~125 • • • • • • NXP Logic selection guide 2016 127 Latches/registered drivers Package (suffix) Features Type number Description 74AUP1G373-Q100 single D-type transparent latch (3-state) VCC (V) IO (mA) tpd (ns) Tamb (°C) SOT363 (GW) 1.1 - 3.6 ±1.9 8.5 -40~125 • Multivibrators Features Type number Description 74LVC1G123-Q100 single retriggerable monostable multivibrator Package (suffix) VCC (V) IO (mA) tpd (ns) Tamb (°C) SOT505-2 (DP) SOT765-1 (DC) 1.65 - 5.5 ± 32 3.5 -40~125 • • Schmitt triggers tpd (ns) Tamb (°C) SOT353-1 (GW) SOT753 (GV) SOT505-2 (DP) SOT765-1 (DC) SOT996-2 (GD) 74AHC1G14-Q100 Single inverter Schmitt trigger 2.0 - 5.5 ±8 3.2 -40~125 • • 74AHCT1G14-Q100 Single inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 4.1 -40~125 • • 74AHC3G14-Q100 Triple inverter Schmitt trigger 2.0 - 5.5 ±8 3.2 -40~125 • • • 74AHCT3G14-Q100 Triple inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 4.1 -40~125 • • • 74HC1G14-Q100 Single inverter Schmitt trigger 2.0 - 6.0 ± 2.6 10 -40~125 • • 74HCT1G14-Q100 Single inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 2.0 15 -40~125 • • 74HC2G14-Q100 Dual inverter Schmitt trigger 2.0 - 6.0 ± 5.2 16 -40~125 • • 74HCT2G14-Q100 Dual inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 4.0 21 -40~125 • • 74HC2G17-Q100 Dual buffer Schmitt trigger 2.0 - 6.0 ± 5.2 12 -40~125 • • 74HCT2G17-Q100 Dual buffer Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 4.0 21 -40~125 • • 74HC3G14-Q100 Triple inverter Schmitt trigger 2.0 - 6.0 ± 5.2 16 -40~125 • • 74HCT3G14-Q100 Triple inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 4.0 21 -40~125 • • 74LVC1G14-Q100 Single inverter Schmitt trigger 1.65 - 5.5 ± 32 3 -40~125 • • 74LVC1G17-Q100 Single buffer Schmitt trigger 1.65 - 5.5 ± 32 3 -40~125 • • 74LVC2G14-Q100 Dual inverter Schmitt trigger 1.65 - 5.5 ± 32 3.9 -40~125 • • 74LVC2G17-Q100 Dual buffer Schmitt trigger 1.65 - 5.5 ± 32 3.6 -40~125 • • 74LVC3G17-Q100 Triple buffer Schmitt trigger 1.65 - 5.5 ± 32 3.6 -40~125 • • 128 NXP Logic selection guide 2016 SOT457 (GV) Description SOT363 (GW) Type number IO (mA) Package (suffix) VCC (V) Features Level shifters/translators SOT353-1 (GW) 1.1 - 3.6 1.1 - 3.6 ± 1.9 -40~125 • 74AVC1T45-Q100 Single dual-supply voltage level translating transceiver (3-state) 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 74AVC2T45-Q100 Dual-bit dual-supply voltage level translating transceiver (3-state) 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 74AVCH1T45-Q100 Single dual-supply voltage translating transceiver with bus hold (3-state) 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 • 74LVC1T45-Q100 Single dual-supply voltage level translating transceiver (3-state) 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 • 74LVCH1T45-Q100 Single dual-supply voltage translating transceiver with bus hold (3-state) 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 • 74LVC2T45-Q100 Dual-bit dual-supply voltage level translating transceiver (3-state) 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 • 74LVCH2T45-Q100 Dual-bit dual-supply voltage level translating transceiver with bus hold (3-state) 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 • SOT996-2 (GD) Tamb (°C) Single dual supply translating buffer SOT765-1 (DC) IO (mA) 74AUP1T34-Q100 SOT505-2 (DP) Description SOT363 (GW) Type number VCC(B) (V) Package (suffix) VCC(A) (V) Features • • • • Mini Logic packages Package suffix Package GW GV GW GV D DP PW DC GD 5-pin 5-pin 6-pin 6-pin 8-pin 8-pin 8-pin 8-pin 8-pin SOT353-1 SOT753 SOT363 SOT457 SOT96-1 SOT505-2 SOT530-1 SOT765-1 SOT996-2 Width (mm) 2.10 2.75 2.10 2.75 6.00 4.00 3.00 3.10 3.00 Length (mm) 2.00 2.90 2.00 2.90 4.90 3.00 6.40 2.00 2.00 Height (mm) 1.00 1.00 1.00 1.00 1.75 1.10 1.10 1.00 0.50 Pitch (mm) 0.65 0.95 0.65 0.95 1.27 0.65 0.65 0.50 0.50 NXP Logic selection guide 2016 129 Packages Industry-leading size, performance, and selection NXP is a recognized leader in packaging technology and has, over the years, driven the evolution to smaller, higherperformance formats. We were one of the first to offer leadless packages, and continue to break new ground with unique options like the Diamond package, the world’s smallest general-purpose logic package. Delivering industry firsts like the Diamond package underscores NXP’s commitment to leadership, innovation, and understanding of a market that is driven by the need for smaller, cheaper, more reliable solutions. Superior selection Support for legacy formats We deliver improved electrical and mechanical We may have our eye on the future of packaging, but performance, smaller size, higher board-level reliability, we also understand the importance of maintaining and lower cost. We support wider temperature ranges technologies for as long as they’re needed. We know (-40 to +125 °C), and offer packages that are automotive that larger packages, such as SO and TSSOP, still have qualified according to the AEC-Q100 standard. Our their place in some designs, and continue to support roadmap guides the way to the lowest profile and the these tried-and-true solutions. smallest pitch. The journey to smaller formats 130 NXP Logic selection guide 2016 The leadless advantage Our products comply with the following: Today’s ultra-compact designs can be a challenge when it 4 European Union Restriction on Hazardous Substances comes to squeezing more functionality into a smaller space. (RoHS) directive Tiny leadless packages can deliver a significant advantage 4 End of Life Vehicle (ELV) directive here – with options like DQFN, MicroPak, and Diamond 4 China RoHS packages offering a smaller footprint with improved mechanical performance. NXP was one of the earliest semiconductor companies to address environmental concerns over packaging, and we Leadless packages use pads instead of leads. The pads have worked quickly to reduce or eliminate the presence of present a bigger solderable area, so they create a stronger lead, mercury, chromium, and poly-brominated compounds. bond with the PCB. The result is a design that is more We follow the guidelines for compliance with environmental compact, and also more durable. NXP’s DQFN, MicroPak, and directives, such as RoHS, and go beyond the baseline Diamond packages perform better in mechanical tests like requirements by reducing the limits of antimony oxides pull, shear, drop, and bend. (Sb2O3, Sb2O5), as well as chlorinated and brominated flame retardants. Our “Dark Green” packages are RoHS compliant The NXP portfolio includes more than 50 leadless and also free of halogen and antimony. packages, and all are qualified for use in automotive-grade environments. Our LVC, AUP, and AXP logic functions are Our Dark Green products have less impact on the environment available in leadless DQFN, MicroPak, and Diamond packages, and, as an added bonus, are more resistant to moisture. Dark so it’s easy to find the right mix of features, footprint, and Green packages don’t require dry-pack processing, which cost. involves drying the package and sealing it in plastic, and this delivers an added saving on energy and resources. The latest When transitioning to leadless formats, consider the following Dark Green products also use smaller ICs, so they can be guidelines: housed in smaller packages. The result is lower cost, fewer 4 For gates, octals, and other logic functions with 10 or more materials, lower power consumption and, of course, a reduced pins, choose the DQFN package. It uses the same die as a environmental footprint. TSSOP, but the footprint is up to 76 percent smaller. 4 For single-, dual-, and triple-gate functions, which typically use fewer than 10 pins, choose the MicroPak package. It uses the same die as a PicoGate, but the footprint is up to 62 percent smaller. Recommended replacements for leaded packages Definitions of Green and Dark Green Green = RoHS compliant Substance(s) Limit Pb < 1000 ppm Hg, Cr6+, PBB, PBDE < 1000 ppm Cd < 100 ppm Leaded package Leadless equivalent Space savings Best for functions of TSSOP DQFN Up to 76% smaller 10+ pins Substances Limit MicroPak Up to 62% smaller 6 to 10 pins Antimony oxides (Sb2O3, Sb2O5) < 900 ppm Diamond 25% smaller than smallest MicroPak (XSON6) 5 pins Chlorinated and brominated flame retardants ∑ < 900 ppm PicoGate Environmental compliance Respect for the environment is one of the guiding principles of the NXP Sustainability Policy. Our ongoing commitment to excellence in this area means we continuously move toward best-in-class environmental standards, and supply products that use fewer hazardous or restricted substances and can be recycled or disposed of in an environmentally sound way. Dark Green = RoHS compliant and free of antimony and halogen Note: substances above are not intentionally added, but might be present as an impurity with an upper limit according to the listed values. The plastic materials are classified according to UL94V-0. Online access to all chemical contents We were the very first to list all the chemical contents in our products on an easy-to-access web page that also shows compliance with legislative requirements (www.nxp.com/ chemical-content/search/). Search results can be downloaded to an Excel or Zip file. NXP Logic selection guide 2016 131 Package selection matrix Width Pitch Suffix (mm) (mm) 1.27 6 8 10 12 7.5 SSOP 3.9 5.3 TSOP 0.635 0.65 16 SOT108-1 SOT109-1 2.8 2.1 4.4 6.1 0.635 0.95 20 24 28 SOT163 SOT137-1 SOT136-1 SOT724-1 SOT556-1 48 56 SOT370-1 SOT371-1 60 96/144 D/T DS / DK SOT519-1 DB SOT337-1 7.5 TSSOP 1.27 14 D/T SOIC 3.9 5 SOT338-1 SOT339-1 SOT340-1 SOT341-1 DL GV 0.65 GW 0.65 PW / TT 0.5 DGG 0.5 BQ/ BX SOT753 SOT457 SOT353 SOT363 SOT402-1 SOT403-1 SOT360-1 SOT355-1 SOT361-1 SOT362-1 SOT364-1 DQFN 2.5 3.5 0.5 SOT762-1 SOT763-1 SOT764-1 BQ HUQFN 4 TVSOP 4.4 LFBGA 5.5 VFBGA SOT815-1 4.5 0.5 BX SOT1025-1 0.4 DGV SOT480-1 0.8 BC SOT536-1 0.65 EV SOT702-1 0.8 0.5 GX SOT1226 1.0 XSON 1.0 1.0 2 0.5 0.35 0.3 0.5 GM/ GT SOT886 SOT833 SOT1202 SOT1203 SOT1115 SOT1116 GS GN GD SOT996 1 0.35 GF SOT891 1 0.35 SOT1081 DP SOT1089 0.5 GM XQFN 1.6 SOT902 1.7 0.5 SOT1049 SOT1174 GU SOT1161 132 SOT481-2 NXP Logic selection guide 2016 Nomenclature NXP's naming convention embeds the package type in the product number. Our nomenclature diagrams list all items alphabetically. Nomenclature for standard logic functions 74 XXX Logic family AHC(T) ALVC ALVT AUP AVC(M) CBT(D) CBTLV(D) HC(T) HEF4000B LV LVC LVT NPIC VHC(T) XC7 XXX Function number Nomenclature for mini logic functions XXX 74 XXX Package type BQ BX D DB DC DG DGG DL DP FC EV GU P T TS TT DQFN DQFN SO SSOP VSSOP TSSOP TSSOP SSOP TSSOP BGA BGA DQFN TSSOP SO SSOP TSSOP Logic family AHC(T) AUP AVC(M) AXP CBT(D) CBTLV(D) HC(T) LVC XC7 XG XT XXX XXX Gate format Function number Package type 1G Single-gate 2G Dual-gate 3G Triple-gate Translator format 1T 2T 3T 4T Single-translator Dual-translator Triple-translator Quad-translator DC DP GD GF GM GN GS GT GV GW GX PicoGate PicoGate MicroPak MicroPak MicroPak MicroPak MicroPak MicroPak PicoGate PicoGate MicroPak NXP Logic selection guide 2016 133 Package diagrams SOT353 GW Pinout GW Pinout 5 4 1 2 3 Package dimensions 6 5 4 1 2 3 Package dimensions 2.25 1.85 0.60 0.15 0.46 0.21 4 5 2.2 1.8 1.1 0.1 0.0 6 2.2 1.35 2.0 1.15 2.25 1.35 2.00 1.15 1 2 0.65 1.3 Dimensions in mm Solder footprint 134 SOT363 NXP Logic selection guide 2016 0.30 0.15 0.65 0.25 0.08 14-10-01 1.3 Dimensions in mm Solder footprint 5 4 2 3 0.45 0.15 pin 1 index 1 3 1.1 0.8 0.3 0.2 0.25 0.10 14-10-03 SOT457 GV SOT505-2 Pinout Pinout 6 5 4 1 2 3 Package dimensions 6 1.7 1.3 8 5 1 4 Package dimensions 3.1 2.7 3.0 2.5 DP 3.1 2.9 1.1 0.9 5 4 1.1 max 5 8 0.6 0.2 0.15 0.00 0.47 0.33 4.1 3.1 3.9 2.9 pin 1 index 1 2 0.95 1.9 Dimensions in mm 3 0.40 0.25 1 0.26 0.10 4 14-10-03 0.18 0.08 0.38 0.22 0.65 Dimensions in mm 14-10-01 Footprint information for reflow soldering of TSSOP8 package Solder footprint SOT505-2 Solder footprint Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area NXP Logic selection guide 2016 DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 135 SOT650-1 TK Pinout SOT753-1 GV Pinout 10 6 5 1 1 4 2 3 5 Transparent top view Package dimensions Package dimensions 3.1 2.7 3.1 2.9 1.0 2.0 1 5 0.30 0.18 0.5 5 1.7 1.3 1.75 1.45 1 2 0.95 6 10 2.55 2.15 Dimensions in mm 1.9 14-10-01 Footprint information for reflow soldering of HVSON10 package SOT650-1 Solder footprint Gx D (0.105) P C SPx nSPx SPy tot SPy Hy Gy SLy nSPy By Ay SPx tot SLx Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area DIMENSIONS in mm P Ay By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hy nSPx 0.500 4.000 2.200 0.900 0.240 2.400 1.500 1.400 0.650 0.550 0.650 3.300 3.300 4.250 2 Issue date 136 0.6 0.2 4 0.05 0.00 3.0 2.5 0.55 3.1 0.30 2.9 1.1 0.9 09-12-29 09-12-29 NXP Logic selection guide 2016 nSPy 1 sot650-1_fr Dimensions in mm Solder footprint 3 0.40 0.25 0.26 0.10 14-10-03 SOT765-1 DC Pinout SOT833-1 GT Pinout 5 8 8 7 6 5 1 2 3 4 Transparent top view 1 4 Package dimensions Package dimensions 2.1 1.9 1.0 max 2.0 1.9 0.15 0.00 5 8 1 0.40 0.15 1.05 0.6 0.95 3.2 2.4 3.0 2.2 4 0.23 0.08 0.27 0.17 0.5 of VSSOP8 package Footprint information for reflow soldering Dimensions in mm SOT765-1 14-10-01 Solder footprint 3 4 0.5 0.04 0.40 0.32 0.35 0.27 8 1 2 0.25 0.17 Dimensions in mm 0.5 7 0.5 6 0.5 5 14-09-30 Solder footprint Hx Gx P2 Hy D1 (0.125) Gy By Ay C (0.125) (0.175) D2 (4x) P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.500 0.550 3.500 2.000 0.750 0.300 0.400 2.250 1.750 3.075 3.750 sot765-1_fr NXP Logic selection guide 2016 137 SOT886 GM Pinout GF Pinout 6 1 5 4 1 2 3 Transparent top view 3 Package dimensions 0.50 max 1.05 0.95 0.6 3 4 1.05 0.95 2 0.5 max 0.55 0.04 max 0.25 0.17 3 4 2 5 1 6 0.35 0.5 1.5 1.4 2 6 5 4 bottom view Package dimensions 1.05 0.95 5 0.04 max 0.20 0.12 0.35 0.5 1 6 0.40 0.32 0.35 0.27 Dimensions in mm Solder footprint 138 SOT891 NXP Logic selection guide 2016 0.40 0.32 14-10-03 Dimensions in mm Solder footprint 0.35 0.27 14-10-03 SOT902-2 GM Pinout SOT996 GD Pinout 4 3 5 2 6 1 7 4 5 1 8 8 Package dimensions Package dimensions 1.65 1.55 4 2.1 1.9 0.5 1.5 0.05 0.00 0.25 0.15 1 3 0.5 0.5 4 0.35 0.15 0.05 0.00 5 0.5 1.65 1.55 2 6 1 7 0.6 3.1 0.4 2.9 8 0.35 0.25of XQFN8 package 0.55 Footprint information for reflow soldering Dimensions in mm 14-09-30 Solder footprint 8 Dimensions in mm SOT902-2 0.5 0.3 5 14-09-30 Solder footprint Hx D (8×) 0.025 0.025 C (7×) Hy Ay 1.000 SLy 0.110 0.320 SLx 1.200 solder land solder paste deposit solder land plus solder paste occupied area DIMENSIONS in mm Ay C D SLx SLy Hx Hy 1.2 0.22 0.4 0.5 0.5 1.9 1.9 Issue date 12-02-23 12-12-18 sot902-2_fr NXP Logic selection guide 2016 139 SOT1049-3 GM Pinout SOT1081-1/2 GF Pinout 5 4 6 1 9 Package dimensions 5 1 5 Package dimensions 1.8 1.6 0.5 0.05 0.00 0.25 0.15 1.4 0.35 1 6 4 0.5 0.20 0.10 0.05 0.00 5 0.45 0.35 2.1 1.9 0.33 0.23 1.5 1.1 0.9 0.2 0.5 0.4 0.3 Dimensions in mm 0.4 0.3 9 1 10 Solder footprint 140 6 Transparent top view 10 1.65 1.45 10 NXP Logic selection guide 2016 10 0.48 0.38 14-10-01 Dimensions in mm Solder footprint 6 14-09-30 SOT1089 GF Pinout SOT1202 GS Pinout 8 7 6 5 1 2 3 4 Transparent top view 6 5 4 1 2 3 Transparent top view Package dimensions Package dimensions 1.05 0.95 0.20 0.12 1.05 0.95 0.5 0.04 0.55 4 1 5 0.35 2 0.20 0.12 3 0.35 0.27 0.40 0.32 0.35 0.04 1.05 0.55 0.95 1.40 1.30 1 0.40 0.32 Dimensions in mm Solder footprint 8 0.35 0.27 6 5 0.35 14-10-01 4 0.35 Dimensions in mm 14-09-29 SOT1202 Footprint information for reflow soldering of SOT1202 package Solder footprint 0.25 (6x) 0.15 (6x) 0.6 (6x) 0.5 (6x) 0.7 0.35 1.4 0.35 1.05 occupied area solder resist solder paste = solder lands Issue date 10-09-10 14-01-06 Dimensions in mm sot1202_fr NXP Logic selection guide 2016 141 SOT1203 GS Pinout SOT1226 GX Pinout 8 7 6 5 1 5 3 GND 2 1 2 3 4 aaa-018998 Transparent top view Package dimensions Package dimensions 1.40 1.30 1 2 0.35 3 4 0.20 0.12 0.04 0.35 0.27 0.40 0.32 1.05 0.55 0.95 8 7 0.35 Dimensions in mm Solder footprint 142 NXP Logic selection guide 2016 6 0.35 4 5 0.35 14-09-30 Solder footprint SOT815-1 BQ PW Pinout 1 24 Pinout SOT402-1 2 23 3 22 4 21 5 20 6 19 7 18 8 9 10 1 14 2 13 3 12 4 11 5 10 17 6 9 16 7 15 GND(1) 13 14 12 11 8 aaa-019003 aaa-019005 Package dimensions Package dimensions Solder footprint Solder footprint NXP Logic selection guide 2016 143 SOT403-1 PW Pinout SOT360-1 PW Pinout 1 20 1 16 2 19 2 15 3 18 3 14 4 17 4 13 5 16 5 12 6 15 6 11 7 14 7 10 8 13 8 9 9 12 10 aaa-019012 11 aaa-019015 144 Package dimensions Package dimensions Solder footprint Solder footprint NXP Logic selection guide 2016 SOT337-1 DB Pinout SOT338-1 DB Pinout 1 16 1 14 2 15 2 13 3 14 3 12 4 11 4 13 5 10 5 12 6 9 6 11 7 8 7 10 aaa-018999 aaa-019007 Package dimensions Package dimensions 1 14 7 8 Dimensions in mm Solder footprint 9 8 15-05-26 Solder footprint NXP Logic selection guide 2016 145 SOT339-1 DB Pinout SOT519-1 DS Pinout 1 20 2 19 1 16 3 18 2 15 4 17 3 14 5 16 4 13 6 15 5 12 7 14 6 11 8 13 9 12 7 10 10 11 aaa-019013 aaa-009314 146 Package dimensions Package dimensions Solder footprint Solder footprint NXP Logic selection guide 2016 9 8 SOT724-1 DS GM 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1 12 Pinout 11 2 10 3 9 4 8 5 6 Pinout SOT1174 7 aaa-019000 aaa-019016 Package dimensions Package dimensions Solder footprint Solder footprint NXP Logic selection guide 2016 147 SOT1161 GU D 1 13 14 15 Pinout 16 Pinout SOT137-1 VCC(A) 1 24 VCC(B) DIR 2 23 VCC(B) A0 3 22 OE A1 4 21 B0 A2 5 20 B1 A3 6 19 B2 A4 7 18 B3 A5 8 17 B4 A6 9 16 B5 A7 10 15 B6 GND 11 14 B7 12 4 9 aaa-019008 Package dimensions aaa-019011 Package dimensions Dimensions in mm Solder footprint 148 NXP Logic selection guide 2016 13 GND GND 12 8 10 7 3 6 11 5 2 Solder footprint 15-05-26 SOT556-1 DK Pinout SOT340-1 DB Pinout 1 24 1 24 2 23 2 23 3 22 3 22 4 21 4 21 5 20 5 20 6 19 6 19 7 18 7 18 8 17 8 17 9 16 9 16 10 15 10 15 11 14 11 14 12 13 12 aaa-019014 13 aaa-019017 Package dimensions Package dimensions Solder footprint Solder footprint NXP Logic selection guide 2016 149 SOT355-1 PW BQ 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 2 23 3 22 4 21 5 20 6 19 7 18 8 15 14 aaa-019005 Package dimensions Package dimensions Solder footprint Solder footprint NXP Logic selection guide 2016 16 GND(1) 11 aaa-019001 150 17 9 10 13 24 2 1 1 24 Pinout 12 Pinout SOT815-1 Design tools NXP is committed to making the design process as easy as possible. We offer a range of design tools that make it easier to select the right product for a design, verify performance, explore functionality, and begin prototyping. The result is a smoother development process, and faster time-to-market. This section includes the following: 4 Breakout boards for use with breadboard sockets 4 Evaluation boards for standard and configurable logic 4 Demo board for AXP configurable logic 4 Packaging linecard How to order To order a breakout board, an evaluation board, or a package linecard, contact your local NXP sales office or distributor (www.nxp.com/about/sales-offices-distributors), or NXP technical support (www.nxp.com/technicalsupport). The 74AXP1G57 demo board can be ordered online, at www.nxp.com/logic. Breakout boards for use with breadboard sockets Using breadboards is a quick way to create prototypes or experiment with a device, but today’s smallscale packages don’t always fit in breadboard sockets. NXP’s breakout boards are compact PCBs that convert the latest, smallest leadless packages into bigger DIP sockets, providing easy access to all the device I/O. 4 TSSOP, PicoGate, MicroPak, DQFN 4 Accommodate packages with 5, 6, 8, 10, 12, 14, or 16 pins/pads 4 Test pins available for supply pins, I/O access, and measurement 4 Coated with solder paste, for easy mounting 4 Pre-assembled versions available with specific functions NXP Logic selection guide 2016 151 Breakout boards Evaluation boards for standard and configurable logic Our evaluation boards enable quick prototyping by providing GEN1 (1.15 x 0.60 inches) Package type No. of pins Pitch (mm) 353 TSSOP 5 0.65 753 SO5 5 0.95 363 TSSOP 6 0.65 for easy test and verification of the device’s most important 457 TSOP6 6 0.95 features. 886 XSON6 6 0.50 891 XSON6 6 0.35 505 TSSOP8 8 0.65 530 TSSOP8 8 0.65 765 VSSOP8 8 0.50 833 XSON8 8 0.50 902 XQFN8U 8 0.50 GEN2 (1.10 x 0.60 inches) convenient way to verify behavior, confirm static and dynamic characteristics under different loads, compare features, and benchmark against the competition. Each board is equipped Evaluation boards for standard logic Product number Description Board features 74LVC169 Binary counter/ timer 2/4/8/16 clock division, up/down counting 74LVC2G66 Dual SPST switch Switch high-frequency signals with overvoltage-tolerant control inputs up to 5 V 74LVCV2G66 Dual SPST OVT switch Switch high-frequency signals with overvoltage-tolerant control and data inputs up to 5 V 74AUP1Z04 Low-power crystal driver Combines buffered and unbuffered inverters and demonstrates standby mode SOT number Package type No. of pins Pitch (mm) 363 TSSOP 6 0.65 457 TSOP6 6 0.95 1202 XSON6 6 0.35 1115 XSON6 6 0.30 96 SO8 8 1.27 996 XSON8U 8 0.50 determines which logic function the device performs, so you 1089 XSON8 8 0.35 can use just one device type to perform multiple functions 1116 XSON8 8 0.30 in your system. Each evaluation board for configurable logic 1203 XSON8 8 0.35 measures just 2.5 x 3 inches, and includes four sections with Evaluation boards for configurable logic Configurable logic offers nine or more functions in a single PicoGate or MicroPak package. The pin configuration the same configurable logic device mounted on each section. GEN3 (1.60 x 0.60 inches) The user can configure each device to perform one of seven SOT number Package type No. of pins Pitch (mm) 650 HVSON10 10 0.50 1049 XQFN10U 10 0.50 Available for AXP, AUP, and LVC configurable-logic devices 1160 XQFN10 10 0.40 4 Power-supply decoupling provided on-board 1174 XQFN12 12 0.40 4 Supports external supply voltage of 0.7 to 2.75 V (AXP), 0.8 762 DHVQFN14 14 0.50 402 TSSOP14 14 0.65 763 DHVQFN16 16 0.50 1039 HXQFN16U 16 0.50 1161 XQFN16 16 0.40 GEN4 (1.12 x 0.62 inches) 152 access to the I/O and supply-voltage pins. They are a SOT number SOT number Package type No. of pins Pitch (mm) 1226 XSON5 5 0.48 1340-1 HXSON4 4 0.50 1255 XSON6 6 0.50 1348-1 TDQFN6 6 0.65 NXP Logic selection guide 2016 unique functions. to 3.6 V (AUP), or 1.65 to 5.5 V (LVC) 4 Test points at all I/O pins 4 Each board section can be connected or detached via jumpers 4 Supports cascading of multiple devices Evaluation board for configurable logic Demo board for AXP configurable logic The AXP1G57GM demo board is also available as The AXP1G57GM demo board gives designers a a sample kit, which includes sample devices, a USB quick, easy way to demonstrate the configurable drive with data sheets and other literature, and an logic functions. optional A-to-B USB cable. The sample kit can be 4 Seven 74AXP1G57 devices, each configured as a ordered through the e-sample center, located at unique function https://extranet.nxp.com. 4 One 74AVC8T245 device, for translation from 1.2 to 3.3 V 4 Three push-button switches to toggle the A, B, and C input pins of the 74AXP1G57 device 4 NPN transistor PMBT3904 to drive a green/red 2.2 V, 20 mA LED, and a current-limiting resistor 4 Rotary switch for selecting one of seven functions with output connected to status LED 4 Mini-USB socket or battery holder to supply 4.5 or 5 V DC power to the board Packaging linecard NXP offers one of the broadest selections of small-scale, automotive-grade, RoHS-compliant and Halogen-free logic packages. Our packaging linecard, which is populated with actual packages, is a quick reference to compare all our TSSOP, PicoGate, QFN, MicroPak, Diamond, and CSP options. It provides an at-a-glance comparison of size, and lists order number, SOT number, and footprint for each package type. NXP Logic selection guide 2016 153 Competitive cross reference This cross reference allows you to match a competitor’s part number to an NXP part number. Once you have the equivalent part number, check the NXP website www.nxp.com/logic to confirm that the particular configuration is released. Texas instruments logic SN74 TI Prefix NXP SN74 SN54 74 74 Fairchild semiconductor tiny logic LVC Logic Family TI NXP ABT AHC(T) ALVC ALVT AUP AVC CBT CBTLV CD F HC(T) LV LVC LVT TPIC6C 74 ABT AHC(T) ALVC ALVT AUP AVC CBT CBTLV HEF F HC(T) LV LVC LVT NPIC6C LVC 1G 08 Gate count TI NXP nG nT 1G DCK Package TI NXP Function nG nT E M D PW DB DL DGG DGV GKE ZKE DCK DBV DCU DCT DRY YZP 08 NC7 P T D PW, TT DB DL DGG DGV EV EC GW GV DC DP GM GM Prefix FSC NXP NC7 S Gate count FSC NXP 74 S W N 74 1G 2G 3G Z 157 Logic Family FSC NXP B P T V Z P6 Function HC LVC AUP HCT AUP LVC 1G LVC Package FSC NXP P5 M5 P6 K8 L6 L8 157 GW GV GW DC GM GM GW GW On semiconductors logic MC74 VHC 1GT 08 DTT Fairchild semiconductor standard logic Prefix ON NXP MC74 74 Logic Family ON NXP HC LCX LVX MC1 VCX VHC 74 — — TC74 74 HC(T) LCX LVX TC VCX VHC(T) 74 154 LCX Logic Family Tosh NXP Prefix Tosh NXP NXP Logic selection guide 2016 Gate count ON NXP Function nG nG nGT* nG * Indicates TTL variant of the family AHCT Package ON NXP N, C D DT DFT DTT US QZ MN AMX CMX 1G 08 N, P D PW GW GV DC DS BQ GM GS GW On semiconductor low pin count logic Toshiba standard logic TC74 HC(T) LVC LV HEF ALVC AHC(T) 125 Function HC(T) LVC LV HEF ALVC VHC(T) LVC Package Tosh NXP P FW FN FT FS 125 NL FT PW N D D PW DB Prefix ON NXP NLn7 74 74 1 7 Gate count ON NXP n nG LVC SZ 08 Logic Family ON NXP SV SZ WZ WB Function AUP LVC LVC LVC 1G DFT Package ON NXP DFT DTT US AMX CMX 08 GW GW GV DC GM GS Toshiba one gate IDT logic TC7 Prefix Tosh NXP TC7 S Gate count Tosh NXP 74 S W P 1G 1,2 or 3G 1 or 2G Z 157 Logic Family Tosh NXP A G T H ET Z 74 FU HC LVC AUP HCT AHC AHCT LVC FK FU Logic Family IDT NXP Prefix IDT NXP Package Tosh NXP Function 74 54 GV GW, DP FCT ALVC CBTLV FCT LVC QS 74 74 74 74 LVC 1G 157 244 PY Package IDT NXP Function ALVC CBTLV ABT LVC CBT BF CD DC, PS DJ, PF PA PC PG PV PY ABT 244 EC N D DGV DGG DS, DK PW DL DB DB GW Renesas logic Diodes Inc. logic 74 Prefix Diodes NXP 74 74 74 HD74 LVC Logic Family Diodes NXP AHC(T) LVC AHC(T) LVC LVC 1G 08 Gate count Diodes NXP nG 1G FW4 Function nG Package Diodes NXP T14 S14 SE DW W5 FZ4 FW4 08 PW D GW GW GV GM GF HC Prefix Ren . NXP Logic Family Ren . NXP HD74 ALVC BC, LS CBT HC(T) LV LVC LVT 74 74 ALVC ABT CBT HC(T) LV LVC LVT HC 1G 08 Gate count Ren . NXP nG 1G Function nG CM Package Ren . NXP CM FP P T US 08 GW DC N PW DC GW GW NXP Logic selection guide 2016 155 www.nxp.com © 2016 NXP Semiconductors N.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Date of release: March 2016 Published in the USA