TLF4949 5V Low Drop Out Linear Voltage Regulator TLF4949SJ TLF4949EJ Data Sheet Rev. 1.0, 2012-05-07 Automotive Power TLF4949 Table of Contents Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment PG-DSO-8 EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions PG-DSO-8 EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.5 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Preregulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Performance Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 5.1 5.2 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Supply Voltage Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Sheet 2 5 5 5 6 6 Rev. 1.0, 2012-05-07 5V Low Drop Out Linear Voltage Regulator 1 TLF4949 Overview Features • • • • • • • • • • • • • Operating DC Supply Voltage Range 5 V to 28 V Transient Supply Voltage up to 40 V Extremely low Quiescent Current in Standby Mode High Precision Standby Output Voltage 5 V ±1% Output Current Capability up to 100 mA Very low Dropout Voltage less than 0.5 V Reset Circuit sensing the Output Voltage Programmable Reset Pulse Delay with External Capacitor Voltage Sense Comparator Thermal Shutdown and Short Circuit Protections Suitable for Use in Automotive Electronics Green Product (RoHS) AEC Qualified PG-DSO-8 Description The TLF4949 is a monolithic integrated 5V voltage regulator with a very low dropout output and additional functions as undervoltage reset with power-on reset delay and input voltage sense. It is designed to supply microcontroller controlled systems especially in automotive applications. PG-DSO-8 Exposed Pad Type Package Marking TLF4949SJ PG-DSO-8 TLF4949S TLF4949EJ PG-DSO-8 Exposed Pad TLF4949E Data Sheet 3 Rev. 1.0, 2012-05-07 TLF4949 Block Diagram 2 Block Diagram Block_Diagram.vsd Preregulator 5V PRE IN OUT RO Reset Bandgap Reference SO SI GND Figure 1 Data Sheet D Block Diagram 4 Rev. 1.0, 2012-05-07 TLF4949 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-DSO-8 IN 1 8 OUT SI 2 7 SO PRE 3 6 RO D 4 5 GND PG-DSO-8.vsd Figure 2 Pin Configuration PG-DSO-8 3.2 Pin Definitions and Functions PG-DSO-8 Pin Symbol Function 1 IN Input; block to GND directly at the IC with a ceramic capacitor. 2 SI Sense Input; if not needed connect to OUT 3 PRE Preregulator Output; 4 D Reset Delay; to select delay time, connect to GND via capacitor. 5 GND Ground 6 RO Reset Output; open-collector output. Keep open, if not needed. 7 SO Sense Output; open-collector output. Keep open, if not needed. 8 OUT 5-V Output; connect to GND with a capacitor ≥ 4.7μF, ESR < 10 Ω.1) 2) 1) For the usage of capacitors with very low ESR-values it is recommended to use a small 1Ω resistor in series. 2) Measured at f = 10kHz. Data Sheet 5 Rev. 1.0, 2012-05-07 TLF4949 Pin Configuration 3.3 Pin Assignment PG-DSO-8 Exposed Pad IN 1 8 OUT SI 2 7 SO PRE 3 6 RO D 4 5 GND PG-DSO-8-EP.vsd Figure 3 Pin Configuration PG DSO-8 Exposed Pad 3.4 Pin Definitions and Functions PG-DSO-8 Exposed Pad Pin Symbol Function 1 IN Input; block to GND directly at the IC with a ceramic capacitor. 2 SI Sense Input; if not needed connect to OUT. 3 PRE Preregulator Output; 4 D Reset Delay; to select delay time, connect to GND via capacitor. 5 GND Ground 6 RO Reset Output; open-collector output. Keep open, if not needed. 7 SO Sense Output; open-collector output. Keep open, if not needed. 8 OUT 5-V Output; connect to GND with a capacitor ≥ 4.7μF, ESR < 10 Ω1) 2). Exposed Pad PAD Heat sink connect to PCB heat sink area and GND 1) For the usage of capacitors with very low ESR-values it is recommended to use a small 1Ω resistor in series. 2) Measured at f = 10kHz. Data Sheet 6 Rev. 1.0, 2012-05-07 TLF4949 General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40°C to +125°C; all voltages with respect to ground, direction of current as shown in Figure 4 “Application Diagram” on Page 15 (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. VIN VIN_TR VPRE VOUT VRO VSI VSO VD -0.3 28 V – – 45 V 2) – 7 V – -0.3 20 V – -0.3 20 V – -30 40 V – -0.3 20 V – -0.3 7 V – IPRE IRO ISO – 5 mA – – 5 mA – – 5 mA – Tj Tstg -40 150 °C – -50 150 °C – VESD VESD -4 4 kV HBM3) -1 1 kV CDM4) Voltage Rating 4.1.1 DC Operating Supply 4.1.2 Transient Supply Voltage 4.1.3 Preregulator Output 4.1.4 Voltage Regulator Output 4.1.5 Reset Output 4.1.6 Sense Input 4.1.7 Sense Output Voltage 4.1.8 Reset Delay Current Rating 4.1.9 Preregulator Output 4.1.10 Reset Out 4.1.11 Sense Out Temperatures 4.1.12 Junction Temperature 4.1.13 Storage Temperature ESD Susceptibility 4.1.14 ESD Resistivity to GND 4.1.15 ESD Resistivity to GND 1) 2) 3) 4) Not subject to production test, specified by design. For transient durations of tTR < 1s. ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF). ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1. Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 7 Rev. 1.0, 2012-05-07 TLF4949 General Product Characteristics 4.2 Functional Range Table 1 Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. 4.2.1 Input Voltage Range for Normal Operation VIN 5.5 28 V – 4.2.2 Extended Input Voltage Range VIN 3.5 40 V –1) 2) 1) The output voltage will follow the input voltage for input voltages below VOUT + VDR, i.e device is in tracking mode until VOUT + VDR is reached. 2) Input voltages ranging from > 28 V up to 40 V may only be applied for transient periods tTR < 1s. Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. – 71 – K/W – – 116 – K/W –2) 4.3.5 – 172 – K/W Footprint only3) 4.3.6 – 145 – K/W 300 mm2 heatsink area on PCB3) 4.3.7 – 139 – K/W 600 mm2 heatsink area on PCB3) – 19 – K/W – – 52 – K/W –4) 4.3.3 – 167 – K/W Footprint only3) 4.3.4 – 78 – K/W 300 mm2 heatsink area on PCB3) 4.3.5 – 66 – K/W 600 mm2 heatsink area on PCB3) – 165 – °C 1) TLF4949SJ (PG-DSO-8) 4.3.3 4.3.4 Junction to Soldering Point1) Junction to Ambient 1) RthJSP RthJA TLF4949EJ (PG-DSO-8 Exposed Pad) 4.3.1 4.3.2 Junction to Case1) Junction to Ambient 1) RthJC RthJA Thermal Shutdown 4.3.6 Junction Temperature TJSD 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). 4) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Data Sheet 8 Rev. 1.0, 2012-05-07 TLF4949 4.4 Electrical Characteristics 4.4.1 Voltage Regulator Electrical Characteristics: Regulator VIN = 14 V, Tj = -40°C to +125°C, all voltages with respect to ground, direction of current as shown in Figure 4 “Application Diagram” on Page 15 (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions TJ = 25°C; IOUT = 1mA 6V ≤ VIN ≤ 28V; 1mA ≤ IOUT ≤ 50mA VIN = 40V1); 5mA ≤ IOUT ≤ 100mA 6V ≤ VIN ≤ 28V; 0mA ≤ IOUT ≤ 100mA IOUT = 10mA IOUT = 50mA IOUT = 100mA VIN = 3.5V; IOUT = 35mA Min. Typ. Max. 4.95 5 5.05 V 4.4.2 4.90 5 5.10 V 4.4.3 4.85 – 5.15 V 4.4.4 4.85 5 5.15 0.1 0.2 0.3 0.25 0.4 0.5 V V V 4.4.1 4.4.5 Output Voltage Dropout Voltage VDR = VIN - VOUT VOUT VDR 4.4.6 Input to Output Voltage Difference in Undervoltage Condition VIO – 0.17 0.4 V 4.4.7 Current Sink Capability from Output to GND Iouth2) -30 -55 – µA VIN = 25V; VOUT = 5.5V 4.4.8 Line Regulation ΔVOUT,line – 1 15 mV 6V < VIN < 28V; IOUT = 1mA 4.4.9 Load Regulation ΔVOUT,load IOUT,lim – 4 20 mV 1mA ≤ IOUT ≤ 100mA VOUT = 4.5V VOUT = 0V 3) 4.4.11 Quiescent Current IQSE – 180 300 µA IOUT = 0.3mA 4.4.12 Quiescent Current IQ – – 3.6 mA IOUT = 100mA 1) VIN = 40V may be only applied as transient supply voltage to the device for maximum period of tTR < 1s. Please note that also for such transient conditions, especially under higher load conditions, the absolute maximum rating of TJ must be respected at any time. If transient conditions up to VIN = 40V and elevated load currents are expected in the application a 4.4.10 Current Limit 120 240 180 400 mA mA sufficient cooling must be provided to meet the power dissipation. Testing this parameter for the maximum allowed period of T = 1s is for thermal reasons not subject to production test but guaranteed by design. 2) The test of this parameter ensures that the output voltage will not exceed 5.5V in a corresponding “no load current”condition. A sufficiently high value for Iouth will allow the output to react in a fast manner in case of a sudden decrease of load current (e.g. if load is switching to standby or powerdown mode) . 3) Foldback characteristic. Data Sheet 9 Rev. 1.0, 2012-05-07 TLF4949 4.4.2 RESET Electrical Characteristics: Reset VIN = 14 V, Tj = -40°C to +125°C, all voltages with respect to ground, direction of current as shown in Figure 4 “Application Diagram” on Page 15 (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 4.4.13 Reset Threshold Voltage 4.25 4.5 4.4.14 Reset Threshold Hysteresis 50 4.4.15 Reset Pulse Delay VRT VRTH tRD 4.75 V – 100 200 mV – 55 100 180 ms Calculated Value: CD = 100nF; tR ≥ 100µs 4.4.16 Reset Output Low Voltage VRL – – 0.4 V Reset Output High Leakage Current IRH – – 1 µA RRES ≥ 10kΩ to VOUT; VIN ≥ 0V and VOUT ≥ 1V1) VRES = 5V 4.4.17 4.4.18 Delay Comparator Threshold – 2 – V – 4.4.19 Delay Comparator Threshold Hysteresis VD,th VD,th, hy – 100 – mV – 4.4.20 Delay Capacitor charge current ID,chg – 2 – µA VD = 1V; current flowing out of D pin 4.4.21 Delay Capacitor discharge current ID,dchg – 9 – mA VD = 1V; current flowing into D pin 1) Device entering this condition by decreasing VIN from powered up and fully initialized operation state. 4.4.3 Sense Electrical Characteristics: Sense VIN = 14 V, Tj = -40°C to +125°C, all voltages with respect to ground, direction of current as shown in Figure 4 “Application Diagram” on Page 15 (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. VST VSTH VSL 1.16 1.23 1.35 V – 20 100 200 mV – – – 0.4 V ISH ISI – – 1 µA -5 -1.5 0 µA VSI ≤ 1.16V; VIN ≥ 3.5V; RSO ≥ 10KΩ to VOUT VSO= 5V; VSI ≥ 1.5V VSI = 0 Sense 4.4.22 Sense Low Threshold 4.4.23 Sense Threshold Hysteresis 4.4.24 Sense Output Low Voltage 4.4.25 Sense Output Leakage 4.4.26 Sense Input Current Data Sheet 10 Rev. 1.0, 2012-05-07 TLF4949 4.4.4 Preregulator Electrical Characteristics: Preregulator VIN = 14 V, Tj = -40°C to +125°C, all voltages with respect to ground, direction of current as shown in Figure 4 “Application Diagram” on Page 15 (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 4.5 5 6 V IPRE = 10 µA – – 10 µA – Preregulator 4.4.27 Preregulator Output Voltage 4.4.28 Preregulator Output Current Data Sheet VPRE IPRE 11 Rev. 1.0, 2012-05-07 TLF4949 4.5 Typical Performance Graphs Typical Performance Characteristics Equivalent Series Resistance ESR(COUT) versus Output Current IOUT Output Voltage VOUT versus Junction Temperature TJ 100 5,20 COUT = 4.7µF TJ = 25°C VIN = 6..28V VIN = 14V IOUT = 1mA 5,15 5,05 VOUT [V] ESR(COUT) [Ω] 5,10 10 Stable Region 1 5,00 4,95 4,90 4,85 0,1 0 4,80 10 20 30 40 50 60 70 80 90 100 -40 0 IOUT [mA] 40 80 120 TJ [°C] Output Voltage VOUT versus Input Voltage VIN Dropout Voltage VDR versus Output Current IOUT 6,00 0,4 TJ = 25°C TJ = 25°C 0,35 5,00 0,3 VDR [V] VOUT [V] 4,00 3,00 RL = 5kΩ 0,25 0,2 0,15 2,00 0,1 RL = 100Ω 1,00 0,05 0 0,00 0 2 4 6 8 0 10 50 75 100 IOUT [mA] VIN [V] Data Sheet 25 12 Rev. 1.0, 2012-05-07 TLF4949 Dropout Voltage VDR versus Junction Temperature TJ Quiescent Current IQ versus Output Current IOUT 3 0,4 VIN = 14V TJ = 25°C IOUT = 100mA 2,5 0,3 2 IQ [mA] VDR [V] IOUT = 50mA 0,2 1,5 IOUT = 10mA 1 0,1 0,5 0 -40 0 40 80 0 120 0,1 1 10 TJ [°C] 100 IOUT [mA] Quiescent Current IQSE versus Junction Temperature TJ Quiescent Current IQ versus Input Voltage VIN 3 300 TJ = 25°C VIN = 14V IOUT= 0.3mA 2,5 250 IQ [mA] IQSE [µA] 2 200 1,5 1 RLOAD = 5kΩ 150 0,5 RLOAD = 100Ω 0 100 -40 0 40 80 0 120 10 15 20 25 30 35 40 VIN [V] TJ [°C] Data Sheet 5 13 Rev. 1.0, 2012-05-07 TLF4949 Reset Thresholds VRT versus Junction Temperature TJ 6 4,8 5 4,7 4 4,6 VRT [V] VRO [V] Reset Output Voltage VRO versus Regulator Output Voltage VOUT 3 4,5 2 4,4 1 4,3 4,2 0 4 4,2 4,4 4,6 4,8 -40 5 0 40 Sense Thresholds VST versus Junction Temperature TJ 6 1,4 5 1,35 4 1,3 VST [V] VSO [V] Sense Output Voltage VSO versus Sense Input Voltage VSI 3 1,25 2 1,2 1 1,15 0 1,1 1,2 1,3 1,4 1,1 1,5 -40 VSI [V] Data Sheet 120 TJ [°C] VOUT [V] 1 80 0 40 80 120 TJ [°C] 14 Rev. 1.0, 2012-05-07 TLF4949 Application Information 5 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Application_diagram .vsd PRE Preregulator 5V VBatt IN OUT RO Reset Bandgap Reference SO SI GND Figure 4 D Application Diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application 5.1 Supply Voltage Transients For many other voltage regulators fast supply voltage transients can often be the cause of unwanted reset output signal perturbations. In contrast the TLF4949 shows a very high immunity of its reset output against such supply voltage transients. Already starting from input voltages as low as 5.5 V the TLF4949 shows an immunity of the reset output against supply transients of more than 100 V/µs even without an additional external capacitor at the PRE pin1) 2). 5.2 Functional Description Description The TLF4949 is a monolithic integrated low dropout voltage regulator. Several outstanding features and auxiliary functions are implemented to meet the requirements of supplying microprocessor systems in automotive applications. Nevertheless, it is suitable also in other applications where the present functions are required. The modular approach of this device allows to get easily also other features and functions when required. 1) Please note that also for the case of such input transients the absolute maximum ratings must not be violated. 2) The PRE pin of the IFX4949 offers the possibility to connect a bypass capacitor to GND to stabilize PRE output and to optimize the transient behaviour. See also section “Preregulator ” on Page 17. Data Sheet 15 Rev. 1.0, 2012-05-07 TLF4949 Application Information Voltage Regulator The voltage regulator uses a PNP transistor as a regulation element. With this structure a very low dropout voltage at currents of up to 100mA is obtained. The dropout operation of the standby regulator is maintained down to 3.5V input supply voltage. The output voltage is regulated up to a transient input supply voltage of 40V. With this feature no functional interruption due to over voltage pulses is generated. The typical curve showing the standby output voltage as a function of the input supply voltage VS is shown in Figure 5 “Output Voltage vs. Input Voltage” on Page 16.Typical values of the current consumption of this device at small loads (quiescent current) are less than 200µA. TJj ==25 25°C V VOUT [V] 5,00 0,00 0 5 10 15 40 VIN [V] Figure 5 Output Voltage vs. Input Voltage To reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region, the dropout voltage is controlled. The quiescent current as a function of the supply input voltage is shown for two different load conditions in Figure 6 “Quiescent Current vs. Supply Voltage” on Page 16. 3 TJ = 25 °C 2,5 IQ [mA] 2 1,5 1 RLOAD = 5 kΩ 0,5 RLOAD = 100 Ω 0 0 5 10 15 20 25 30 35 40 VIN [V] Figure 6 Quiescent Current vs. Supply Voltage Short Circuit Protection The maximum output current of the device is internally limited. In case of short circuit, the output current is foldback limited as described in Figure 7 “Foldback Characteristics of VOUT” on Page 17. Data Sheet 16 Rev. 1.0, 2012-05-07 TLF4949 Application Information 6,00 TJ = 25 V 5,00 VOUT [V] 4,00 3,00 2,00 1,00 0,00 0 0,05 0,1 0,15 0,2 0,25 0,3 IOUT [A] Figure 7 Foldback Characteristics of VOUT Preregulator To improve the transient immunity a preregulator stabilizes the internal supply voltage to 5V. This internal voltage is also present at the PRE pin (Pin 3). This voltage should not be used as an output because the output capability is very small (≤ 10 µA). This output at the PRE pin may be used as an option when an improved transient behavior for supply voltages less than 8V is desired. In this case a capacitor (100nF -1µF) can be connected between the PRE pin and GND. At the same time the usage of such a bypass capacitor is suitable to reduce output noise at the OUT pin. If this feature is not used the PRE pin must be left open. Reset Circuit The block circuit diagram of the reset circuit is shown in Figure 8 “Reset Circuit” on Page 18. The reset circuit supervises the output voltage. The reset threshold of 4.5V is defined by the internal reference voltage and standby output divider. The reset pulse delay time tRD, is defined by the charge time of an external capacitor CD: C D × 2.0 V t RD = -------------------------2.0 µA The reaction time of the reset circuit originates from the discharge time limitation of the reset capacitor CD and is proportional to the value of CD. Data Sheet 17 Rev. 1.0, 2012-05-07 TLF4949 Application Information Reset .vsd 2uA Ref 1,23V 22K Reset D OUT 2.0V VReg Figure 8 Reset Circuit The reaction time of the reset circuit corresponds to its noise immunity. Standby output voltage drops below the reset threshold that are only marginally longer than the reaction time will result in a shorter reset delay times. The nominal reset delay time will be generated for standby output voltage drops longer than approximately 50µs. The typical reset output waveforms are shown in Figure 9 “Typical Reset Output Waveforms” on Page 18. Reset _diagram.vsd OUT 40V VIN VOUT 5.0V VRT + 0.1V VRT 1.5V t tR Reset tRD Switch on Figure 9 Data Sheet tRR tRD Input drop Dump Output overload Switch off Typical Reset Output Waveforms 18 Rev. 1.0, 2012-05-07 TLF4949 Application Information Sense Comparator The sense comparator compares an input signal with the internal voltage reference of typical 1.23V. The use of an external voltage divider makes this comparator very flexible in the application. It can be used to supervise the input voltage either before or after a protection diode and to give additional informations to the microprocessor like low voltage warnings. Data Sheet 19 Rev. 1.0, 2012-05-07 TLF4949 Package Outlines 6 Package Outlines 0.1 2) 0.41+0.1 -0.06 0.2 8 5 1 4 5 -0.2 1) M B 0.19 +0.06 C 8 MAX. 1.27 4 -0.21) 1.75 MAX. 0.175 ±0.07 (1.45) 0.35 x 45˚ 0.64 ±0.25 6 ±0.2 A B 8x 0.2 M C 8x A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01181 Figure 10 Data Sheet PG-DSO-8 20 Rev. 1.0, 2012-05-07 TLF4949 Package Outlines 0.35 x 45˚ 1.27 0.41±0.09 2) 0.2 M 0.19 +0.06 0.08 C Seating Plane C A-B D 8x 0.64 ±0.25 D 0.2 6 ±0.2 8˚ MAX. C 0.1 C D 2x 1.7 MAX. Stand Off (1.45) 0.1+0 -0.1 3.9 ±0.11) M D 8x Bottom View 8 1 5 1 4 8 4 5 2.65 ±0.2 3 ±0.2 A B 4.9 ±0.11) 0.1 C A-B 2x Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width 3) JEDEC reference MS-012 variation BA Figure 11 PG-DSO-8-27-PO V01 PG-DSO-8 Exposed Pad Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on packages, please visit our website: http://www.infineon.com/packages. Data Sheet 21 Dimensions in mm Rev. 1.0, 2012-05-07 TLF4949 Revision History 7 Revision History Revision Date Changes 1.0 2012-05-07 Data Sheet – Initial Release. Data Sheet 22 Rev. 1.0, 2012-05-07 Edition 2012-05-07 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.