INFINEON TLE6262G

Fault Tolerant CAN - LDO
TLE 6262 G
Final Data Sheet
1
Overview
1.1
Features
• Standard fault tolerant differential CAN-transceiver
(TLE6254 LS CAN cell)
• Bus failure management
• Low power mode management
• CAN data transmission rate up to 125 kBaud
• Low-dropout voltage regulator 5V ± 2%
• Two Low Side Switches
• Three High Side Switches
• Power on and under-voltage reset generator
• Vcc supervisor
• Window watchdog
• Programable time base
• Integrated fail-safe mechanism
• Standard 16 bit SPI-Interface
• Wide input voltage and temperature range
• Enhanced power P-DSO-Package
P-DSO-28-6
Enhanced Power
Type
Ordering Code
Package
TLE 6262 G
on request
P-DSO-28-6
Description
The TLE 6262 G is a monolithic integrated circuit in a P-DSO-28-6 package, which
incorporates a failure tolerant low speed CAN-transceiver for differential mode data
transmission, a low dropout voltage regulator for internal and external 5V supply as well
as a 16 bit SPI interface to control and monitor the IC. Further there are integrated three
high side switches, two low side switches, a window watchdog circuit and a reset circuit.
Both, the window watchdog and reset function are referring to a time base that is
programmable via an external resistor.
The IC is designed to withstand the severe conditions of automotive applications.
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
1.2
Pin Configuration
(top view)
CANH 1
28 OSC
RTH 2
27 PWM
RO 3
26 TxD
CANL 4
25 RxD
RTL 5
24 Vcc
GND 6
23 GND
GND 7
22 GND
GND 8
21 GND
GND 9
20 GND
OUTH1 10
19 CLK
OUTL1 11
18 DI
OUTL2 12
17 DO
OUTH2 13
16 CSN
OUTH3 14
15 Vs
P-DSO-28-6
(enhanced power package)
Figure 1
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
1.3
Pin Definitions and Functions
Pin No.
Symbol
Function
1
CANH
CAN-H bus line; HIGH in dominant state
2
RTH
Termination input for CANH
3
RO
Reset output; open drain output; integrated pull up; active low
4
CANL
CAN-L bus line; LOW in dominant state
5
RTL
Termination input for CANL
6, 7, 8, 9, GND
20, 21,
22, 23
Ground; to reduce thermal resistance place cooling areas on
PCB close to this pins.
10
OUTH1
High side output 1; controlled via PWM input and/or SPI input,
short circuit protected
11
OUTL1
Low side output 1; SPI controlled, with active zener
12
OUTL2
Low side output 2; SPI controlled, with active zener
13
OUTH2
High side output 2; SPI controlled
14
OUTH3
High side output 3; SPI controlled, in low power mode controlled
by internal autotiming function if selected
15
VS
Power supply; block to GND directly at the IC with ceramic
capacitor
16
CSN
SPI interface chip select not; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when CLK is low; CSN has an
internal active pull up and requires CMOS logic level inputs
17
DO
SPI interface data out; this tristate output transfers diagnosis
data to the control device; the output will remain 3-stated unless
the device is selected by a low on Chip-Select-Not (CSN); see
table 3 for diagnosis protocol
18
DI
SPI interface data in; receives serial data from the control
device; serial data transmitted to DI is a 16 bit control word with
the Least Significant Bit (LSB) being transferred first: the input
has an active pull down and requires CMOS logic level inputs; DI
will accept data on the falling edge of CLK-signal; see table 2 for
input data protocol
19
CLK
SPI interface clock input; clocks the shiftregister; CLK has an
internal active pull down and requires CMOS logic level inputs
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
1.3
Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Function
24
VCC
Output voltage regulator; 5V logic supply, block to GND with an
100nF external ceramic capacitor directly at the IC + external
capacitor CQ ³ 22 µF
25
RxD
CAN Receive data output;
26
TxD
CAN Transmit data input; integrated pull up
27
PWM
Pulse width control; for high side switch 1
28
OSC
Oscillator input; time base for power on reset, watchdog window
and stand by timer for HS3, to program connect external resistor
to GND
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
1.4
Functional Block Diagram
OUTL1
Drive
Charge
Pump
OUTL2
Drive
Vs
OUTH1
Switch
Fail Detect
Protection + Drive
PWM
OUTH2
Drive
OUTH3
CSN
Drive
UVLO
CLK
SPI
POR
DI
DO
Vcc
Timer
+
Reset
Generator
+
Window
Watchdog
Band
Gap
OSC
RO
CAN
Standby / Sleep Control
CANH
H Output Stage
CANL
L Output Stage
RTH
Filter
Receiver
Fail Management
RTL
Driver
TxD
Temp.
Protect
Input
Stage
RxD
CAN Fail Detect
GND
Figure 2
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
1.5
Circuit Description
The TLE 6262 G is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for
internal and external 5V supply as well as a SPI interface to control and monitor the IC.
Further there are integrated three high side switches, two low side switches, a window
watchdog circuit and a reset circuit. Both, the window watchdog and reset function are
referring to a time base that is programmable via an external resistor.
Figure 2 shows a block schematic diagram of the TLE 6262 G
Table 1: mode truth table
Feature
normal mode
Receive-only
mode
VBAT stand-by
mode
VCC
ON
ON
ON
Reset
ON
ON
ON
Watchdog
ON1)
ON1)
ON1)
SPI
ON
ON
ON
CAN transmit
ON
OFF
OFF
CAN receive
ON
ON
OFF2)
OUTHS 13) 4) 5)
ON
ON
ON
OUTHS 23) 5)
ON
ON
ON
OUTHS 33) 5)
ON
ON
ON
OUTHS3-auto timing3) 5)
OFF
ON
ON
OUTLS 13) 6)
ON
ON
ON
OUTLS 23) 6)
ON
ON
ON
1)
at low VCC output current only active when watchdog undercurrent function is not activated
2)
a bus wake-up is monitored by setting the RxD output low
3)
only active when selected via SPI
4)
also active when driven via the PWM input
5)
automatically disabled when a reset occurs
6)
automatically disabled when a reset or watchdog reset respectively, occurs or the watchdog is disabled
by the undercurrent function
6
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
CAN Transceiver
The TLE 6262 is optimized for low speed data transmission up to 125 kbaud in
automotive applications. Normally a differential signal is transmitted or received
respectively. When a bus wiring failure (see table 4) is detected the device automatically
switches to a dedicated CANH or CANL single-wire mode to maintain the communication
if necessary. Therefore it is equipped with one differential receiver and four single ended
comparators (two for each bus line). To avoid false triggering by external RF influences
the single wire modes are activated after a certain delay time. As soon as the bus failure
disappears the transceiver switches back to differential mode after another time delay.
The bus failures are monitored via the diagnosis protocol of the SPI. Therefore it is
possible to distinguish 6 CAN bus failures or failure groups on the bits 8 to 13 (see table
3).
To reduce EMC caused by the transceiver the dynamic slopes of the CANL and CANH
signals are both limited and symmetric. This allows the use of an unshielded twisted or
parallel pair of wires for the bus. During single-wire transmission (bus-failure) the EMC
performance of the system is degraded from the differential mode.
The differential receiver threshold is set to typ. -2.8 V. This ensures correct reception in
the normal operation mode as well as in the failure cases 1, 2, 3a and 4 with a noise
margin as high as possible. When one of the bus failures 3, 5, 6, 6a, and 7 is detected,
the defective bus wire is disabled by switching off the affected bus termination and output
stage.
The CAN-transceiver offers three different operation modes that are controlled via the
SPI: the normal operation mode, Receive-only mode and Vbat stand-by mode. Please
see the state diagram (figure 3). In the Vbat stand-by mode the RTL output voltage is
switched to VS.
In case of a wake-up via the bus lines or one of the bus lines respectively, the TLE 6262
automatically sets the RxD output LOW. To send respectively receive messages the
CAN-transceiver can now be set in normal operation mode or receive-only mode by the
microcontroller.
When a reset occurs the transceiver circuit is automatically switched to Vbat-stand-by
mode because the SPI input bits are automatically set LOW for this event.
A thermal shutdown of the CAN-transceiver circuit is monitored via the SPI diagnosis
bit 15.
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Start Up
Power Up
Normal Mode
NSTB
1
ENT
ENT
1
0
V CC
ON
ENT
NSTB
0
ENT
0
NSTB
ENT
V CC
ON
1
1
NSTB
ENT
or
VCC
1
NSTB
VCC
RxD-Only
NSTB
1
NSTB
ENT
NSTB
0 or
VRT
0
0
VRT
Vbat Stand-By
NSTB
0
1
ENT
0
VCC
ON
0
1
Go- To-Sleep
Mode
NSTB
0
ENT
1
V CC
ON
ENT
1
Figure 3: State Diagram
Low Dropout Voltage Regulator
The TLE 6262 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance
is less than ± 2%. In addition the regulator circuit drives the internal loads like the CANtransceiver circuit.
An external reverse current protection is recommended to prevent the output capacitor
from being discharged by negative transients or low input voltage.
Stability of the output voltage is guaranteed for output capacitors CVCC ³ 100 nF.
Nevertheless a lot of applications require a much larger output capacitance to buffer the
output voltage in case of low input voltage or negative transients. Furthermore the due
function of e.g. the reset and 3V-supervisor circuit are supported by a larger output
capacitance because of their reaction times. Therefore a output capacitance
CVCC ³ 10 µF is recommended.
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
SPI (serial peripheral interface)
The 16-bit wide programming word or input word (see table 1) is read in via the data input
DI, and this is synchronized with the clock input CLK supplied by the µC. The diagnosis
word appears synchronously at the data output DO (see table 3).
The transmission cycle begins when the chip is selected by the chip select not input CSN
(H to L). After the CSN input returns from L to H, the word that has been read in becomes
the new control word. The DO output switches to tristate status at this point.
For details of the SPI timing please refer to figure 3 to 7.
Oscillator
All internal delay times are referring to the internal oscillator frequency, which is set by
an external resistor from pin OSC to GND. The oscillator frequency and the resulting
internal cycling time can be calculated by the equations:
9
28, 45 ´10 [ Hz W ]
f OSC = ----------------------------------------R OSC
32
t CYL = -----------f OSC
Window Watchdog, Reset and 3V-Supervisor
When the output voltage VCC exceeds the reset threshold voltage VRT the reset output
RO is switched HIGH after a delay time of 16 cycles. This is necessary for a defined start
of the microcontroller when the application is switched on. As soon as an under-voltage
condition of the output voltage (VCC < VRT) appears, the reset output RO is switched
LOW again. The LOW signal is guaranteed down to an output voltage VCC ³ 1V. Please
refer to fig.11, reset timing diagram.
Should the output voltage fall short of the 3V-supervisor threshold VST an internal flipflop is set LOW. The SPI diagnosis bit 7 monitors this. In normal operation this flip-flop
has to be activated via the SPI input bit 7. This feature is useful e.g. to monitor that the
RAM data of the microcontroller might be damaged or the application is connected to VS
the first time.
After the above described delayed reset (LOW to HIGH transition of RO) the window
watchdog circuit is started by opening a long open window of 32 cycles. Now the
microcontroller has to service a watchdog trigger signal via the SPI interface (input bit 0).
A watchdog trigger is detected as a falling edge by sampling for 2 cycles a HIGH followed
by 2 cycles LOW of the SPI input bit 0. The long open window ensures a simple and fast
9
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
synchronization of the TLE 6262 watchdog timing to the watchdog services of the
microcontroller.
After the first trigger the watchdog has to be serviced by meeting an open window of 20
cycles that follows a closed window of 12 cycles. A correct watchdog service
immediately results in starting the next closed window. Please refer to fig. 10, watchdog
timing diagram.
If the trigger signal does not meet the open window (trigger to early or to late) the reset
output RO is set LOW for a period of 4 cycles. Afterwards a long open window is started
again. In addition, the SPI diagnosis bit 2 is set HIGH to monitor a watchdog reset.
Both, the undervoltage reset and the watchdog reset are setting all SPI input bits LOW.
To avoid a cyclic wake-up of the microcontroller in low power mode (sleep mode) the
watchdog circuit can be automatically disabled at low output currents (ICC < ICCWD). To
activate this feature the SPI input bit 8 has to be set HIGH. In this under-current mode
the low side switches are switched off automatically by the TLE 6262 to guarantee failsave operation of the application. When the microcontroller returns back to normal mode
(ICC > ICCWD) the first closed window is transformed to an open window so that the total
open window time is 32 cycles. This ensures a more simple and fast synchronization of
the TLE 6262 watchdog timing to the watchdog services of the microcontroller.
Flash program mode
To disable the watchdog feature a flash program mode is available. This mode is
selected by applying a voltage of 6.8V < VPWM < 7.2V at pin PWM. This is useful e.g. if
the flash-memory of the micro has to be programmed and therefore a regular watchdog
triggering is not possible. If the SPI is required in the flash program mode to change e.g.
the mode of the TLE6262 the first input telegram has to be “00000000”.
High Side Switch 1
The high side output OUTH1 is able to switch loads up to 250 mA. Its on-resistance is
1.0 W typ. @ 25°C. This switch can be controlled either via the PWM input or the SPI
input bit 1. When the input PWM is used it has to be enabled by setting the SPI input bit
11 HIGH. In case of both control inputs being active the PWM signal is masked by the
SPI signal (see fig. 8, High Side Switch 1 Timing Diagram).
The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0
flags a thermal prewarning. By this the microcontroller is able to reduce the power
dissipation of the TLE 6262 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. Further OUTH1 is protected
against short circuit and overload. The SPI diagnosis bit 1 indicates an overload of
OUTH1. As soon as the under-voltage condition of the supply voltage is met (VS <
VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit.
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
This is flagged by the SPI diagnosis bit 3. Moreover the switches are disabled when a
reset occurs.
High Side Switch 2
The high side output OUTH2 is able to switch loads up to 250 mA. Its on-resistance is
1.0 W typ. @ 25°C. This switch is controlled via the SPI input bit 2.
The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0
flags a thermal prewarning. By this the microcontroller is able to reduce the power
dissipation of the TLE 6262 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. As soon as the under-voltage
condition of the supply voltage is met (VS < VUVOFF), the switches are automatically
disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3.
Moreover the switches are disabled when a reset occurs.
High Side Switch 3
The high side output OUTH3 is able to switch loads up to 150 mA. Its on-resistance is
1.5 W typ. @ 25°C. This switch is controlled via the SPI input bits 3 and 4. To supply
external wake-up circuits in low power mode (sleep mode or Vbat-stand-by mode), the
output OUTH3 can be periodically activated by the internal oscillator circuit. For
activating this feature the SPI input bits 3 and 4 have to be set HIGH. The autotiming
period is 128 internal cycle times; the on-time is 2 cycles. In case of a watchdog reset
the autotiming period may be shorter.
The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0
flags a thermal prewarning. By this the microcontroller is able to reduce the power
dissipation of the TLE 6262 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. As soon as the under-voltage
condition of the supply voltage is met (VS < VUVOFF), the switches are automatically
disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3.
Moreover the switches are disabled when a reset occurs.
Low Side Switches 1/2
The two low side outputs OUTL1 and OUTL2 are able to switch loads up to 100 mA.
Their on-resistance is 1.5 W (typ.) @ 25°C. This switches are controlled via the SPI input
bits 5 and 6. In case of high inrush currents a built in zener circuit (typ. 37 V) activates
the switches to protect them.
The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0
flags a thermal prewarning. By this the microcontroller is able to reduce the power
dissipation of the TLE 6262 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. The SPI diagnosis bits 5/6
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
are giving a feedback about current status of OUTL1/OUTL2. As soon as the undervoltage condition of the supply voltage is met (VS < VUVOFF), the switches are
automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI
diagnosis bit 3. In addition the outputs OUTL1 and OUTL2 are also disabled when the
watchdog is switched off in undercurrent state or when a reset occurs.
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Table 2
Table 3
Input Data Protocol
Diagnosis Data Protocol
BIT
BIT
15
not used
15
Thermal Shutdown Transceiver
14
not used
14
Thermal Shutdown Switches
13
not used
13
CAN Failure 2 and 4
12
not used
12
CAN Failure 1 and 3a
11
PWM Enable
11
CAN Failure 6
10
CAN Enable Transmit
10
CAN Failure 6a
9
CAN Not Stand-By
9
CAN Failure 6a, 5 and 7
8
Watchdog Control
8
CAN Failure 3
7
Supervisor Enable
7
Vcc < 3V
6
LS-Switch 2
6
Status LS2
5
LS-Switch 1
5
Status LS1
4
HS3 Auto Timing
4
not used
3
HS-Switch 3
3
Vs Undervoltage Lockout
2
HS-Switch 2
2
Window Watchdog Reset
1
HS-Switch 1
1
Overload HS1
0
Watchdog Trigger
0
Temperature Prewarning
H = ON
L = OFF
H = ON
L = OFF
13
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Table 4
CAN bus line failure cases (according to ISO 11519-2)
failure
#
failure description
1
CANL line interrupted
2
CANH line interrupted
3
CANL shorted to Vbat, CANL > 7.2 V
3a (no ISO failure) CANL shorted to Vcc; 3.2 V < CANL < 7.2 V
4
CANH shorted to GND
5
CANL shorted to GND
6
CANH shorted to Vbat; CANH > 7.2 V
6a (no ISO failure) CANH shorted to Vcc; 1.8 V < CANH < 7.2 V
7
CANL shorted to CANH
14
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2
Electrical Characteristics
2.1
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
-0.3
28
V
–
-0.3
40
V
tp< 0.5s; tp/T < 0.1
-0.3
5.5
V
-10
28
V
-40
40
V
VS >0 V
tp< 0.5s; tp/T < 0.1
-0.3
VCC
V
0 V < VS < 24 V
0 V < VCC < 5.5 V
V
0 V < VS < 24 V
0 V < VCC < 5.5 V
V
0 V < VS < 24 V
0 V < VCC < 5.5 V
Voltages
Supply voltage
Supply voltage
Regulator output voltage
CAN input voltage (CANH, CANL)
CAN input voltage
(CANH, CANL)
VS
VS
VCC
VCANH/L
VCANH/L
Logic input voltages (DI, CLK, VI
CSN, OSC, PWM, TxD)
+0.3
Logic output voltage
(DO, RO, RxD)
VDO/RO/RD -0.3
VCC
Termination input voltage
(RTH, RTL)
VTL /TH
Electrostatic discharge
voltage at pin CANH, CANL
VESD
-4000
4000
V
human body model;
C = 100pF, R = 1.5kW
Electrostatic discharge
voltage
VESD
-2000
2000
V
human body model;
C = 100pF, R = 1.5kW
ICC
IOUTH1
IOUTH2
IOUTH3
IOUTL1
IOUTL2
–
–
A
internally limited
*)
0.3
A
*) internally limited
-0.7
0.3
A
tp< 0.5s; tp/T < 0.1
-0.5
0.2
A
tp< 0.5s; tp/T < 0.1
-0.2
0.4
A
tp< 0.5s; tp/T < 0.1
-0.2
0.4
A
tp< 0.5s; tp/T < 0.1
+0.3
-0.3
VS
+0.3
Currents
Output current; Vcc
Output current; OUTH1
Output current; OUTH2
Output current; OUTH3
Output current; OUTL1
Output current; OUTL2
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version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.1
Absolute Maximum Ratings (cont’d)
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
-40
150
°C
–
-50
150
°C
–
Temperatures
Junction temperature
Storage temperature
Tj
Tstg
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause
irreversible damage to the integrated circuit.
16
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.2
Operating Range
Parameter
Symbol
Limit Values
min.
Unit
Remarks
max.
Supply voltage
VS
VUV OFF 27
V
After VS rising above
VUV ON
Supply voltage slew rate
dVS /dt
-0.5
5
V/ms
–
Supply voltage increasing
VS
VS
VI
-0.3
VUV ON V
VUV OFF V
VCC
V
Supply voltage decreasing
Logic input voltage (DI, CLK,
CSN, PWM, TxD)
-0.3
-0.3
22
OSC-Adjust Resistor
ICC
ICC
CCC
fCLK
ROSC
Junction temperature
Output current
Output current
Output capacitor
SPI clock frequency
35
mA
45
mA
Outputs in tristate
Outputs in tristate
–
T < 0.1s
mF
–
1
MHz
–
51
680
kW
Ta=-40°C; f = 10kHz
Tj
-40
150
°C
–
Rthj-pin
Rthj-a
–
25
K/W
measured to pin 7
–
65
K/W
–
Thermal Resistances
Junction pin
Junction ambient
Thermal Prewarning and Shutdown (junction temperatures)
Thermal prewarning
ON temperature
TjPW
120
170
°C
bit 0 of SPI diagnosis
word;
hysteresis 30°K (typ.)
Thermal shutdown temp.
TjSD
150
200
°C
hysteresis 30°K (typ.)
Ratio of SD to PW temp.
TjSD / TjPW 1.05
–
–
160
°C
Thermal shutdown temp. CAN TjSD
135
17
–
hysteresis 10°K (typ.)
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
IS
ISSB1
–
5
10
mA
–
180
280
mA
low power mode;
VS=12V; Tj=25°C
4.9
5.0
5.2
V
0.1mA < ICC< 30mA
4.8
5.0
5.5
V
0A < ICC < 100µA
Line regulation
VCC
VCC
,VCC
-20
20
mV
9 V < VS < 15 V;
ICC = 10mA
Load regulation
,VCC
-25
25
mV
0.1mA < ICC< 30mA;
VS = 9V
40
dB
VS < 1 Vss;
CQ ³ 22µF;
100Hz< f <100kHz
60
mA
1)
V
ICC = 30 mA;
see note 1)
kHz
ROSC = 453kW
µs
ROSC = 453kW
Quiescent current Pin VS
Current consumption
Quiescent current
ISSB1 = IS - ICC
Voltage Regulator; Pin VCC
Output voltage
Output voltage
Power supply ripple rejection PSRR
Output current limit
Drop voltage
VDR = VS - VCC
ICCmax
VDR
45
0.15
0.45
Oscillator; Pin OSC
Oscillating frequency
Internal cycling time
(1/32 * fOSC)-1
fOSC
tCYL
62.8
383
509
637
1) measured when the output voltage VCC has dropped 100 mV from the nominal value obtained at 13.5 V input
voltage VS
18
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
4.0
4.3
4.65
V
Reset low output voltage
VRT
VRO
0.2
0.4
V
Reset high output voltage
VRO
4.0
Reset Generator; Pin RO
Reset threshold voltage
IRO = 1mA
(VCC ³ VRT) or
VCC ³ 1V
(IRO = 200 µA)
VCC+ V
0.1
20
150
500
mA
VRO = 0V
Reset reaction time
IRO
tRR
1
3
10
µs
VCC < VRT to
RO = L
Reset delay time (16 cyl.)
tRD
6.1
8.1
10.2
ms
ROSC = 453kW
2.3
2.7
3.1
V
2
8
20
µs
VCC < VST to
diagnosis bit 7 = L
7.6
10
12.3
ms
ROSC = 453kW
4.6
6.1
7.6
ms
ROSC = 453kW
7.7
10.2
12.7
ms
ROSC = 453kW
1.5
2.0
2.6
ms
ROSC = 453kW
2
4
12
mA
Tj < 85 °C; Watchdog
OFF when
ICC < ICCWD and SPIinput bit 8 = H
Reset pull up current
3 V Supervisor; (bit 7 of SPI diagnosis word)
Supervisor threshold voltage VST
Supervisor reaction time
tSR
Watchdog Generator
tWD
Closed window time (12 cyl.) tCW
Open window time (20 cyl.) tOW
Watchdog reset-puls time
tWDR
Watchdog trigger time
(4 cyl.)
Watchdog activating current
ICCWD
Watchdog activating current
hysteresis
ICCWDhys
0.5
19
mA
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Long open window (32 cyl.)
Symbol
ICCWDhys
Limit Values
Unit Test Condition
min.
typ.
max.
12.2
16.2
20.4
ms
ROSC = 453kW
sleep mode (WD OFF)
to normal mode
Switches
Under-Voltage Lockout (bit 3 of SPI diagnosis word)
UV-Switch-ON voltage
UV-Switch-OFF voltage
UV-ON/OFF-Hysteresis
VUV ON
VUV OFF
VUV HY
–
5.35
6.00
V
VS increasing
4.50
4.85
5.20
V
VS decreasing
–
0.5
–
V
VUV ON – VUV OFF
High Side Output OUTH1; (controlled by PWM or bit 1 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTH1 = -0.25 A
RDSON H1 –
VOUTH1
Clamp diode forward voltage VOUTH1
Leakage current
IOLH1
Switch ON delay time
tdONH1
Active zener voltage
-5.0
-100
1.0
2.0
W
1.5
4.0
W
5.2 V £ VS £ 9 V
-3.0
-0.5
V
IOUTH1 = – 0.25 A
0.8
1
V
IOUTH1 = 0.25 A
-5
–
µA
VOUTH1 = 0 V
10
100
ms
PWM to OUTH1;
RL = 100 W
20
100
ms
PWM to OUTH1;
RL = 100 W
–
Switch OFF delay time
tdOFFH1
Overcurrent shutdown
threshold
ISDH1
-1.0
-0.6
-0.3
A
Shutdown delay time
tdSDH1
IOCLH1
10
25
50
ms
-2.0
-1.0
-0.5
A
Current limit
20
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
PWM Input to control OUTH1; Pin PWM (high active)
H-input voltage threshold
VIH
–
–
0.7
´VCC
V
–
L-input voltage threshold
VIL
0.2
´Vcc
–
–
V
–
Hysteresis of input voltage
VIHY
II
CI
50
200
500
mV
–
5
25
180
mA
VI = 0.2 * VCC
–
10
15
pF
0 V < VCC < 5.25 V
Pull down current
Input capacitance
High Side Output OUTH2; (controlled by bit 2 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTH2 = -0.25 A
RDSON H2 –
VOUTH2
Clamp diode forward voltage VOUTH2
Leakage current
IOLH1
Switch ON delay time
tdONH1
Active zener voltage
Switch OFF delay time
-5.0
-100
tdOFFH1
1.0
2.0
W
1.5
4.0
W
5.2 V £ VS £ 9 V
-3.0
-0.5
V
IOUTH2 = – 0.25 A
0.8
1
V
IOUTH2 = 0.25 A
-5
–
µA
VOUTH2 = 0 V
10
100
µs
CSN high to OUTH2;
RL = 100 W
20
100
µs
CSN high to OUTH2;
RL = 100 W
High Side Output OUTH3; (controlled by bit 3 and bit 4 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTH3 = -0.15 A
RDSON H3 –
VOUTH3
Clamp diode forward voltage VOUTH3
Leakage current
IOLH3
Active zener voltage
-5.0
-100
21
1.5
3.0
W
2.0
5.0
W
5.2 V £ VS £ 9 V
-3.0
-0.5
V
IOUTH3 = – 0.15 A
0.8
1
V
IOUTH3 = 0.15 A
-5
–
µA
VOUTH3 = 0 V
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Switch ON delay time
IOLH3
tdONH3
Switch OFF delay time
tdOFFH3
Auto time period
(128 cyl.)
tPH3
Auto time ON duty cycle
(2 cyl.)
D.C.
Leakage current
Limit Values
min.
typ.
–
5
49
Unit Test Condition
max.
µA
VOUTH3 = 5 V
10
100
µs
CSN high to OUTH3;
RL = 100 W
20
100
µs
CSN high to OUTH3;
RL = 100 W
65
82
ms
ROSC = 453kW;
SPI-bit 4 = H,
no WD reset
1/64
referring to tPH3
Low Side Output OUTL1 (bit 5 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTL1 = 0.1 A
RDSON L1
Active zener clamp voltage
Leakage current
VOUTL1
IOLL1
Switch ON delay time
tdONL1
Switch OFF delay time
tdOFFL1
–
32
1.5
3.0
W
2.0
5.0
W
5.2 V £ VS £ 9 V
37
42
V
IOUTL1 = – 0.1 A
5
µA
VOUTL1 =15 V;
Tj < 85°C
5
50
µs
CSN high to OUTL1;
RL = 100 W
5
50
µs
CSN high to OUTL1;
RL = 100 W
1.5
3.0
W
2.0
5.0
W
5.2 V £ VS £ 9 V
37
42
V
IOUTL2 = – 0.1 A
5
µA
VOUTL2 =15 V;
Tj < 85°C
Low Side Output OUTL2 (bit 6 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTL2 = 0.1 A
RDSON L2
Active zener clamp voltage
Leakage current
VOUTL2
IOLL2
Switch ON delay time
tdONL2
5
50
µs
CSN high to OUTL2;
RL = 100 W
Switch OFF delay time
tdOFFL2
5
50
µs
CSN high to OUTL2;
RL = 100 W
–
32
22
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
VCC
–
VCC
V
I0 = – 250µA
–
0.9
V
I0 = 1.25mA
CAN-Transceiver
Receiver Output R´D
HIGH level output voltage
VOH
– 0.9
LOW level output voltage
VOL
0
Transmission Input T´D
HIGH level input voltage
threshold
VIH
LOW level input voltage
threshold
VIL
HIGH level input current
0.52´ 0.70´ V
VCC
VCC
0.30´ 0.48´
V
VCC
VCC
IIH
IIL
-140
-40
-10
µA
Vi = 4 V
-600
-200
-40
µA
Vi = 1 V
Differential receiver
recessive-to-dominant
threshold voltage
VdRxD(rd)
-2.8
-2.5
-2.2
V
Differential receiver
dominant-to-recessive
threshold voltage
VdRxD(dr)
-3.1
-2.9
-2.5
V
CANH recessive output
voltage
VCANHr
0.1
0.2
0.3
V
TxD = VCC;
RRTH < 4 kW
CANL recessive output
voltage
VCANLr
VCC
–
–
V
TxD = VCC;
RRTL < 4 kW
CANH dominant output
voltage
VCANHd
VCC
VCC
VCC
V
-1.4
-1.0
TxD = 0 V;
ICANH = – 40 mA
LOW level input current
Bus Lines CANL, CANH
- 0.2
23
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
CANL dominant output
voltage
VCANLd
–
1.0
1.4
V
TxD = 0 V;
ICANL = 40 mA
CANH output current
ICANH
-110
-80
-50
mA
VCANH = 0 V;
TxD = 0 V
-5
0
5
µA
sleep mode;
VCANH = 12 V
50
80
110
mA
VCANL = 5 V;
TxD = 0 V
-5
0
5
µA
sleep mode;
VCANL = 0 V;
VS = 0 V
6.5
7.3
8.0
V
normal operation
mode
CANL output current
ICANL
Voltage detection threshold Vdet(th)
for short-circuit to battery
voltage on CANH and CANL
CANH wake-up voltage
threshold
VWAKEH
1.2
1.9
2.7
V
–
CANL wake-up voltage
threshold
VWAKEL
2.2
3.1
3.9
V
–
CANH single-ended receiver VCANH
threshold
1.6
2.1
2.6
V
failure cases 3, 5 and
7
CANL single-ended receiver
threshold
VCANL
2.4
3.0
3.4
V
failure case 6 and 6a
CANL leakage current
ICANLl
-5
0
5
µA
VCC = 0 V, VS = 0 V,
VCANL = 13.5 V,
Tj < 85 °C
CANH leakage current
ICANHl
-5
0
5
µA
VCC = 0 V;VS = 0 V;
VCANH = 5 V;
Tj < 85 °C
Termination Outputs RTL, RTH
RTL to VCC switch-on
resistance
RRTL
–
40
95
W
Io = – 10 mA;
RTL to BAT switch series
resistance
RoRTL
5
15
30
kW
VBAT-stand-by
24
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
RTH to ground switch-on
resistance
RRTH
–
40
95
W
Io = 10 mA
RTH output voltage
VoRTH
–
0.7
1.0
V
Io = 1 mA;
Vbat-stand-by mode
RTH pull-down current
IRTHpd
IRTLpu
40
75
120
µA
failure cases 6 and 6a
-120
-75
-40
µA
failure cases 3, 3a, 5
and 7
RTL pull-up current
25
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
CANH and CANL bus output trd
transition time recessive-todominant
0.6
1.2
2.1
µs
10% to 90%;
C1 = 10 nF;
C2 = 0; R1 = 100 W
CANH and CANL bus output tdr
transition time dominant-torecessive
0.3
0.6
1.3
µs
10% to 90%;
C1 = 1 nF; C2 = 0; R1 =
100 W
stand-by mode;
VS = 13.5 V
CAN-Transceiver
Dynamic Characteristics
Minimum dominant time for
wake-up on CANL or CANH
twu(min)
12
20
38
µs
Failure cases 3 and 6
detection time
tfail
30
45
80
µs
Failure case 6a detection
time
2.0
4.8
8.0
ms
Failure cases 5, 6, 6a and 7
recovery time
30
45
80
µs
Failure cases 3 recovery time
250
500
750
µs
Failure cases 5 and 7
detection time
1.0
2.0
4.0
ms
0.4
1.0
2.4
ms
stand-by modes;
VS = 13.5 V
Failure cases 6, 6a and 7
detection time
0.8
4.0
8.0
ms
stand-by modes;
VS = 13.5 V
Failure cases 5, 6, 6a and 7
recovery time
0.4
1.0
2.4
µs
stand-by modes;
VS = 13.5 V
Failure cases 5 detection
time
tfail
26
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
–
1.5
2.1
µs
C1 = 100 pF;
C2 = 0; R1 = 100 W; no
failures and bus failure
cases 1, 2, 3a and 4
–
1.7
2.4
µs
C1 = C2 = 3.3 nF;
R1 = 100 W; no bus
failure and failure
cases 1, 2, 3a and 4
–
1.8
2.5
µs
C1 100 pF; C2 = 0;
R1 = 100 W; bus failure
cases 3, 5, 6, 6a and 7
–
2.0
2.6
µs
C1 = C2 = 3.3 nF;
R1 =100 W; bus failure
cases 3, 5, 6, 6a and 7
–
1.5
2.0
µs
C1 = 100 pF;
C2 = 0; R1 =100 W; no
failures and bus failure
cases 1, 2, 3a and 4
–
2.5
3.5
µs
C1 = C2 = 3.3 nF;
R1 = 100 W; no bus
failure and failure
cases 1, 2, 3a and 4
–
1.0
2.1
µs
C1 100 pF; C2 = 0;
R1 = 100 W; bus failure
cases 3, 5, 6, 6a and 7
–
1.5
2.6
µs
C1 = C2 = 3.3 nF;
R1 = 100 W; bus failure
cases 3, 5, 6, 6a and 7
ne
Edge-count difference
(falling edge) between CANH
and CANL for failure cases 1,
2, 3a and 4 detection
–
4
–
–
Edge-count difference (rising
edge) between CANH and
CANL for failure cases 1, 2,
3a and 4 recovery
–
2
–
–
1.3
2.0
3.5
ms
Propagation delay
tPD(L)
TxD-to-RxD LOW (recessive
to dominant)
Propagation delay
tPD(H)
TxD-to-RxD HIGH (dominant
to recessive)
TxD permanent dominant
disable time
tTxD
27
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
VIH
–
–
0.7 *
VIL
0.3 *
VIHY
IICSN
IICLK/DI
SPI-Interface
Logic Inputs DI, CLK and CSN
H-input voltage threshold
L-input voltage threshold
Hysteresis of input voltage
Pull up current at pin CSN
Pull down current at pin DI
and CLK
Input capacitance
at pin CSN, DI or CLK
V
–
VCC
–
–
V
–
50
200
500
mV
–
-100
-25
-5
mA
VCSN = 0.7 ´ VCC
5
25
100
mA
VDI = 0.2 ´ VCC
CI
–
10
15
pF
0 V < VCC < 5.25 V
VDOH
VCC
VCC
–
V
IDOH = 1 mA
VCC
Logic Output DO
H-output voltage level
– 1.0 – 0.7
L-output voltage level
Tri-state leakage current
VDOL
IDOLK
–
0.2
0.4
V
IDOL = – 1.6 mA
-10
–
10
mA
VCSN = VCC
0 V < VDO < VCC
Tri-state input capacitance
CDO
–
10
15
pF
VCSN = VCC
0 V < VCC < 5.25 V
Data Input Timing
Clock period
Clock high time
Clock low time
Clock low before CSN low
tpCLK
tCLKH
tCLKL
tbef
1000
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
28
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
2.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
CSN setup time
CLK setup time
Clock low after CSN high
DI setup time
DI hold time
Input signal rise time
at pin DI, CLK and CSN
Input signal fall time
at pin DI, CLK and CSN
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
tlead
tlag
tbeh
tDISU
tDIHO
trIN
500
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
250
–
–
ns
–
250
–
–
ns
–
–
–
200
ns
–
tfIN
–
–
200
ns
–
trDO
tfDO
tENDO
tDISDO
tVADO
–
50
100
ns
CL = 100 pF
–
50
100
ns
CL = 100 pF
–
–
250
ns
low impedance
–
–
250
ns
high impedance
–
100
250
ns
VDO < 0.2 VCC;
VDO > 0.7VCC;
CL = 100 pF
Data Output Timing
DO rise time
DO fall time
DO enable time
DO disable time
DO valid time
29
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
3
Timing Diagrams
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register
CSN
time
CSN Low to High: Data from Shift-Register is transfered to Output Power Switches
CLK
1
0
2
3
5
4
6
7
8
10 11 12
9
13 14 15
0
1
2
3
4
5
_
6
7
8
1
new Data
actual Data
DI
0
9
10 11 12
0
+
13 14 15
1
+
DI: Data will be accepted on the falling edge of CLK-Signal
actual Status
previous Status
DO
_0
_1
_2
_3
4_
5_
_6
_7
_8
_9
_ 11
_ 12
_
10
_ 14
_ 15
_
13
0
1
DO: State will change on the rising edge of CLK-Signal
eg.
HS1
old Data
actual Data
Figure 4
Data Transfer Timing
30
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Figure 5
SPI-Input Timing
Figure 6
Turn OFF/ON Time
31
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Figure 7
DO Valid Data Delay Time and Valid Time
Figure 8
DO Enable and Disable Time
32
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Figure 9: High Side Switch1 Timing Diagram
SPI input
bit 1
H
L
PWM
(SPI input
bit 11 = H)
t
H
L
HSSwitch1
t
ON
OFF
t
33
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Figure 10: Watchdog Time-out Definitions
tWD
tCW
tOW
closed window
open window
t / ms
Figure 11: Watchdog Timing Diagram
tCW
WD
Trigger
tCW
tOW
tLOW
tCW+tOW
tOW
tLOW
tLOW
tCW
tLOW
tCW
tOW
tWDR
Reset
Out
t
Watchdog
timer reset
t
normal
operation
timeout
(to long)
34
normal
operation
timeout
(to short)
normal
operation
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Figure 12: Reset Timing Diagram
Vcc
VRT
t < tRR
VST
tRD
WD
Trigger
tLOW
tLOW
tCW
tOW
tRD
tLOW
tCW
Watchdog
timer reset
SPI
diagnosis
bit 7
start up
t
t
tRR
tWDR
Reset
Out
tCW
t
normal operation
tSR
undervoltage
start up
HIGH
LOW
t
activation by
microcontroller
35
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
4
Application
Vbat
CAN bus
+VS
CSN
CLK
DI
22 µF 68 nF
CANH
DQ
CANL
TxD
RxD
RTH
µP
PWM
RTL
RQ
OUTL2
OUTL1
Vcc
OUTH3
453 k9
OUTH2 OSC
OUTH1 GND
22 µF
GND
TLE 6262 G
Figure 13
Application Circuit
36
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
5
Package Outlines
GPS05123
P-DSO-28-6
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
37
version: 2.03 date: 2002-03-20
Final Data TLE 6262 G
Edition 1999-10-12
Published by Infineon Technologies AG
St.-Martin-Strasse 53
D-81541 München
© Infineon Technologies AG1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and
charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to
support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
38
version: 2.03 date: 2002-03-20