DATASHEET Multi-Cell Li-Ion Battery Manager ISL78610 Features The automotive grade ISL78610 12-cell battery pack monitor can be used as a stand-alone battery monitor or as a redundant back-up device in an ASIL compliant system. It supervises up to 12 series connected cells and features cell voltage and temperature monitoring along with system diagnostics. • Up to 12-cell voltage monitors, support Li-ion CoO2, Li-ion Mn2O4, and Li-ion FePO4 chemistries • Cell voltage measurement accuracy ±10mV • 13-bit cell voltage measurement • 14-bit pack voltage and temperature measurements The ISL78610 communicates to a host microcontroller via an SPI interface and to other ISL78610 devices using a robust, proprietary, two-wire daisy chain system. • Cell voltage scan rate of 19.5µs per cell (234µs to scan 12 cells) The ISL78610 is offered in a 64 Ld TQFP package and is specified for operation at a temperature range of -40°C to +105°C. • Up to four external temperature inputs • Internal and external temperature monitoring • Robust daisy chain communications system • Integrated system diagnostics for all key internal functions Applications • Hybrid Electric Vehicle (HEV), Plug-in Hybrid Electric Vehicle (PHEV) and Electric Vehicle (EV) battery packs • Integrated watchdog shuts down device if communication is lost • 2Mbps SPI • Electric motorcycle battery packs • AEC-Q100 qualified • Backup battery and energy storage systems requiring high accuracy management and monitoring Related Literature • Portable and semiportable equipment • UG077, “ISL78610EVKIT1Z Evaluation Kit User Guide” TO OTHER DEVICES (OPTIONAL) ISL78610 ISL78610 VG2 VG2 VG1 VG1 DHi2 DLo2 DHi2 DHi1 DLo2 DLo1 SCLK DOUT DIN CS DATA READY HOST MICRO FAULT EN VG1 VG1 MONITOR BOARD (Master or Stand-alone) VG2 MONITOR BOARD (Daisy Chain - Optional) FIGURE 1. TYPICAL APPLICATION June 16, 2016 FN8830.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78610 Table of Contents Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell/VBAT Reading Error - 3 Sigma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell/VBAT Reading Error - 5 Sigma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 16 Device Description and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 System Hardware Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery and Cell Balance Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supplies and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating with Reduced Cell Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes on Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Level Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 25 26 27 29 29 30 39 39 39 System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read and Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Voltages Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Temperatures Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Mixed Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Wires Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan All Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Continuous Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Inhibit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measure Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Monitoring Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Balance Enable Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Balance Inhibit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual Balance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timed Balance Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Balance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 40 41 41 41 41 42 42 42 43 43 43 44 44 45 45 45 46 47 47 Daisy Chain Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identify Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACK (Acknowledge) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAK (Not Acknowledge) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 51 51 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Daisy Chain Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 52 53 55 55 56 Submit Document Feedback 2 FN8830.1 June 16, 2016 ISL78610 CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 58 60 61 62 63 System Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 66 67 68 System Diagnostics Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Fault Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Out of Limit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Activity Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication Failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Communications Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Signal from Host. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 72 72 73 73 74 74 74 74 75 Fault Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Worked Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference Check Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Balancing – Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Balancing – Timed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Balancing – Auto Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 79 80 80 System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Voltage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Data, Secondary Voltage Reference Data, Scan Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set-Up Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Balance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Coefficient Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cells In Balance Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonvolatile Memory (EEPROM) Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 83 84 87 90 90 91 92 93 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Submit Document Feedback 3 FN8830.1 June 16, 2016 ISL78610 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TRIM VOLTAGE, VNOM (V) TEMP. RANGE (°C) PACKAGE (RoHS Compliant) 3.3 -40 to +105 64 Ld TQFP ISL78610ANZ ISL78610ANZ ISL78610EVKIT1Z Evaluation Kit for ISL78610 PKG. DWG. # Q64.10x10D NOTES: 1. Add “-T” suffix for 1k unit Tape and Reel option. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL78610. For more information on handling and processing moisture sensitive devices, please see Techbrief TB363. 4. For other trim options, please contact Intersil Automotive Marketing. TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS INITIAL CELL MONITOR VOLTAGE ERROR (mV) (Note 5) PART NUMBER ISL78600 2.0 (maximum) ISL78610 10.0 (maximum) NOTE: 5. Conditions: Temperature = -20°C to +60°C, VCELL = 2.6V to 4.0V, limits applied to a ±3 sigma distribution. Submit Document Feedback 4 FN8830.1 June 16, 2016 ISL78610 Pin Configuration VC10 CB11 VC11 CB12 VC12 VBAT VBAT NC DHi2 DLo2 NC SCLK/DHi1 CS/DLo1 NC DIN/NC DOUT/NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ISL78610 (64 LD 10x10 TQFP) TOP VIEW DNC CB4 13 36 V3P3 VC3 14 35 V2P5 CB3 15 34 VCC VC2 16 33 REF 32 37 VDDEXT 12 31 VC4 NC BASE 30 DNC 38 29 39 11 ExT4 10 CB5 TEMPREG VC5 28 COMMS SELECT 2 27 COMMS SELECT 1 40 NC 41 9 ExT3 8 CB6 26 VC6 25 COMMS RATE 1 NC 42 ExT2 COMMS RATE 0 7 24 43 CB7 ExT1 VC7 23 DGND 22 44 6 NC 5 VSS CB8 21 FAULT 20 DATA READY 45 VC0 46 4 VSS 3 VC8 19 CB9 18 EN VC1 DNC 47 CB1 48 2 17 1 VC9 CB2 CB10 Pin Descriptions SYMBOL VC0, VC1, VC2, VC3, VC4, VC5, VC6, VC7, VC8, VC9, VC10, VC11, VC12 PIN NUMBER DESCRIPTION 20, 18, 16, Battery cell voltage inputs. VCn connects to the positive terminal of CELLn and the negative terminal of 14, 12, 10, 8, CELLn+1. (VC12 connects only to the positive terminal of CELL12 and VC0 only connects with the negative 6, 4, 2, 64, 62, terminal of CELL1.) 60 19, 17, 15, Cell balancing FET control outputs. Each output controls an external FET, which provides a current path CB1, CB2, CB3, CB4, CB5, CB6, CB7, CB8, CB9, CB10, 13, 11, 9, 7, 5, around the cell for balancing. 3, 1, 63, 61 CB11, CB12 VBAT 58, 59 Main IC Supply pins. Connect to the most positive terminal in the battery string. VSS 21, 22 Ground. These pins connect to the most negative terminal in the battery string. ExT1, ExT2, ExT3, ExT4 TEMPREG Submit Document Feedback 24, 26, 28, 30 External temperature monitor or general purpose inputs. The temperature inputs are intended for use with external resistor networks using NTC type thermistor sense elements but may also be used as general purpose analog inputs at the user’s discretion. 0V to 2.5V input range. 29 5 Temperature monitor voltage regulator output. This is a switched 2.5V output, which supplies a reference voltage to external NTC thermistor circuits to provide ratiometric ADC inputs for temperature measurement. FN8830.1 June 16, 2016 ISL78610 Pin Descriptions (Continued) SYMBOL PIN NUMBER DESCRIPTION VDDEXT 32 External V3P3 supply input/output. Connected to the V3P3 pin via a switch, this pin may be used to power external circuits from the V3P3 supply. The switch is open when the ISL78610 is placed in Sleep mode. REF 33 2.5V voltage reference decoupling pin. Connect a 2.0µF to 2.5µF X7R capacitor to VSS. Do not connect any additional external load to this pin. VCC 34 Analog supply voltage input. Connect to V3P3 via a 33Ω resistor. Connect a 1µF capacitor to ground. V2P5 35 Internal 2.5V digital supply decoupling pin. Connect a 1µF capacitor to DGND. V3P3 36 3.3V digital supply voltage input. Connect the emitter of the external NPN regulator transistor to this pin. Connect a 1µF capacitor to DGND. BASE 38 Regulator control pin. Connect the external NPN transistor’s base. Do not let this pin float. DNC 37, 39, 48 COMMS SELECT 1 41 Communications Port 1 mode select pin. Connect via a 1kΩ resistor to V3P3 for daisy chain communications on Port 1 or to DGND for SPI operation on Port 1. COMMS SELECT 2 40 Communications Port 2 mode select pin. Connect via a 1kΩ resistor to V3P3 to enable Port 2 or to DGND to disable this port. COMMS RATE 0, COMMS RATE 1 43, 42 DGND 44 Digital Ground. FAULT 45 Logic fault output. Asserted low if a fault condition exists. DATA READY 46 SPI data ready. Asserted low when the device is ready to transmit data to the host microcontroller. EN 47 Enable input. Tie to V3P3 to enable the part. Tie to DGND to disable (all IC functions are turned off). DOUT/NC 49 Serial Data Output (SPI) or NC (daisy chain). 0V to 3.3V push-pull output. DIN/NC 50 Serial Data Input (SPI) or NC (daisy chain). 0V to 3.3V input. CS/DLo1 52 Chip-select, active low 3.3V input (SPI) or daisy chain Port 1 Lo connection. SCLK/DHi1 53 Serial-Clock Input (SPI) or daisy chain Port 1 Hi connection. DHi2 56 Daisy chain Port 2 High connection. DLo2 55 Daisy chain Port 2 Low connection. NC Submit Document Feedback Do not connect. Leave pins floating. Daisy chain communications data rate setting. Connect via a 1kΩ resistor to DGND (0) or to V3P3 (1) to select between various communication data rates. 23, 25, 27, No internal connection. 31, 51, 54, 57 6 FN8830.1 June 16, 2016 ISL78610 Block Diagram DHi 2 DLo 2 CONTROL LOGIC AND COMMUNICATIONS VBAT VC12 CB12 VC11 CB11 VC10 CB10 VC9 INPUT BUFFER/LEVEL SHIFT AND FAULT DETECTION CB9 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 SPI COMMS CS/DLo 1 DIN DOUT DATA READY COMMS RATE 1 COMMS RATE 0 COMMS SELECT 2 COMMS SELECT 1 DGND FAULT EN BASE VREG V3P3 VDDEXT V2P5 V2P5 VCC VREF MUX CB4 DAISY CHAIN AND REF VC MUX VC8 SCLK/DHi 1 VC3 ADC CB3 TEMPREG VC2 TEMP MUX IC TEMP VC1 CB1 VC0 REFERENCE CB2 ExT1 ExT2 ExT3 ExT4 VSS FIGURE 2. BLOCK DIAGRAM Submit Document Feedback 7 FN8830.1 June 16, 2016 ISL78610 Absolute Maximum Ratings Thermal Information Unless otherwise specified. With respect to VSS. BASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 5.5V DIN, SCLK, CS, DOUT, DATA READY, COMMS SELECT n, ExTn, TEMPREG, REF, V3P3, VCC, FAULT, COMMS RATE n, EN, VDDEXT . . . . . . .-0.2V to 4.1V V2P5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 2.9V VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 63V Dhi1, DLo1, DHi2, DLo2 . . . . . . . . . . . . . . . . . . . . . . .-0.5V to (VBAT + 0.5V) VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +9.0V VC1, VC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +18V VC3, VC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +27V VC5, VC6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +36V VC7, VC8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +45V VC9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +54V VC10, VC11, VC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +63V VCn (for n = 0 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VBAT +0.5V CBn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VBAT +0.5V CBn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . . V(VCn-1) -0.5V to V(VCn-1) +9V CBn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . . V(VCn) -9V to V(VCn) +0.5V Current into VCn, VBAT, VSS (Latch-Up Test) . . . . . . . . . . . . . . . . . . ±100mA ESD Rating Human Body Model (Tested per AECQ100-002) . . . . . . . . . . . . . . . . 2kV Charged Device Model (Tested per AECQ100-011) . . . . . . . . . . . . . . 2kV Latch-Up (Tested per AEC-Q100-004; Class 2, Level A) . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (C/W) θJC (C/W) 64 Ld TQFP Package (Notes 6, 7) . . . . . . . 42 9 Maximum Continuous Package Power Dissipation . . . . . . . . . . . . .400mW Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . .+125°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions TA, Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to +105°C VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V to 60V VBAT (Daisy Chain Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V to 60V VCn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . .V(VCn-1) to V(VCn-1) + 5V VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V CBn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V(VCn-1) to V(VCn-1) + 9V CBn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V(VCn) -9V to V(VCn) DIN, SCLK, CS, COMMS SELECT 1, COMMS SELECT 2, V3P3, VCC, COMMS RATE 0, COMMS RATE 1, EN. . . . . . . . . . . . . . . . . . . . . . .0V to 3.6V ExT1, ExT2, ExT3, ExT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 2.5V NOTE: DOUT, DATA READY and FAULT are digital outputs and should not be driven from external sources. V2P5, REF, TEMPREG and BASE are analog outputs and should not be driven from external sources. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the “case temp” location is taken at the package top center. Electrical Specifications Figure 45 on page 26 or equivalent. PARAMETER VBAT = 6 to 60V, TA = -20°C to +85°C, unless otherwise specified. Biasing setup as in SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNIT 5 V MEASUREMENT SPECIFICATIONS Cell Voltage Input Measurement Range VCELL VC(N) - VC(N-1). For design reference. Cell Monitor Voltage Resolution VCELLRES [VC(N)-VC(N-1)] LSB step size (13-bit signed number), 5V full scale value ISL78610 Cell Monitor Voltage Error (Absolute) For Performance Characteristics, see “Performance Characteristics” on page 15 VCELLA Cell Measurement Error (Cell measurement error compared with applied voltage with 1k series resistance in line to cell input) Cell Input Current IVCELL Note: Cell accuracy figures assume a fixed 1kΩ resistor is placed in series with each VCn pin (n = 0 to 12) VBAT Monitor Voltage Resolution Submit Document Feedback VBATRES 8 0 0.61 mV Temperature = +25°C, VCELL = 3.3V -6.5 6.5 mV Temperature = +85°C, VCELL = 3.3V -25.0 25.0 mV VC0 input, VCELL = 0.5V to 4.95V -2.0 -1 -0.5 µA VC1, VC2, VC3 inputs, VCELL = 0.5V to 4.95V -3.0 -2 -0.9 µA VC4 input, VCELL = 0.5V to 4.95V -0.8 0 0.9 µA VC5, VC6, VC7, VC8, VC9, VC10, VC11 inputs, VCELL = 0.5V to 4.95V 0.5 2 3.2 µA VC12 input, VCELL = 0.5V to 4.95V 0.4 1 2.0 µA ADC resolution referred to input (VBAT) level. 14b unsigned number. Full scale value = 79.67V. 4.863 mV FN8830.1 June 16, 2016 ISL78610 Electrical Specifications VBAT = 6 to 60V, TA = -20°C to +85°C, unless otherwise specified. Biasing setup as in Figure 45 on page 26 or equivalent. (Continued) PARAMETER SYMBOL VBAT VBAT Monitor Voltage Error TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNIT Temperature = +25°C, Measured at VBAT = 39.6V -120 120 mV Temperature = +85°C, Measured at VBAT = 39.6V -320 320 mV 2.475 2.525 V External Temperature Monitoring Regulator VTEMP Voltage on TEMPREG output. (0 to 2mA load) External Temperature Output Impedance RTEMP Output Impedance at TEMPREG pin 2.500 0.1 Ω External Temperature Input Range VEXT External Temperature Input Pull-Up REXTTEMP External Temperature Input Offset VEXTOFF External Temperature Input INL VEXTINL ±0.3 VEXTG ±8 Internal Temperature Monitor Error VINTMON ±10 °C Internal Temperature Monitor Resolution TINTRES Output resolution (LSB/°C). 14b number 31.9 LSB/°C Internal Temperature Monitor Output TINT25 Output count at +25°C 9180 Decimal Power-Up Condition Threshold VPOR VBAT voltage (rising) Power-Up Condition Hysteresis VPORhys External Temperature Input Gain Error ExTn input voltage range. For design reference 0 Pull-up resistor to VTEMPREG applied to each input during measurement VBAT = 39.6V 2344 mV 10 -12 MΩ 12 mV mV 18.5 mV Power-Up Specifications 4.8 5.1 5.6 V 400 mV Initial Power-Up Delay tPOR Time after VPOR condition VREF from 0V to 0.95 x VREF(nom) (EN tied to V3P3) Device can now communicate 27.125 ms Enable Pin Power-Up Delay tPUD Delay after EN = 1 to VREF from 0V to 0.95 x VREF(nom) (VBAT = 39.6V) - Device can now communicate 27.125 ms Submit Document Feedback 9 FN8830.1 June 16, 2016 ISL78610 Electrical Specifications VBAT = 6 to 60V, TA = -20°C to +85°C, unless otherwise specified. Biasing setup as in Figure 45 on page 26 or equivalent. (Continued) PARAMETER SYMBOL MIN (Note 8) TEST CONDITIONS TYP MAX (Note 8) UNIT Supply Current Specifications VBAT Supply Current IVBAT Non-daisy chain configuration. Device enabled. No communications, ADC, measurement or open-wire detection activity. 6V 35 µA 39.6V 64 µA 60V IVBATMASTER Daisy chain configuration – master device. Enabled. No communications, ADC, measurement or open-wire detection activity. 10 530 µA 680 µA 550 µA 18 mA µA 39.6V 1250 µA 1000 6V 39.6V 60V 1400 1700 µA 18 mA 530 µA 680 550 Peak current when daisy chain transmitting 750 µA 1000 18 µA mA IVBATSLEEP1 Sleep mode (EN = 1, daisy chain configuration). 20 35 50 µA IVBATSLEEP2 Sleep mode (EN = 1, stand-alone, non-daisy chain) 13 20 50 µA 6 15 54 µA 10.5 µA 3.5 V IVBATSHDN VBAT Supply Current Tracking. Sleep Mode 1000 1020 60V Daisy chain configuration – top device. Enabled. No communications, ADC, measurement or open-wire detection activity. 750 6V Peak current when daisy chain transmitting IVBATTOP µA 6V Peak current when daisy chain transmitting Daisy chain configuration – mid stack device. Enabled. No communications, ADC, measurement or open-wire detection activity. 96 39.6V 60V IVBATMID 73 Shutdown. device “off” (EN = 0) (Daisy chain and non-daisy chain configurations) IVBATΔSLEEP EN = 1, daisy chain Sleep mode configuration. VBAT current difference between any two devices operating at the same temperature and supply voltage. 0 V3P3 Regulator Voltage (Normal) V3P3N EN = 1, Load current range 0 to 5 mA. VBAT = 39.6V V3P3 Regulator Voltage (Sleep) V3P3S EN = 1, Load current range. No load. (SLEEP). VBAT = 39.6V V3P3 Supply Current IV3P3 Device Enabled No measurement activity, normal mode VREF Reference Voltage VREF EN = 1, no load, normal mode 2.5 V Switch “On” resistance, VBAT = 39.6V 12 Ω VDDEXT Switch Resistance RVDDEXT VCC Supply Current IVCC IVCCACTIVE1 Submit Document Feedback 10 Device enabled (EN = 1). Stand-alone or daisy configuration. No ADC or daisy chain communications active. 3.2 3.35 2.7 0.7 2.00 1 3.25 V 1.3 5.00 mA mA Device enabled (EN = 1). Stand-alone or daisy configuration. Average current during 16ms Scan Continuous operation. VBAT = 39.6V 6.0 mA IVCCSLEEP Device enabled (EN = 1). Sleep mode. VBAT = 39.6V 2.4 µA IVCCSHDN Device disabled (EN = 0). Shutdown mode. 0 1.2 9.0 µA FN8830.1 June 16, 2016 ISL78610 Electrical Specifications VBAT = 6 to 60V, TA = -20°C to +85°C, unless otherwise specified. Biasing setup as in Figure 45 on page 26 or equivalent. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNIT Over-Temperature Protection Specifications Internal Temperature Limit Threshold TINTSD Balance stops and auto scan stops. Temperature rising or Falling. 150 °C External Temperature Limit Threshold TXT Corresponding to 0V (minimum) and VTEMPREG (maximum) External temperature input voltages higher than 15/16 VTEMPREG are registered as open input faults. 0 16383 Decimal Undervoltage Threshold VUV Programmable. Corresponding to 0V (minimum) and 5V (maximum) 0 8191 Decimal Overvoltage Threshold VOV Programmable. Corresponding to 0V (minimum) and 5V (maximum) 0 8191 Decimal V3P3 Power-Good Window V3PH 3.3V power-good window high threshold. VBAT = 39.6V 3.90 V V3PL 3.3V power-good window low threshold. VBAT = 39.6V 2.65 V V2PH 2.5V power-good window high threshold. VBAT = 39.6V 2.7 V V2PL 2.5V power-good window low threshold. VBAT = 39.6V 2.0 V VVCCH VCC power-good window high threshold. VBAT = 39.6V 3.75 V VVCCL VCC power-good window low threshold. VBAT = 39.6V 2.7 V VRPH VREF power-good window high threshold. VBAT = 39.6V 2.7 V VRPL VREF power-good window low threshold. VBAT = 39.6V 2.30 V VREF Reference Accuracy Test VRACC VREF value calculated using stored coefficients. VBAT = 39.6V (See “Voltage Reference Check Calculation” on page 79.) 2.500 V Voltage Reference Check Timeout tVREF Time to check voltage reference value from power-on, enable or wake-up 20 ms Oscillator Check Timeout tOSC Time to check main oscillator frequency from power-on, enable or wake-up 20 ms Oscillator Check Filter Time tOSCF Minimum duration of fault required for detection 100 ms Fault Detection System Specifications V2P5 Power-Good Window VCC Power-Good Window VREF Power-Good Window Fast Oscillator Oscillator frequency 3.4 4 4.6 MHz Slow Oscillator Oscillator frequency 27.2 32 36.8 kHz ISCN bit = 0; VBAT = 39.6V 0.125 0.150 0.185 mA ISCN bit = 1; VBAT = 39.6V 0.85 1.00 1.15 mA Cell Open-Wire Detection (See “Scan Wires Command” on page 41, and “Open-wire Test” on page 73.) Open-Wire Current IOW Open-Wire Detection Time tOW Open-wire current source “on” time Open VC0 Detection Threshold VVC0 CELL1 negative terminal (with respect to VSS) VBAT = 39.6V (Note 9) Submit Document Feedback 11 4.6 1.2 1.5 ms 1.8 V FN8830.1 June 16, 2016 ISL78610 Electrical Specifications VBAT = 6 to 60V, TA = -20°C to +85°C, unless otherwise specified. Biasing setup as in Figure 45 on page 26 or equivalent. (Continued) PARAMETER MIN (Note 8) TYP MAX (Note 8) UNIT CELL1 positive terminal (with respect to VSS) VBAT = 39.6V (Note 9) 0.6 0.7 0.8 V -2 -1.5 0 V -100 -30 50 mV SYMBOL Open VC1 Detection Threshold VVC1 TEST CONDITIONS Primary Detection Threshold, VC2 to VC12 VVC2_12P V(VC(n - 1))-V(VCn), n = 2 to 12 VBAT = 39.6V (Note 9) Secondary Detection Threshold, VC2 to VC12 VVC2_12S Via ADC. VC2 to VC12 only VBAT = 39.6V (Note 9) Open VBAT Fault Detection Threshold VVBO VC12 - VBAT 200 mV Open VSS Fault Detection Threshold VVSSO VSS - VC0 250 mV Cell Balance Pin Output Impedance RCBL CBn output off impedance between CB(n) to VC(n-1): cells 1 to 9 and between CB(n) to VC(n): cells 10 to 12 2 4 5 MΩ Cell Balance Output Current ICBH1 CBn output on. (CB1-CB9); VBAT = 39.6V; device sinking current -28 -25 -21 μA ICBH2 CBn output on. (CB10-CB12); VBAT = 39.6V; device sourcing current 21 25 28 μA ICBSD EN = GND. VBAT = 39.6V -500 10 700 nA CBn Output on; External 320kΩ between VCn and CBn (n = 10 to 12) and between CBn and VCn-1 (n = 1 to 9) 7.04 8.00 8.96 V ICB = 100µA 8.94 Cell Balance Output Specifications Cell Balance Output Leakage in Shutdown External Cell Balance FET Gate Voltage Internal Cell Balance Output Clamp VGS VCBCL V Logic Inputs: SCLK, CS, DIN Low Level Input Voltage VIL High Level Input Voltage VIH Input Hysteresis 0.8 1.75 VHYS Input Current IIN Input Capacitance (Note 9) CIN V V 250 0V < VIN < V3P3 -1 mV +1 µA 10 pF 0.3*V3P3 V Logic Inputs: EN, COMMS SELECT1, COMMS SELECT2, COMMS RATE 0, COMMS RATE 1 Low Level Input Voltage VIL High Level Input Voltage VIH Input Hysteresis VHYS Input Current IIN Input Capacitance (Note 9) CIN (Note 9) 0V < VIN < V3P3 0.7*V3P3 V 0.05*V3P3 V -1 +1 µA 10 pF Logic Outputs: DOUT, FAULT, DATA READY Low Level Output Voltage High Level Output Voltage SPI Interface Timing VOL1 At 3mA sink current 0 0.4 V VOL2 At 6mA sink current 0 0.6 V VOH1 At 3mA source current V3P3 – 0.4 V3P3 V VOH2 At 6mA source current V3P3 – 0.6 V3P3 V 2 MHz 200 ns See Figures 3 and 4 SCLK Clock Frequency fSCLK Pulse Width of Input Spikes Suppressed Submit Document Feedback 12 tIN1 50 FN8830.1 June 16, 2016 ISL78610 Electrical Specifications VBAT = 6 to 60V, TA = -20°C to +85°C, unless otherwise specified. Biasing setup as in Figure 45 on page 26 or equivalent. (Continued) PARAMETER SYMBOL TEST CONDITIONS Chip select low to ready to receive clock data MIN (Note 8) TYP MAX (Note 8) UNIT Enable Lead Time tLEAD 200 ns Clock High Time tHIGH 200 ns Clock Low Time tLOW 200 ns Enable Lag Time tLAG 250 ns Last data read clock edge to Chip Select high Slave Access Time tA Chip Select low to DOUT active 200 ns Data Valid Time tV Clock low to DOUT valid 350 ns Data Output Hold Time tHO Data hold time after falling edge of SCLK 0 ns DOUT Disable Time tDIS DOUT disabled following rising edge of CS Data Setup Time tSU Data input valid prior to rising edge of SCLK 100 ns Data Input Hold Time tHI Data input to remain valid following rising edge of SCLK 80 ns 240 ns Data Ready Start Delay Time tDR:ST Minimum chip select high to Data Ready low 100 ns Data Ready Stop Delay Time tDR:SP Maximum chip select high to Data Ready high 750 ns Data Ready High Time tDR:WAIT Minimum time between bytes 1.0 µs Chip Select High Time tCS:WAIT Minimum high time for CS between bytes 200 ns Maximum time the CS remains high before SPI communications time out - requiring the start of a new command 100 µs SPI Communications Timeout tSPI:TO DOUT Rise Time tR Up to 50pF load 30 ns DOUT Fall Time tF Up to 50pF load 30 ns Daisy Chain Communications Interface: DHi1, DLo1, DHi2, DLo2 Daisy Chain Clock Frequency Comms Rate (0, 1) = 11 450 500 550 kHz Comms Rate (0, 1) = 10 225 250 275 kHz Comms Rate (0, 1) = 01 112.5 125 137.5 kHz Comms Rate (0, 1) = 00 56.25 62.5 68.75 kHz Common-Mode Reference Voltage VBAT/2 V NOTES: 8. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. Limits are 100% tested, unless declared otherwise. 9. These MIN and/or MAX values are based on characterization data and are not 100% tested. 10. Stresses may be induced in the ISL78610 during soldering or other high temperature events that affect measurement accuracy. Initial accuracy does not include effects due to this. See Figure 8 for cell reading accuracy obtained after soldering to Intersil evaluation boards. When soldering the ISL78610 to a customized circuit board with a layout or construction significantly differing from the Intersil evaluation board, design verification tests should be applied to determine drift due to soldering and over lifetime. Submit Document Feedback 13 FN8830.1 June 16, 2016 ISL78610 Timing Diagrams CS (FROM µC) tSPI:TO tLEAD tHIGH tLOW tCS:WAIT tLAG SCLK (FROM µC) tA tF tV tDIS tHO DOUT (TO µC) tSU tR tHI DIN (FROM µC) CLOCK DATA INTO ISL78610 CLOCK DATA OUT OF ISL78610 FIGURE 3. SPI FULL DUPLEX (4-WIRE) INTERFACE TIMING tCS:WAIT tSPI:TO CS (FROM µC) tDR:WAIT tDR:SP DATA READY (TO µC) SCLK (FROM µC) tA tDIS DOUT (TO µC) CLOCK DATA OUT OF ISL78610 SIGNALS ON DIN IGNORED WHILE DATA READY IS LOW DIN (FROM µC) CLOCK DATA INTO ISL78610 FIGURE 4. SPI HALF DUPLEX (3-WIRE) INTERFACE TIMING Submit Document Feedback 14 FN8830.1 June 16, 2016 ISL78610 Performance Characteristics Cell/VBAT Reading Error - 3 Sigma PARAMETER SYMBOL ISL78610 Initial Cell Reading Error (Absolute) VCELLA ISL78610 Initial VBAT Reading Error (Absolute) VBAT TEST CONDITIONS -3 SIGMA (Note 11) TYP +3 SIGMA (Note 11) UNIT Temperature = +25°C VCELL = 3.3V Limits applied to a ±3 sigma distribution -3.2 3.2 mV Temperature = -20°C to +60°C VCELL = 2.6V to 4.0V Limits applied to a ±3 sigma distribution -10 10 mV Temperature = -40°C to -20°C VCELL = 2.6V to 4.0V Limits applied to a ±3 sigma distribution -15 15 mV Temperature = +60°C to +85°C VCELL = 2.6V to 4.0V Limits applied to a ±3 sigma distribution -15 15 mV Temperature = -20°C to +60°C VBAT = 31.2V to 48V Limits applied to a ±3 sigma distribution -175 175 mV Temperature = -40°C to +105°C VBAT = 31.2V to 48V Limits applied to a ±3 sigma distribution -300 300 mV Voltage Reference Long Term Drift -0.31 mV/ log (days) Cell/VBAT Reading Error - 5 Sigma PARAMETER SYMBOL ISL78610 Initial Cell Monitor Voltage Error (Absolute) VCELLA ISL78610 Initial VBAT Reading Error (Absolute) VBAT TEST CONDITIONS -5 SIGMA (Note 11) TYP +5 SIGMA (Note 11) UNIT Temperature = +25°C VCELL = 3.3V Limits applied to a ±5 sigma distribution -5 5 mV Temperature = -20°C to +60°C VCELL = 2.6V to 4.0V Limits applied to a ±5 sigma distribution -12 12 mV Temperature = -40°C to -20°C VCELL = 2.6V to 4.0V Limits applied to a ±5 sigma distribution -20 20 mV Temperature = +60°C to +85°C VCELL = 2.6V to 4.0V Limits applied to a ±5 sigma distribution -25 25 mV Temperature = +85°C to +105°C VCELL = 2.6V to 4.0V Limits applied to a ±5 sigma distribution -45 45 mV Temperature = -20°C to +60°C VBAT = 31.2V to 48V Limits applied to a ±5 sigma distribution -250 250 mV Temperature = -40°C to +105°C VBAT = 31.2V to 48V Limits applied to a ±5 sigma distribution -425 425 mV NOTE: 11. These distribution values are based on characterization of devices mounted on evaluation boards and are not 100% tested. Submit Document Feedback 15 FN8830.1 June 16, 2016 ISL78610 These performance curves are based on characterization of devices mounted on evaluation boards. 20 50 15 40 30 READING ERROR (mV) READING ERROR (mV) Performance Curves 10 5 0 -5 -10 20 10 0 -10 -20 -30 -15 -40 -50 -20 0.5 2.6 3 3.3 3.6 4 4.5 -40 -20 0 20 80 100 120 FIGURE 6. CELL VOLTAGE READING ERROR 3.0V TO 3.6V PER CELL 40.0 35 PERCENTAGE OF CELLS (%) PERCENTAGE OF CELLS (%) 60 TEMPERATURE ( C) FIGURE 5. CELL VOLTAGE READING ERROR FROM -20°C TO +60°C 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 30 25 20 15 10 5 0 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 -4 -3 -2 -1 READING ERROR (mV) 200 150 102 105 108 103 106 109 READING ERROR (mV) 101 104 107 110 100 50 0 -50 -100 -150 0 5 10 15 20 25 30 35 40 45 50 55 60 PACK VOLTAGE (V) FIGURE 9. PACK VOLTAGE READING ERROR AT +25°C (MULTIPLE BOARDS) Submit Document Feedback 16 1 2 3 4 5 6 7 8 9 10 FIGURE 8. CELL READING ERROR FROM EVALUATION BOARDS AT CELL VOLTAGE FROM 2.6V TO 4.0V, AND -20°C TO +60°C HISTOGRAM 300 250 0 READING ERROR (mV) FIGURE 7. INITIAL CELL VOLTAGE ACCURACY FROM EVALUATION BOARDS AT 3.3V, +25°C HISTOGRAM READING ERROR (mV) 40 o CELL VOLTAGE (V) 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 6V 36V 43.2V 54V -40 10 60 31.2V 39.6V 48V 110 160 TEMPERATURE (oC) FIGURE 10. AVERAGE PACK VOLTAGE READING ERROR AT 6V to 54V PACK VOLTAGE FN8830.1 June 16, 2016 ISL78610 Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued) 30.0 5.00 4.00 READING ERROR (°C) PERCENTAGE (%) 25.0 20.0 15.0 10.0 5.0 3.00 2.00 1.00 0.00 -1.00 -2.00 6V 36V 43.2V 54V -3.00 -4.00 0.0 -5.00 -140 -100 -60 -20 20 60 100 140 180 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 o TEMPERATURE ( C) READING ERROR (mV) FIGURE 11. INITIAL PACK VOLTAGE ACCURACY 31.2V TO 48V, -20°C TO +60°C HISTOGRAM FIGURE 12. IC TEMPERATURE READING ERROR vs TEMPERATURE 6V 36V 43.2V 54V 4.00 3.00 2.00 CELL MEASUREMENT ERROR (mV) 2ND REFERENCE ERROR (mV) 5.00 31.2V 39.6V 48V 1.00 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 0.001 0.01 0.1 YEARS TEMPERATURE (oC) FIGURE 13. VOLTAGE REFERENCE CHECK VOLTAGE ERROR OVER VBAT = 6V TO 54V AND TEMPERATURE 1.0 10.0 FIGURE 14. LONG TERM DRIFT 25.60 25.6 BALANCE CURRENT (µA) BALANCE CURRENT (µA) 31.2V 39.6V 48V 25.55 25.50 25.45 25.4 VCELL = 3.3V 25.2 25.0 24.8 24.6 24.4 25.40 0 10 20 30 40 PACK VOLTAGE (V) 50 FIGURE 15. BALANCE CURRENT vs PACK VOLTAGE Submit Document Feedback 17 60 24.2 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 FIGURE 16. BALANCE CURRENT vs TEMPERATURE FN8830.1 June 16, 2016 ISL78610 Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued) 1000 975 980 VCELL = 3.3V TEMPERATURE = +25°C 960 970 IOPWI (µA) 940 IOPWI (µA) 965 960 920 900 880 860 840 955 820 800 950 -40 -20 0 20 40 60 80 100 120 0 10 20 TEMPERATURE ( oC ) FIGURE 17. OPEN-WIRE TEST CURRENT vs TEMPERATURE (1mA SETTING) 50 60 158.6 159 158.4 VCELL = 3.3V 158 TEMPERATURE = +25°C 158.2 157 IOPWI (µA) IOPWI (µA) 40 FIGURE 18. OPEN-WIRE TEST CURRENT vs PACK VOLTAGE (1mA SETTING) 160 156 155 158 157.8 157.6 154 157.4 153 157.2 152 157 -40 -20 0 20 40 60 80 100 0 120 10 20 o FIGURE 19. OPEN-WIRE TEST CURRENT vs TEMPERATURE (150µA SETTING) 4.05 30 40 50 60 PACK VOLTAGE (V) TEMPERATURE ( C ) FIGURE 20. OPEN-WIRE TEST CURRENT vs PACK VOLTAGE (150µA SETTING) 4.045 VBAT = 39.6V 4.040 FREQUENCY (MHz) 4.00 FREQUENCY (MHz) 30 PACK VOLTAGE (V) 3.95 3.90 3.85 3.80 VBAT = 39.6V 4.035 4.030 4.025 4.020 4.015 4.010 3.75 4.005 3.70 4.000 -40 -20 0 20 40 60 80 100 120 TEMPERATURE ( oC ) FIGURE 21. 4MHz OSCILLATOR FREQUENCY vs TEMPERATURE Submit Document Feedback 18 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 VCC (V) FIGURE 22. 4MHz OSCILLATOR FREQUENCY vs VCC FN8830.1 June 16, 2016 ISL78610 Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued) 31.60 31.35 31.40 FREQUENCY (kHz) FREQUENCY (kHz) 31.30 VBAT = 39.6V 31.20 31.00 30.80 30.60 30.40 30.20 VBAT = 39.6V 31.25 31.20 31.15 31.10 31.05 30.00 31.00 29.80 -40 -20 0 20 40 60 80 100 2.5 120 2.7 2.9 3.1 TEMPERATURE ( oC ) FIGURE 23. 32kHz OSCILLATOR FREQUENCY vs TEMPERATURE 3.7 3.9 80 50 70 VBAT = 60V 30 VBAT = 39.6V 20 VBAT = 60V 60 40 IVBAT (µA) IVBAT (µA) 3.5 FIGURE 24. 32kHz OSCILLATOR FREQUENCY vs VCC 60 VBAT = 6V 50 VBAT = 39.6V 40 30 20 10 VBAT = 6V 10 0 0 -40 -20 0 20 40 60 80 100 -40 120 -20 0 80 70 70 80 100 120 60 VBAT = 60V IVBAT (µA) 50 VBAT = 39.6V 30 VBAT = 6V 20 60 FIGURE 26. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (DAISY CHAIN MASTER) 80 40 40 TEMPERATURE ( C ) FIGURE 25. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (STAND-ALONE MODE) 60 20 o o TEMPERATURE ( C ) IVBAT (µA) 3.3 VCC (V) 50 VBAT = 39.6V VBAT = 60V 40 VBAT = 6V 30 20 10 10 0 0 -40 -20 0 20 40 60 80 100 120 o TEMPERATURE ( C ) FIGURE 27. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (DAISY CHAIN MIDDLE) Submit Document Feedback 19 -40 -20 0 20 40 60 80 100 120 o TEMPERATURE ( C ) FIGURE 28. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (DAISY CHAIN TOP) FN8830.1 June 16, 2016 ISL78610 Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued) 750 100 VBAT = 60V 95 700 90 650 80 IVBAT (µA) IVBAT (µA) 85 VBAT = 60V 75 70 65 VBAT = 39.6V 600 550 VBAT = 6V 60 VBAT = 39.6V 55 50 -40 -20 0 20 VBAT = 6V 500 40 60 80 100 450 120 -40 -20 0 o FIGURE 29. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (STAND-ALONE MODE) 750 VBAT = 60V 60 80 100 120 VBAT = 60V 700 1250 1150 IVBAT (µA) IVBAT (µA) 40 FIGURE 30. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (DAISY CHAIN MASTER) 1450 1350 20 TEMPERATURE (oC ) TEMPERATURE ( C ) VBAT = 39.6V 1050 VBAT = 6V 950 650 VBAT = 39.6V 600 550 VBAT = 6V 500 450 850 -40 -20 0 20 40 60 80 100 -40 120 -20 0 20 40 60 80 100 120 o TEMPERATURE (oC ) TEMPERATURE ( C ) FIGURE 31. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (DAISY CHAIN MIDDLE) FIGURE 32. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V (DAISY CHAIN TOP) 3.45 60 3.40 3.35 3.25 40 30 VBAT = 60V IVCC (mA) IVBAT (µA) 50 VBAT = 39.6V 20 3.20 3.15 3.10 3.05 3.00 10 2.95 VBAT = 6V 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC ) FIGURE 33. PACK VOLTAGE SHUTDOWN CURRENT vs TEMPERATURE (EN = 0) AT 6V, 39.6V, 60V Submit Document Feedback 20 2.90 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 34. VCC SUPPLY CURRENT vs TEMPERATURE AT 6V, 39.6V, 60V FN8830.1 June 16, 2016 ISL78610 Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued) 2.5 1.06 CELL INPUT CURRENT (µA) SUPPLY CURRENT (mA) 1.04 39.6V 1.03 60V 1.02 6V 1.01 1.00 0.99 -40 VCELL = 3.3V 2.0 1.05 -20 0 20 40 60 80 100 VC11 1.5 VC5 VC10 1.0 VC7 VC9 VC6 VC12 0.5 0 VC4 -0.5 -1.0 VC0 -1.5 -2.0 -2.5 -40 VC3 -20 VC2 0 VC1 20 40 60 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 35. V3P3 SUPPLY CURRENT vs TEMPERATURE VC8 80 100 120 FIGURE 36. CELL INPUT CURRENT vs TEMPERATURE CELL INPUT CURRENT (µA) 2.5 2.0 VC11 VC10 VC9 1.5 VC8 VC7 1.0 VC6 VC5 0.5 VC12 VC4 0.0 -0.5 VC0 -1.0 -1.5 VC3 -2.0 VC2 VC1 -2.5 0 10 20 30 40 PACK VOLTAGE (V) 50 60 FIGURE 37. CELL INPUT CURRENT vs PACK VOLTAGE (+25°C) Submit Document Feedback 21 FN8830.1 June 16, 2016 ISL78610 Device Description and Operation The ISL78610 is a Li-ion battery manager IC that supervises up to 12 series connected cells. Up to 14 ISL78610 devices can be connected in series to support systems with up to 168 cells. The ISL78610 provides accurate monitoring, cell balance control and diagnostic functions. The ISL78610 includes a voltage reference, 14-bit A/D converter and registers for control and data. When multiple ISL78610 devices are connected to a series of cells, their power supply domains are normally non-overlapping. The lower (VSS) supply of each ISL78610 nominally connects to the same potential as the upper (VBAT) supply of the ISL78610 device below. Within each device, the cell voltage monitoring system comprises two basic elements; a level shift to eliminate the cell common-mode voltage and an analog-to-digital conversion of the cell voltage. Each ISL78610 is calibrated at a specific cell input voltage value, VNOM. Cell voltage measurement error data is given in “MEASUREMENT SPECIFICATIONS” on page 8 for various voltage and temperature ranges with voltage ranges defined with respect to VNOM. Plots showing the typical error distribution over the full input range are included in the “Performance Curves” section beginning on page 16. To collect cell voltage and temperature measurements, the ISL78610 provides two multiple parameter measurement “scanning” modes in addition to single parameter direct measurement capability. The scanning modes provide pseudo simultaneous measurement of all cell voltages in the stack. The ISL78610 does not measure current. The system performs this separately using other measurement systems. The only filtering applied to the ADC measurements is that resulting from external protection circuits and the limited bandwidth of the measurement path. No additional filtering is performed within the part. This arrangement is typically needed to maintain timing integrity between the cell voltage and pack current measurements. However, the ISL78610 does apply filtering to the fault detection systems. Cell balancing is an important function in a battery pack consisting of a stack of multiple Li-ion cells. As the cells charge and discharge, differences in each cell’s ability to take on, and give up charge, typically leads to cells with different states of charge. The problem with a stack of cells having different states of charge is that Li-ion cells have a maximum voltage, above which it should not be charged, and a minimum voltage, below which it should not be discharged. The extreme case, where one cell in the stack is at the maximum voltage and one cell is at the minimum voltage, results in a nonfunctional battery stack, since the battery stack cannot be charged or discharged. The ISL78610 provides multiple cell balance modes, Manual Balance mode, Timed Balance mode, and Auto Balance mode. These are described in more detail in “Alarm Response” on page 75. Submit Document Feedback 22 The ISL78610 incorporates extensive fault diagnostics functions which include cell overvoltage and undervoltage, regulator and oscillator operation, open cell input detection and communication faults. The current status of most faults is accessible using the ISL78610 registers. Some communication faults are reported by special responses to system commands and some as “unprompted” responses from the device detecting the fault to the host microcontroller through the daisy chain. To conserve power, the ISL78610 has three main power modes: Normal mode, Sleep mode and “off” (Shutdown mode). Sleep mode is entered in response to a Sleep command or after a watchdog timeout (see “Watchdog Function” on page 75.) Only the communications input circuits, low speed oscillator and internal registers are active in Sleep mode, allowing the part to perform timed scan and balancing activity and to wake up in response to communications. With the Enable pin low the device is in Shutdown mode. In this mode, the internal bias for most of the IC is powered down except digital core, Sleep mode regulators and digital input buffers. When exiting, the device powers up and does not reload the factory programmed configuration data from EEPROM. The Normal mode consists of an Active state and a Standby state. In the Standby state, all systems are powered and the device is ready and waiting to perform an operation in response to commands from the host microcontroller. In the Active state, the device is performing an operation, such as ADC conversion, open-wire detection, etc. System Hardware Connection Battery and Cell Balance Connection The first consideration in designing a battery system around the ISL78610 is the connection of the cells to the IC. The battery connection elements are split between the cell monitor connections (VCn) and the cell balance connections (CBn). BATTERY CONNECTION All inputs to the ISL78610 VCn pins are protected against battery voltage transients by external RC filters. The basic input filter structure, with capacitors to the local ground, provides protection against transients and EMI for the cell inputs. They carry the loop currents produced by EMI and should be placed as close to the battery connector as possible. The ground terminals of the capacitors must be connected directly to a solid ground plane. Do not use vias to connect these capacitors to the input signal path or to ground. Any vias should be placed in line to the signal inputs so that the inductance of these forms a low pass filter with the grounded capacitors. The resistors on the input filter provide a current limit function during hot plug events. The ISL78610 is calibrated for use with 1kΩ series protection resistors at the VCn inputs. The VBAT connection uses a lower value input resistor to accommodate the supply current of the ISL78610. As much as possible, the time constant produced by the filtering applied to VBAT should be matched to that applied to the VCn monitoring inputs. See Figure 38. FN8830.1 June 16, 2016 ISL78610 LOCATE CLOSE TO INPUT CONNECTOR 27 B14b VBAT C1 *EXAMPLE DIODE: PTVS58VS1UTR 58V* VSS 180 820 B12 ISL78610 VC12 22nF B11 180 820 this. First, the power supply current for the devices might affect the accuracy of the cell voltage readings. Second, if the single wire breaks, it is very difficult for the system to tell specifically what happened through normal diagnostic methods. An alternative circuit in Figure 40 shows the connection of one (or two) wires with additional Schottky diodes to provide supply current paths to allow the device to detect that there is a connection fault and to minimize the effects on cell voltage measurements when there is an open connection to the battery. VC11 22nF B10 B9 180 820 VC10 180 VC9 22nF B2 B0b 100 ISL78610 27 180 820 VC2 180 820 VC1 820 180 22nF VC0 VSS2 VC3 22nF B0 VSS2 22nF 22nF B1 VC1 820 180 100 22nF BOARD CONNECTIONS B3 VSS2 820 22nF 820 ISL78610 VC2 22nF 22nF 820 100 820 VBAT C1 VSS 820 100 VSS 100 VC11 22nF VSS VC12 22nF 820 VC0 VSS VSS = “QUIET” GROUND = “NOISY” GROUND FIGURE 39. BATTERY CONNECTION BETWEEN STACKED DEVICES (OPTION 1) CELL BALANCE CIRCUITS NOT SHOWN IN THIS FIGURE FIGURE 38. TYPICAL INPUT FILTER CIRCUITS ISL78610 The filtered battery voltage connects to the internal cell voltage monitoring system. The monitoring system comprises three basic elements; a level shifter to eliminate the cell common-mode voltage, a multiplexer to select a specific input and an analog-to-digital conversion of the cell voltage. 820 Each ISL78610 is calibrated at a specific cell input voltage value, VNOM with an expected input series resistance of 1kΩ. Cell voltage measurement error data is given in “MEASUREMENT SPECIFICATIONS” on page 8 for various voltage and temperature ranges with voltage ranges defined with respect to VNOM. Plots showing the typical error distribution over the full input range are included in the “Performance Curves” section beginning on page 16. 820 Submit Document Feedback 23 VC2 22nF 820 VSS2 180 VC1 22nF VSS2 180 VC0 22nF VSS2 ISL78714 ISL78610 VBAT 27 BOARD CONNECTIONS Another important consideration is the connection of cells in a stacked (non-overlapping) configuration. Mainly, this involves how to connect the supply and ground pins at the junction of two devices. The diagram in Figure 39 shows the recommended minimum connection to the pack. It is preferred that there be four connection wires at the intersection of two devices, but this does pose a cost constraint. To minimize the connections, the power and monitor pins are connected separately, as shown in Figure 39. It is not recommended that all four wires connect together with a single wire to the pack. There are two reasons for 180 C1 VSS 820 VSS 180 VC12 22nF 820 VSS 180 VC11 22nF VSS FIGURE 40. BATTERY CONNECTION BETWEEN STACKED DEVICES (OPTION 2) FN8830.1 June 16, 2016 ISL78610 CELL BALANCE CONNECTION The ISL78610 uses external MOSFETs for the cell balancing function. The gate drive for these is derived from on-chip current sources on the ISL78610 which are 25µA nominally. The current sources are turned on and off as needed to control the external MOSFET devices. The current sources are turned off when the device is in Shutdown mode or Sleep mode. The ISL78610 uses a mix of N-channel and P-channel MOSFETs for the external balancing function. The top three cell locations, cells 10, 11, 12 are configured to use P-channel MOSFETs while the remaining cell locations, cells 1 through 9, use N-channel MOSFETs. The mix of N-channel and P-channel devices are used for the external FETs in order to remove the need for a charge pump, while providing a balance FET gate voltage that is sufficient to drive the FET on, regardless of the cell voltages. Figures 41 and 43 shows the circuit detail for the recommended balancing and cell voltage monitoring system. In this configuration, the cell voltage is monitored after the cell balance resistor. This allows the system to monitor the operation of the ISL78610 FIGURE 41. CELL MONITOR AND BALANCE CIRCUIT ARRANGEMENT (VC12) Submit Document Feedback 24 Figure 41 shows the connection for VC12. This connection uses P-channel FETs and is similar for VC11 and VC10. Similarly, Figure 43 shows the connection for VC1, using an N-channel FET, with the connections for VC2 through VC9 being similar. See Figure 51 on page 31 for a more complete example. An alternative balancing and cell voltage monitoring arrangement is shown in Figure 42 and Figure 44. The diagram in Figure 42 shows the connection for VC10 through VC12, using P-channel FETs. Figure 44 shows the connection for VC1 through VC9. using N-channel FETs. With this alternative circuit it is possible to monitor the cell voltages during cell balancing (even though the voltage will likely drop a little when measuring a cell that is being balanced). But this circuit connection does not allow the system to check for all potential external component failures. See Figure 54 on page 34 for a more complete example. ISL78610 FIGURE 42. ALTERNATE CELL MONITOR AND BALANCE CIRCUIT ARRANGEMENT (VC10 TO VC12) ISL78610 FIGURE 43. CELL MONITOR AND BALANCE CIRCUIT ARRANGEMENT (VC1) external balance circuits and is part of the fault detection system. However, this connection prevents monitoring the cell voltage while cell balance is enabled for that cell. ISL78610 FIGURE 44. ALTERNATE CELL MONITOR AND BALANCE CIRCUIT ARRANGEMENT (VC1 TO VC9) FN8830.1 June 16, 2016 ISL78610 The gate of the N-channel MOSFET (cell locations 1 through 9) and P-channel MOSFETs (cells 10 through 12) are normally protected against excessive voltages during cell voltage transients by the action of the parasitic Cgs and Cgd capacitances. These momentarily turn on the FET in the event of a large transient, thus limiting the Vgs values to reasonable levels. A 10nF capacitor is included between the MOSFET gate and source terminals to protect against EMI effects. This capacitor provides a low impedance path to ground at high frequencies and prevents the MOSFET turning on in response to high frequency interference. TABLE 2. CELL READINGS DURING BALANCING CELL BALANCED CELL WITH LOW READING CELL WITH HIGH READING 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 The 10k and 330k resistors are chosen to prevent the 9V clamp at the output from the ISL78610 from activating. 7 7 8 8 8 9 Reduced cell counts for fewer than 12 cells are accommodated by removing connections to the cells in the middle of the stack first. The top and bottom cell locations are always occupied. See “Operating with Reduced Cell Counts” on page 30 for suggested cell configurations when using fewer than 12 cells. 9 9* 10* CELL VOLTAGE MEASUREMENTS DURING BALANCING The standard cell balancing circuit (Figures 41 and 43 on page 24 and Figure 51 on page 31) is configured so the cell measurement is taken from the drain connection of the balancing MOSFET. When balancing is enabled for a cell, the resulting cell measurement is then the voltage across the balancing MOSFET (VGS voltage). This system provides a diagnostic function for the cell balancing circuit. The input voltage of the cell adjacent to the MOSFET drain connection is also affected by this mechanism: the input voltage for this cell increases by the same amount that the voltage of the balance cell decreases. For example, if cells 2 and 3 are both at 3.6V, and balancing is enabled for cell 2. The voltage across the balancing MOSFET may be only 50mV. In this case, the input voltage on the VC2 pin would be VC1 + 50mV and cell 3 would be VC2 + 7.15V. The VC3 value in this case is outside the measurement range of the cell input. VC3 would then read full scale voltage, which is 4.9994V. This full scale voltage reading will occur if the sum of the voltages on the two adjacent cells is greater than the total of 5V plus the “balancing on” voltage of the balanced cell. Table 2 shows the cell affected when each cell is balanced. The cell voltage measurement is affected by impedances in the cell connectors and any associated wiring. The balance current passes through the connections at the top and bottom of the balanced cell. This effect further reduces the voltage measured on the balanced cell and also increases the voltage measured on cells above and below the balanced cell. For example, if cell 4 is balanced with 100mA, and the total impedance of the connector and wiring for each cell connection is 0.1Ω, then cell 4 would read low by an additional 20mV (10mV due to each pin) while cells 3 and 5 would both read high by 10mV. Submit Document Feedback 25 10 10* 9* 11 11 10 12 12 11 NOTE: *Cells 9 and 10 produce a different result from the other cells. Cell 9 uses an N-channel MOSFET while cell 10 uses a P-channel MOSFET. The circuit arrangement used with these devices produces approximately half the normal cell voltage when balancing is enabled. The adjacent cell then sees an increase of half the voltage of the balanced cell. Power Supplies and Reference VOLTAGE REGULATORS The two VBAT pins, along with V3P3, VCC and VDDEXT are used to supply power to the ISL78610. Power for the high voltage circuits and Sleep mode internal regulators is provided via the VBAT pins. V3P3 is used to supply the logic circuits and VCC is similarly used to supply the low voltage analog circuits. The V3P3 and VCC pins must not be connected to external circuits other than those associated with the ISL78610 main voltage regulator. The VDDEXT pin is provided for use with external circuits. The ISL78610 main low voltage regulator uses an external NPN pass transistor to supply 3.3V power for the V3P3 and VCC pins. This regulator is enabled whenever the ISL78610 is in Normal mode and may also be used to power external circuits via the VDDEXT pin. An internal switch connects the VDDEXT pin to the V3P3 pin. Both the main regulator and the switch are off when the part is placed in Sleep mode or Shutdown mode (EN pin LOW.) The pass transistor’s base is connected to the ISL78610 BASE pin. A suitable configuration for the external components associated with the V3P3, VCC and VDDEXT pins is shown in Figure 45. The external pass transistor is required. Do not allow the BASE pin to float. VOLTAGE REFERENCE A bypass capacitor is required between REF (pin 33) and the analog ground VSS. The total value of this capacitor should be in the range of 2.0µF to 2.5µF. Use X7R type dielectric capacitors for this function. The ISL78610 continuously performs a power-good check on the REF pin voltage starting 20ms after a power-up, Enable or Wake-up condition. If the REF capacitor is too large, then the reference voltage may not reach its target voltage range before the power-good check starts and result in a REF fault. If the capacitor is too small, then it may lead to inaccurate voltage readings. FN8830.1 June 16, 2016 ISL78610 R1 VBAT PACK VOLTAGE ISL78610 R3 C7 Q1 BASE C1 COMPONENT VALUE R1 Note 12 R2 33Ω V3P3 D1 R2 V2P5 C3 C5 VCC Note 13 1μF C6 2.2μF VREF C6 VSS C4 27Ω C1 C2, C3, C4, C5 C2 VDDEXT R3 C7 220nF/100V D1 PTVS54VS1UTR Q1 Note 14 TO EXTERNAL CIRCUITS NOTES: 12. R1 should be sized to pass the maximum supply current at the minimum specified battery pack voltage. 13. C1 should be selected to produce a time constant with R1 of a few milliseconds. C1 and R1 provide transient protection for the collector of Q1. Component values and voltage ratings should be obtained through simulation of measurement of the worst case transient expected on VBAT. 14. Q1 should be selected for power dissipation at the maximum specified battery voltage and load current. The load current includes the V3P3 and VCC currents for the ISL78610 and the maximum current drawn by external circuits supplied via VDDEXT. The voltage rating should be determined as described in Note 13. FIGURE 45. ISL78610 REGULATOR AND EXTERNAL CIRCUIT SUPPLY ARRANGEMENT Communications Circuits The ISL78610 operates as a stand-alone monitor for up to 12 series connected cells or in a daisy chain configuration for multiple series connected ISL78610 monitoring devices. For stand-alone (non-daisy chain) systems, only a synchronous SPI is needed for communications between a host microcontroller and the ISL78610. In systems where there is more than one ISL78610, both the SPI port and daisy chain ports are needed for communication. A daisy chain consists of a bottom device, a top device and up to 12 middle devices. The ISL78610 device located at the bottom of the stack is called the master and communicates to the host microcontroller using SPI communications and to other ISL78610 devices using the daisy chain port. Each middle device provides two daisy chain ports: one is connected to the ISL78610 above in the stack and the other to the ISL78610 below. Communications between the SPI and daisy chain interfaces are buffered by the master device to accommodate timing differences between the two systems. The communications setup is controlled by the COMMS SELECT 1 and COMMS SELECT 2 pins on each device. These pins specify whether the ISL78610 is a stand-alone device, the daisy chain master, the daisy chain top, or a middle position in the daisy chain. See Figures 46 and 47 and Table 3. This configuration also specifies the use of SPI or daisy chain on the communication ports. TABLE 3. COMMUNICATIONS MODE CONTROL COMMS COMMS SELECT 1 SELECT 2 PORT 1 COMM PORT 2 COMM COMMUNICATIONS CONFIGURATION 0 0 SPI Disabled (Full Duplex) Stand-alone 0 1 SPI Enabled (Half Duplex) Daisy chain, master device setting 1 0 Daisy Chain Disabled Daisy chain, top device setting 1 1 Daisy Chain Enabled Daisy chain middle device setting The daisy chain ports are fully differential, DC balanced, bidirectional and AC coupled to provide maximum immunity to EMI and other system transients while requiring only two wires for each port. The addressed device, the top device and the bottom device act as master devices for controlling command and response communications. All other devices are repeaters, passing data up or down the chain. Submit Document Feedback 26 FN8830.1 June 16, 2016 ISL78610 Daisy Chain Circuits ISL78610 COMMS SELECT2 COMMS SELECT1 SPI VSS FIGURE 46. NON-DAISY CHAIN COMMUNICATIONS CONNECTIONS AND SELECTION . V3P3 ISL78610 COMMS SELECT2 COMMS SELECT1 Daisy Down The daisy chain operates with standard unshielded twisted pair wiring. The component values given in Table 5 will accommodate cable capacitance values from 0pF to 50pF when operating at the 500kHz data rate. Higher cable capacitance values may be accommodated by either reducing the value of C2 or operating at lower data rates. V3P3 ISL78610 Daisy Up Daisy Down The values of components in Figure 48 are given in Table 5 for various Daisy chain operating data rates. VSS The circuit and component values of Figure 48 and Table 5 will accommodate cables with differential capacitance values in the ranges given. This allows a range of cable lengths to be accommodated through careful selection of cable properties. V3P3 ISL78610 Daisy Up COMMS SELECT2 COMMS SELECT1 The basic circuit elements are the series resistor and capacitor elements R1 and C1, which provide the transient current limit and AC coupling functions, and the line termination components C2, which provide the capacitive load. Capacitors C1 and C2 should be located as closely as possible to the board connector. The AC coupling capacitors C1 need to be rated for the maximum voltage, including transients, that will be applied to the interface. Specific component values are needed for correct operation with each daisy chain data rate and are given in Table 5 on page 28. VSS COMMS SELECT2 COMMS SELECT1 The ISL78610 daisy chain communications system external circuit arrangement is symmetrical to provide the bidirectional communications function. The performance of the system under transient voltage and EMI conditions is enhanced by the use of a capacitive load. A schematic of the daisy chain circuit for board to board connection is shown in Figure 48 on page 28. SPI VSS FIGURE 47. DAISY CHAIN COMMUNICATIONS CONNECTIONS AND SELECTION The circuit of Figure 48 provides full isolation when used with off board wiring. The daisy chain external circuit can be simplified in cases where the daisy chain system is contained within a single board. Figure 49 on page 28 and Table 6 on page 29 show the circuit arrangement and component values for single board use. In this case the AC coupling capacitors C1 need only be rated for the maximum transient voltage expected from device to device. Four daisy chain data rates are available and are configurable by pin selection using the COMMS RATE 0 and COMMS RATE 1 pins (see Table 4). TABLE 4. DAISY CHAIN COMMUNICATIONS DATA RATE SELECTION COMMS RATE 0 COMMS RATE 1 DATA RATE (kHz) 0 0 62 0 1 125 1 0 250 1 1 500 Submit Document Feedback 27 FN8830.1 June 16, 2016 ISL78610 ISL78610 CONNECTOR R2 R1 C1 DHi C2 VSS DGND1 R2 C2 C1 R1 DLo ISL78610 C1 R2 R1 DHi C2 DGND2 C1 C2 R1 VSS R2 DLo CONNECTOR FIGURE 48. ISL78610 DAISY CHAIN CIRCUIT IMPLEMENTATION TABLE 5. COMPONENT VALUES IN FIGURE 48 FOR VARIOUS DAISY CHAIN DATA RATES DAISY CHAIN CLOCK RATES COMPONENT 500kHz 250kHz 125kHz 62.5kHz C1 (4 ea) 220pF 470pF 1nF 2.2nF C2 (4 ea) 200pF (Note) 440pF 940pF 2nF R1 (4 ea) 470Ω 470Ω 470Ω 470Ω R2 (4 ea) 100Ω 100Ω 100Ω 100Ω Cable Capacitance Range 0 to 50pF 0 to 100pF 0 to 200pF 0 to 400pF COMMENTS NPO dielectric type capacitors are recommended. Please consult Intersil if Y type or “open mode” devices are required for your application. Use same dielectric type as C1 NOTE: Can be accommodated using two 100pF capacitors in parallel. ISL78610 ISL78610 C1 DHi1 VSS R1 DHi2 C2 C2 C2 R1 C2 DLo1 VSS DLo2 C1 DGND1 DGND2 ISOLATED GROUND PLANES ON THE SAME PCB FIGURE 49. ISL78610 DAISY CHAIN – BOARD LEVEL IMPLEMENTATION CIRCUIT Submit Document Feedback 28 FN8830.1 June 16, 2016 ISL78610 TABLE 6. DAISY CHAIN COMPONENT VALUES FOR BOARD LEVEL IMPLEMENTATION DAISY CHAIN DATA RATE COMPONENT TOLERANCE 500kHz 250kHz 125kHz 62.5kHz C1 (2 ea) 5% 100pF 220pF 470pF 1nF C2 (4 ea) 5% 220pF 470pF 1nF 2.2nF 1kΩ 1kΩ 1kΩ 1kΩ R1 (4 ea) TEMPREG VREF VCC 10M ADC EXT4 ISL78610 R1 10k R2 10k C1 10nF RT R12 FIGURE 50. CONNECTION OF NTC THERMISTOR TO INPUT EXT4 TABLE 7. COMPONENT FUNCTIONS AND DIAGNOSTIC RESULTS FOR CIRCUIT OF FIGURE 50 COMPONENT FUNCTION DIAGNOSTIC RESULT R1 Protection from wiring shorts to external HV connections. Open: Open-wire detection Short: No diagnostic result R2 Measurement high-side resistor Open: Low input level (over-temperature indication) Short: High input level (open-wire indication). Thermistor C1 Open: High input level (open-wire indication). Short: Low input level (over-temperature indication) Noise Filter. Connects to measurement ground VSS. External Inputs The ISL78610 provides 4 external inputs for use either as general purpose analog inputs or for NTC type thermistors. The arrangement of the external inputs is shown in Figure 50 using the ExT4 input as an example. It is important that the components are connected in the sequence shown in Figure 50, e.g., C1 must be connected such the trace from this capacitor’s positive terminal connects to R2 before connecting to R1. This guarantees the correct operation of the various fault detection functions. Each of the external inputs has an internal pull-up resistor, which is connected by a switch to the VCC pin whenever the TEMPREG output is active. This arrangement results in an open input being pulled up to the VCC voltage. Inputs above 15/16 of full scale are registered as open inputs and cause the relevant bit in the Over-Temperature Fault register, along with the OT bit in the Fault Status register to be set, on condition of the respective temperature test enable bit in the Fault Setup register. The user must then read the register value associated with the faulty input to determine if the fault was due to an open Submit Document Feedback 29 Open: No diagnostic result. Short: Low input level (over-temperature indication) input (value above 15/16 full scale) or an over-temperature condition (value below the External Temperature Limit setting). The function of each of the components in Figure 50 is listed in Table 7 together with the diagnostic result of an open or short fault in each component. Typical Applications Circuits Typical applications circuits are shown in Figures 51 to 57. Table 8 on page 38 contains recommended component values. All external (off-board) inputs to the ISL78610 are protected against battery voltage transients by RC filters, they also provide a current limit function during hot plug events. The ISL78610 is calibrated for use with 1kΩ series protection resistors at the cell inputs. VBAT uses a lower value resistor to accommodate the VBAT supply current of the ISL78610. A value of 27Ω is used for this component. As much as possible, the time constant produced by the filtering applied to VBAT should be matched to that applied to the cell 12 monitoring input. Component values given in Table 8 produce the required matching characteristics. FN8830.1 June 16, 2016 ISL78610 Figure 51 on page 31 shows the standard arrangement for connecting the ISL78610 to a stack of 12 cells. The cell input filter is designed to maximize EMI suppression. These components should be placed close to the connector with a well controlled ground to minimize noise for the measurement inputs. The balance circuits shown in Figure 51 provide normal cell monitoring when the balance circuit is turned off and a near zero cell voltage reading when the balance circuit is turned on. This is part of the diagnostic function of the ISL78610. Figure 52 on page 32 shows connections for the daisy chain system, setup pins, power supply and external voltage inputs for daisy chain devices other than the master (stack bottom) device. Figure 53 on page 33 shows the daisy chain system, setup pins, microcontroller interface, power supply and external voltage inputs for the daisy chain master device. Figure 53 is also applicable to stand-alone (non-daisy chain) devices although in this case, the daisy chain components connected to DHi2 and DLo2 would be omitted. Figure 54 on page 34 shows an alternate arrangement for the battery connections in which the cell input circuits are connected directly to the battery terminal and not via the balance resistor. In this condition, the balance diagnostic function capability is removed. Submit Document Feedback 30 Operating with Reduced Cell Counts When using the ISL78610 with fewer than 12 cells it is important to ensure that each used cell has a normal input circuit connection to the top and bottom monitoring inputs for that cell. The simplest way to use the ISL78610 with any number of cells is to always use the full input circuit arrangement for all inputs and short together the unused inputs at the battery terminal. In this way, each cell input sees a normal source impedance independent of whether or not it is monitoring a cell. The cell balancing components associated with unconnected cell inputs are not required and can be removed. Unused cell balance outputs should be tied to the adjacent cell voltage monitoring pin. The input circuit component count can be reduced in cases where fewer than 10 cells are being monitored. It is important that cell inputs that are being used are not connected to other (unused) cell inputs as this would affect measurement accuracy. Figures 55, through 57 starting on page 35, show examples of systems with 10 cells, 8 cells, and 6 cells, respectively. The component notations and values used in Figures 56 and 57 are the same as those used in Figures 51 to 54. In Figure 57 the resistor associated with the input filter on VC9 is noted as R5, rather than R5U. This value change is needed to maintain the correct input network impedance in the absence of the cell 9 balance circuits. FN8830.1 June 16, 2016 ISL78610 PLACE THESE COMPONENTS CLOSE TO CONNECTOR PACK VOLTAGE R1 B12b C1 D1 58 59 B12 R2 C27 61 R3 C3 R3A R31 C28 R32 R30 C29 R4 B9 R33 C4 R4A C30 Q4 R37 R39 C31 Q5 R40 R42 C32 Q6 R43 R45 C33 Q7 R46 R48 C34 Q8 R49 R51 C35 Q9 R52 R54 C36 R55 4 5 C7 R7A 6 7 C8 R8A 8 9 C9 R9A 10 11 C10 R10A R53 R11 B3 R6A R50 R10 B4 C6 R47 R9 B5 2 3 R44 R8 B6 R5A R41 R7 B7 C5 R38 R6 B8 64 1 R5U R5L R36 62 63 R34 Q3 R35 60 R27 R29 Q2 B10 R2A R28 Q1 B11 C2 12 13 C11 R11A R56 14 15 ISL78610 VBAT VBAT VC12 CB12 VC11 CB11 VC10 CB10 VC9 CB9 VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 Q10 R12 B2 R57 C37 Q11 R58 R12A R59 R13 B1 C12 16 17 C13 R13A 18 R60 C38 Q12 R61 R62 R71 B0 19 C39 R71A 20 21 B0b 22 VC2 CB2 VC1 CB1 VC0 VSS VSS FIGURE 51. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS Submit Document Feedback 31 FN8830.1 June 16, 2016 ISL78610 PLACE THESE COMPONENTS CLOSE TO DEVICE DHi2 56 R63 DHi1 DLo1 COMMS RATE 0 COMMS RATE 1 COMMS SELECT 1 COMMS SELECT 2 EN R65 C44 DAISY UP HI R66 C45 DAISY UP LO R69 C51 DAISY DN HI R70 C52 DAISY DN LO C42 ISL78610 DLo2 PLACE THESE COMPONENTS CLOSE TO CONNECTOR 55 R64 53 R67 C43 C49 52 R68 C50 43 42 Connect pins 40 to 43 to V3P3 or VSS Depending on comms selection and daisy chain clock speed 41 40 Connect pin 47 to V3P3 to Enable Connect pin 47 to VSS to Disable 47 PACK VOLTAGE DGND V2P5 BASE V3P3 VCC REF 44 R81 35 C53 V3P3 38 C55 Q13 36 R82 34 C54 33 C56 C57 TEMPREG EXT4 EXT3 EXT2 EXT1 R83 R84 R85 R86 29 30 R87 EXT IN 4 28 R90 EXT IN 3 26 R93 EXT IN 2 24 R96 EXT IN 1 C58 C59 C60 C61 FIGURE 52. TYPICAL APPLICATIONS CIRCUIT – NON BATTERY CONNECTIONS, MIDDLE AND TOP DAISY CHAIN DEVICES Submit Document Feedback 32 FN8830.1 June 16, 2016 ISL78610 PLACE THESE COMPONENTS CLOSE TO DEVICE DHi2 ISL78610 56 PLACE THESE COMPONENTS CLOSE TO CONNECTOR R63 R65 C44 DAISY UP HI R66 C45 DAISY UP LO C42 DLo2 COMMS RATE 0 COMMS RATE 1 COMMS SELECT 1 COMMS SELECT 2 SCLK CS DIN DOUT EN DATA READY FAULT 55 R64 C43 43 42 Connect pins 40 to 43 to V3P3 or VSS Depending on comms selection and daisy chain clock speed 41 40 Connect pin 47 to V3P3 to Enable Connect pin 47 to VSS to Disable 53 52 50 49 MICROCONTROLLER INTERFACE 47 46 45 PACK VOLTAGE DGND V2P5 BASE V3P3 VCC REF 44 R81 35 C53 V3P3 38 C55 Q13 36 R82 34 C54 33 C56 C57 TEMPREG EXT4 EXT3 EXT2 EXT1 R83 R84 R85 R86 29 30 R87 EXT IN 4 28 R90 EXT IN 3 26 R93 EXT IN 2 24 R96 EXT IN 1 C58 C59 C60 C61 FIGURE 53. TYPICAL APPLICATIONS CIRCUIT – NON BATTERY CONNECTIONS, MASTER DAISY CHAIN DEVICE Submit Document Feedback 33 FN8830.1 June 16, 2016 ISL78610 PLACE THESE COMPONENTS CLOSE TO CONNECTOR PACK VOLTAGE R1 B12b C1 D1 58 59 C27 B12 R27 B11 C28 R30 B10 C29 R33 R35 R36 Q4 Q5 C30 R37 Q6 C31 R40 C32 R43 Q7 C33 R46 Q8 C34 R49 R51 Q9 C35 R52 Q10 C36 R55 Q11 C37 R58 Q12 B0 C38 R61 2 3 4 5 C7 R7A 6 7 C8 R8A R47 R9A 10 11 R10A R53 12 13 R11A R56 14 15 R12A R59 16 17 R13A R62 R71 C 39 8 9 R50 R13 C 13 B1 R60 C6 R6A R12 C 12 B2 R57 R5A R11 C 11 B3 R54 C5 R10 C 10 B4 64 1 R99 C 9 B5 R48 C4 R4A R44 R8 62 63 R41 R7 B6 R45 C3 R3A R38 R6 B7 R42 R4 R5 B8 R39 R3 60 61 R34 Q3 B9 R2A R31 Q2 R32 C2 R28 Q1 R29 R2 18 19 R71A 20 21 B0b 22 VBAT ISL78610 VBAT VC12 CB12 VC11 CB11 VC10 CB10 VC9 CB9 VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS VSS FIGURE 54. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS ALTERNATIVE CONFIGURATION Submit Document Feedback 34 FN8830.1 June 16, 2016 ISL78610 PLACE THESE COMPONENTS CLOSE TO CONNECTOR PACK VOLTAGE B12b R1 B12 R2 C1 D1 58 59 Q1 B11 R29 Q2 B10 B9 R32 Q3 R35 R36 Q4 C2 R28 C27 C3 R3A C4 R4A R31 R30 R34 C29 R33 C30 R37 C31 R40 C5 R5A 2 3 R38 C6 R6A R41 R7 64 1 R5U R5L 62 63 R4 R6 Q5 61 R3 C28 60 R27 B8 R39 R2A 4 5 C7 R7A 6 7 R8 C8 R8A 8 9 R9 B5 R48 Q8 C34 R49 R50 R10 B4 R51 Q9 C35 R52 R54 C36 R55 Q10 R57 Q11 C37 R58 R10A 12 13 C11 R11A 14 15 C12 R12A R59 R13 B1 C10 R56 R12 B2 10 11 R53 R11 B3 C9 R9A 16 17 C13 R13A 18 R60 Q12 B0 B0b C38 R61 R62 R71 19 C39 R71A 20 21 22 VBAT ISL78610 VBAT VC12 CB12 VC11 CB11 VC10 CB10 VC9 CB9 VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS VSS FIGURE 55. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS, SYSTEM WITH 10 CELLS Submit Document Feedback 35 FN8830.1 June 16, 2016 ISL78610 PLACE THESE COMPONENTS CLOSE TO CONNECTOR VBAT B12b R1 B12 R2 C1 D1 58 59 Q1 B11 B10 B9 R28 C27 R32 Q3 R35 C3 R3A R31 R30 R33 C30 R37 R4 C4 R4A 64 1 R5U C5 R5L R5A 2 3 R38 R6 62 63 R34 C29 R36 Q4 61 R3 C28 60 R27 R29 Q2 C2 R2A C6 R6A 4 5 6 7 8 9 R9 C9 R9A 10 11 R10 B4 R51 Q9 C35 R52 R53 R11 B3 R54 C36 R55 Q10 R57 Q11 C37 R58 C11 R11A 14 15 C12 R12A R59 R13 B1 12 13 R56 R12 B2 C10 R10A 16 17 C13 R13A 18 R60 Q12 B0 C38 R61 R62 R71 19 C39 R71A 20 21 B0b 22 VBAT ISL78610 VBAT VC12 CB12 VC11 CB11 VC10 CB10 VC9 CB9 VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS VSS FIGURE 56. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS, SYSTEM WITH 8 CELLS Submit Document Feedback 36 FN8830.1 June 16, 2016 ISL78610 PLACE THESE COMPONENTS CLOSE TO CONNECTOR PACK VOLTAGE B12b R1 B12 R2 C1 D1 58 59 Q1 B11 B10 R28 C27 R3 R32 Q3 R35 61 C3 R3A C4 R4A R31 C28 R30 R4 R33 R5 62 63 R34 C29 60 R27 R29 Q2 C2 R2A 64 1 C5 R5A 2 3 4 5 6 7 8 9 10 11 R10 C10 R10A 12 13 R11 B3 R54 C36 R55 Q10 R57 Q11 R56 R12 B2 C37 R58 14 15 C12 R12A R59 R13 B1 C11 R11A 16 17 C13 R13A 18 R60 Q12 B0 B0b C38 R61 R62 R71 19 C39 R71A 20 21 22 VBAT ISL78610 VBAT VC12 CB12 VC11 CB11 VC10 CB10 VC9 CB9 VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS VSS FIGURE 57. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS, SYSTEM WITH 6 CELLS Submit Document Feedback 37 FN8830.1 June 16, 2016 ISL78610 TABLE 8. RECOMMENDED COMPONENT VALUES FOR FIGURES (Figures 51 to 57) RESISTORS VALUE COMPONENTS 0 R101 27 R1 33 R82 820 R2, R71 720 Figure 51 on page 31 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13 910 Figure 54 on page 34 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13 180 100 R2A, R3A, R4A, R5A, R6A, R7A, R8A, R9A, R10A, R11A, R12A, R13A 1/2W (or larger) R29, R32, R35, R36, R39, R42, R45, R48, R51, R54, R57, R60 1.3k R81 (assumes minimum pack voltage of 12V and maximum supply current of 6.5mA. Higher current or lower minimum pack voltage requires the use of a smaller resistor.) 100 R63, R64, R67, R68 1.4k R5U, R5L 470 R65, R66, R69, R70 10k R28, R31, R34, R38, R41, R44, R47, R50, R53, R56, R59, R62, R83, R84, R85, R86, R87, R90, R93, R96, R100a, R100b, R100c, R100d 330k R27, R30, R33, R37, R40, R43, R46, R49, R52, R55, R58, R61 CAPACITORS VALUE VOLTAGE COMPONENTS 200p 100 C42, C43, C49, C50 220p 500 C44, C45, C51, C52 10n 50 C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C58, C59, C60, C61 22n 100 C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C39 220n 100 C1 1µ 10 C53, C54, C56 1µ 100 C55 2.2µ 10 C57 ZENER DIODES VALUE EXAMPLE 54V PTVS54VS1UTR Submit Document Feedback 38 COMPONENTS D1 - DIODE-TVS, SMD, 2P, SOD-123W, 54VWM, 87.1VC FN8830.1 June 16, 2016 ISL78610 Notes on Board Layout Referring to Figure 51 on page 31 (battery connection circuits), the basic input filter structure comprises resistors R2 to R13, R71 and capacitors C2 to C13, C39. These components provide protection against transients and EMI for the cell inputs. They carry the loop currents produced by EMI and should be placed as close to the connector as possible. The ground terminals of the capacitors must be connected directly to a solid ground plane. Do not use vias to connect these capacitors to the input signal path or to ground. Any vias should be placed in line to the signal inputs so that the inductance of these forms a low pass filter with the grounded capacitors. Referring to Figure 52 on page 32, the daisy chain components are shown to the top right of the drawing. These are split into two sections. Components to the right of this section should be placed close to the board connector with the ground terminals of capacitors connected directly to a solid ground plane. This is the same ground plane that serves the cell inputs. Components to the left of this section should be placed as closely to the device as possible. The battery connector and daisy chain connectors should be placed closely to each other on the same edge of the board to minimize any loop current area. Two grounds are identified on the circuit diagram. These are nominally referred to as noisy and quiet grounds. The noisy ground, denoted by an “earth” symbol carries the EMI loop currents and digital ground currents while the quiet ground is used to define the decoupling voltage for voltage reference and the analog power supply rail. The quiet and noisy grounds should be joined at the VSS pin. Keep the quiet ground area as small as possible. with two devices in series, each with double the value of the single capacitor. A dual point failure in the balancing resistor (R29, R32, R35, etc.) of Figure 51 on page 31 and associated balancing MOSFET (Q1 to Q12) could also give rise to a shorted cell condition. It is recommended that the balancing resistor be replaced by two resistors in series. Board Level Calibration For best accuracy, the ISL78610 may be recalibrated after soldering to a board using a simple resistor trim. The adjustment method involves obtaining the average cell reading error for the cell inputs at a single temperature and cell voltage value and applying a select-on-test resistor to zero the average cell reading error. The adjustment system uses a resistor placed either between VDDEXT and VREF or VREF and VSS as shown in Figure 58. The value of resistor R1 or R2 is then selected based on the average error measured on all cells at 3.3V per cell and room temperature e.g., with 3.3V on each cell input scan the voltage values using the ISL78610 and record the average reading error (ISL78610 reading – cell voltage value). Table 9 shows the value of R1 and R2 required for various measured errors. To use Table 9, find the measured error value closest to the result obtained with measurements using the ISL78610 and select the corresponding resistor value. Alternatively, if finer adjustment resolution is required, then this may be obtained by interpolation using Table 9. VDDEXT R1 The circuits shown to the bottom right of Figure 52 on page 32 provide signal conditioning and EMI protection for the external temperature inputs. These inputs are designed to operate with external NTC thermistors. VREF C1 Each of the external inputs has an internal pull-up resistor, which is connected by a switch to the VCC pin whenever the TEMPREG output is active. This arrangement results in an open input being pulled up to the VCC voltage. Component Selection Certain failures associated with external components can lead to unsafe conditions in electronic modules. A good example of this is a component that is connected between high energy signal sources failing short. Such a condition can easily lead to the component overheating and damaging the board and other components in its proximity. One area to consider with the external circuits on the ISL78610 is the capacitors connected to the cell monitoring inputs. These capacitors are normally protected by the series protection resistors but could present a safety hazard in the event of a dual point fault where both the capacitor and associated series resistor fail short. Also, a short in one of these capacitors would dissipate the charge in the battery cell if left uncorrected for an extended period of time. It is recommended that capacitors C1 to C13 be selected to be “fail safe” or “open mode” types. An alternative strategy would be to replace each of these capacitors Submit Document Feedback 39 R2 VSS ISL78610 FIGURE 58. CELL READING ACCURACY ADJUSTMENT SYSTEM TABLE 9. COMPONENT VALUES FOR ACCURACY CALIBRATION ADJUSTMENT OF FIGURE 58 MEASURED ERROR AT VC = 3.3V V78610 - VCELL (mV) R1 (kΩ) 4 205 DNP 3 274 DNP 2 412 DNP 1 825 DNP 0 DNP DNP -1 DNP 2550 -2 DNP 1270 -3 DNP 866 -4 DNP 649 R2 (kΩ) DNP = Do Not Populate FN8830.1 June 16, 2016 ISL78610 System Commands To control the operation of the ISL78610 system, to read and write data to any individual device, and to check system status, the ISL78610 has a series of commands available to the host microcontroller. These commands are listed along with characteristics of the commands. Each command is individually described in the following. For these commands, there are certain attributes associated with each one. These attributes are the device response, whether the command can address all devices with a single command and whether there is a response from the target device. Device Response In a stand-alone configuration, the host should only expect a response when reading data from a register. In all other cases, there is no response expected. In a daisy chain configuration, all commands except any Scan, Measure, Sleep, Wake and Reset commands require a response from either the stack top device or the target device (see Table 10), each device in the stack waits for a response from the stack device above. Correct receipt of a command is indicated by the correct response. Failure to receive a response within a timeout period indicates a communications fault. The timeout value is stack position dependent. The device that detects the fault then transmits the Communications Failure response, which includes its stack address. The host microcontroller should build in handlers for commands that might be delayed within the communication structure and look for a Communications Failure response if the wait time expires. For more detail, see “Communication Faults” on page 74. An ACK response indicates that the command was successfully received by the target device. A NAK indicates that there was an error in decoding the command. Address All The “Address All” is only used in a daisy chain configuration. To address a particular device, the host microcontroller specifies the address of that device (1 through 14) for each of the maximum 14 devices. To address all devices in a daisy chain stack, the host microcontroller uses an address of 15 (Hex ‘1111’) to cause all stack devices to perform functions simultaneously. Only some commands recognize Address All. Read and Write Commands Read and Write commands are the primary communication mechanisms in the ISL78610 system. All commands make use of the read and write operations. Since a discussion of Read and Write operations involves detailed descriptions of protocols, timing, and interactions, it is presented below in “Communications” on page 52. Next are descriptions of the commands and how they are used to control the system. TABLE 10. COMMAND ATTRIBUTES NORMAL DEVICE RESPONSE DEVICE WAITS FOR A “ADDRESS ALL” COMPATIBLE RESPONSE? (Daisy Chain Only) (Daisy Chain Only) VALID IN STAND-ALONE OR DAISY CHAIN STAND-ALONE TOP TARGET Both Data ACK Data Yes Write Both - ACK ACK Yes No Scan Voltages Both - - - No Yes COMMAND Read No Scan Temperatures Both - - - No Yes Scan Mixed Both - - - No Yes Scan Wires Both - - - No Yes Scan All Both - - - No Yes Scan Continuous Both - ACK ACK Yes Yes Scan Inhibit Both - ACK ACK Yes Yes Sleep Both - ACK NAK No Yes Wake-up Both - ACK NAK No Yes Balance Enable Both - ACK ACK Yes Yes Balance Inhibit Both - ACK ACK Yes Yes Measure Both - - - No No Identify (special command) Daisy chain only - ACK NAK No Special address NAK Daisy chain only - ACK ACK Yes No ACK Daisy chain only - ACK ACK Yes No Reset Both - - - No No Calculate Register Checksum Both - ACK ACK Yes No Check Register Checksum Both - ACK ACK Yes No Submit Document Feedback 40 FN8830.1 June 16, 2016 ISL78610 Scan Voltages Command Scan Mixed Command When a device receives the Scan Voltages command to its stack address (or an Address All stack address), it increments the scan counter (see “Scan Counter” on page 43) and begins a scan of the cell voltage inputs. It sequences through the cell voltage inputs in order from cell 12 (top) to cell 1 (bottom). This operation is followed by a scan of the Pack Voltage. When a device receives the Scan Mixed command to its stack address (or an Address All stack address), it increments the Scan counter (see “Scan Counter” on page 43) and begins a Scan Mixed operation. The scan operation forces a sample and hold on each input, an analog-to-digital conversion of the voltage, and the storage of the value in its appropriate register. The IC temperature is also recorded for use with the internal calibration routines. The Scan Voltages command performs cell overvoltage and undervoltage comparisons on each cell input and checks the VBAT and VSS connections for open-wire at the end of the scan. If there is a fault condition (see “Fault Diagnostics” on page 76 for what constitutes a fault condition), the device sets the specific fault bit, sets the device FAULT pin active and sends an “unprompted fault response” to the host down the daisy chain communication link. (A stand-alone device only sets the FAULT pin.) The Unprompted Response is identical to a “Read Status Register” command. Devices revert to the Standby state on completion of the scan activity. Cell voltage and Pack voltage data, along with any fault conditions are stored in local memory ready for reading by the system host microcontroller. Scan Temperatures Command When a device receives the Scan Temperatures command to its stack address (or an Address All stack address), it increments the scan counter (see “Scan Counter” on page 43) and begins a scan of the temperature inputs. The Scan Temperatures command causes the addressed device (or all devices with an Address All stack address) to scan through the internal and 4 external temperature signals followed by multiplexer loopback and reference measurements. The loopback and reference measurements are part of the internal diagnostics function. Over-temperature compares are performed on each temperature measurement depending on the condition of the appropriate bit in the Fault Setup register. Temperature data, along with any fault conditions, are stored in local memory ready for reading by the system host microcontroller. If there is a fault condition, the device sets its FAULT pin active and on completion of a scan sends an “unprompted fault response” to the host down the daisy chain communication link. (A stand-alone device only sets the FAULT pin.) The Unprompted Response is identical to a “Read Status Register” command. Devices revert to the Standby state on completion of the scan activity. See also “Temperature Monitoring Operation” on page 43. The Scan Mixed command causes the addressed device (or all devices with an Address All stack address) to scan through the cell voltage inputs in order from cell 12 (top) to cell 7. Then the external input ExT1 is measured, followed by a scan of cell 6 to cell 1. These operations are followed by a scan of the Pack Voltage and the IC temperature. The IC temperature is recorded for use with the internal calibration routines. Scan Mixed also performs cell overvoltage and undervoltage comparisons on each cell voltage sampled. The VBAT and VSS pins are also checked for open conditions at the end of the scan. ExT1 is sampled in the middle of the cell voltage scan such that half the cells are sampled before ExT1 and half after ExT1. This mode allows ExT1 to be used for an external voltage measurement, such as a current sensing, so it is performed along with the cell voltage measurements, reducing the latency between measurements. The Scan Mixed command is intended for use in stand-alone systems, or by the master device in stacked applications, and would typically measure a single system parameter, such as battery current or Pack voltage. Cell voltage, Pack voltage and ExT1 data, along with any fault conditions are stored in local memory ready for reading by the system host microcontroller. Access the data from the ExT1 measurement by a direct Read ET1 Voltage command or by the All Temperatures read command. If there is a fault condition, (see “Fault Diagnostics” on page 76 for what constitutes a fault condition), the device sets the FAULT pin active and on completion of a scan sends an “unprompted fault response” to the host down the daisy chain communication link. (A stand-alone device only sets the FAULT pin.) The unprompted response is identical to a “Read Status Register” command. Devices revert to the Standby state on completion of the scan activity. Scan Wires Command When a device receives the Scan Wires command to its stack address (or an Address All stack address), it increments the Scan counter (see “Scan Counter” on page 43) and begins a Scan Wires operation. The Scan Wires command causes the addressed device (or all devices with an Address All stack address) to measure all the VCn pin voltages while applying load currents to each input pin in turn. This is part of the fault detection system. If there is a fault condition, the device sets the FAULT pin and returns a fault signal (sent down the stack) on completion of a scan. No cell voltage data is sent as a result of the Scan Wires command. Devices revert to the standby state on completion of this activity. Submit Document Feedback 41 FN8830.1 June 16, 2016 ISL78610 Scan All Command When a device receives the Scan All command to its stack address (or an Address All stack address), it increments the Scan counter (see “Scan Counter” on page 43) and begins a Scan All operation. The Scan All command causes the addressed device (or all devices with an Address All stack address) to execute the Scan Voltages, Scan Wires and Scan Temperatures commands in sequence one time (see Figure 59 on page 44 for example timing). Scan Continuous Command Scan Continuous mode is used primarily for fault monitoring and incorporates the Scan Voltages, Scan Temperatures and Scan Wires commands. See also “Temperature Monitoring Operation” on page 43. The Scan Continuous command causes the addressed device (or all devices with an Address All stack address) to set the SCAN bit in the Device Setup register and performs a succession of scans at a predetermined scan rate. Each device operates asynchronously on its own clock. This is similar to the Scan All command except that the scans are repeated at intervals determined by the SCN0-3 bits in the Fault Setup register. The ISL78610 provides an option that pauses cell balancing activity while measuring cell voltages in Scan Continuous mode. This is controlled by the BDDS bit in the Device Setup register. If BDDS is set, then cell balancing is inhibited during cell voltage measurement and for 10ms before the cell voltages are scanned. Balancing is re-enabled at the end of the scan to allow balancing to continue. This function only applies during the Scan Continuous and the Auto Balance functions and allows the implementation of a circuit arrangement that can be used to diagnose the condition of external balancing components. It is up to the host microcontroller to manually stop balancing functions (if required) when operating a Scan or Measure command. Data is not automatically returned while devices are in Scan Continuous mode except in the case where a fault condition is detected. The results of voltage and temperature scans are stored in local volatile memory and may be accessed at any time by the system host microcontroller. However, since the scan continuous operation is running asynchronously to any communications, it is recommended that the continuous scan be stopped before reading the registers. Devices may be operated in Scan Continuous mode while in Normal mode or in Sleep mode. Devices revert to the Sleep mode or remain in Normal mode, as applicable on completion of each scan. The response to a detected fault condition is to send the Fault signal, either immediately in the case of stand-alone devices or daisy chain devices in Normal mode, or following transmission of the Wake-up signal if the device is being used in a daisy chain configuration and is in Sleep mode. To operate the “Scan Continuous” function in Sleep mode, the host microcontroller simply configures the ISL78610, starts the Scan Continuous mode and then sends the Sleep command. The ISL78610 then wakes itself up each time a scan is required. Note that for the fastest scan settings (scan interval codes 0000, 0001 and 0010) the main measurement functions do not power down between scans, since the ISL78610 remains in Normal mode. TABLE 11. SCAN CONTINUOUS TIMING MODES SCAN INTERVAL SCN3:0 SCAN INTERVAL (ms) TEMP SCAN (ms) WIRE SCAN WSCN = 0 (ms) WIRE SCAN WSCN = 1 (ms) 0000 16 512 512 512 0001 32 512 512 512 0010 64 512 512 512 The Scan Continuous scan interval is set using the SCN3:0 bits (lower nibble of the Fault Setup register.) The temperature and wire scans occur at slower rates and depend on the value of the scan interval selected. The scan system is synchronized such that the wire and temperature scans always follow a voltage scan. The three scan sequences, depending on the scans required at a particular instance, are as follows: 0011 128 512 512 512 0100 256 1024 512 1024 0101 512 2048 512 2048 0110 1024 4096 1024 4096 0111 2048 8192 2048 8192 • Scan Voltages 1000 4096 16384 4096 16384 • Scan Voltages, Scan Wires 1001 8192 32768 8192 32768 • Scan Voltages, Scan Wires, Scan Temperatures 1010 16384 65536 16384 65536 1011 32768 131072 32768 131072 1100 65536 262144 65536 262144 The temperature and wire scans occur at 1/5 the voltage scan rate for voltage scan intervals above 128ms. Below this value the temperature scan interval is fixed at 512ms. The behavior of the wire scan interval is determined by the WSCN bit in the Fault Setup register. A bit value of ‘1’ causes the wire scan to be performed at the same rate as the temperature scan. A bit value of ‘0’ causes the wire scan rate to track the voltage scan rate for voltage scan intervals above 512ms while at, and below this value, the wire scan is performed at a fixed 512ms rate. Table 11 shows the various scan rate combinations available. Submit Document Feedback 42 Scan Inhibit Command The Scan Inhibit command is used to a Continuous scan (i.e., receipt of this command by the target device resets the SCAN bit and stops the Scan Continuous function). FN8830.1 June 16, 2016 ISL78610 Measure Command When a device receives the Measure command to its stack address, it increments the scan counter (see “Scan Counter” on page 43) and begins a Measure operation. This command initiates the voltage measurement of a single cell voltage, internal temperature, any of the four external temperature inputs, or the secondary voltage reference. The command incorporates a 6-bit suffix that contains the address of the required measurement element. See Table 12 on page 43 and Figure 64B on page 55. The device matching the target address responds by conducting the single measurement and loading the result to local memory. The host microcontroller then reads from the target device to obtain the measurement result. All devices revert to the Standby state on completion of this activity. TABLE 12. MEASURE COMMAND TARGET ELEMENT ADDRESSES MEASURE COMMAND (SUFFIX) DESCRIPTION 6’h00 VBAT Voltage 6’h01 Cell 1 Voltage 6’h02 Cell 2 Voltage 6’h03 Cell 3 Voltage 6’h04 Cell 4 Voltage 6’h05 Cell 5 Voltage 6’h06 Cell 6 Voltage 6’h07 Cell 7 Voltage 6’h08 Cell 8 Voltage 6’h09 Cell 9 Voltage 6’h0A Cell 10 Voltage 6’h0B Cell 11 Voltage 6’h0C Cell 12 Voltage 6’h10 Internal temperature reading 6’h11 External temperature input 1 reading. 6’h12 External temperature input 2 reading. 6’h13 External temperature input 3 reading. 6’h14 External temperature input 4 reading. 6’h15 Reference voltage (raw ADC) value. Use this value to calculate corrected reference voltage using reference coefficient data. The scan counter increments whenever the ISL78610 receives a Scan or Measure command. The ISL78610 does not perform a requested Scan or Measure function if there is already a Scan or Measure function in progress, but it still increments the scan counter. Temperature Monitoring Operation One internal and four external temperature inputs are provided together with a switched bias voltage output (TEMPREG, pin 29). The voltage at the TEMPREG output is nominally equal to the ADC reference voltage such that the external voltage measurements are ratiometric to the ADC reference (see Figure 50 on page 29). The temperature inputs are intended for use with external resistor networks using NTC type thermistor sense elements but may also be used as general purpose analog inputs. Each temperature input is applied to the ADC via a multiplexer. The ISL78610 converts the voltage at each input and loads the 14-bit result to the appropriate register. The TEMPREG output is turned “on” in response to a Scan Temperatures or Measure Temperature command. A dwell time of 2.5ms is provided to allow external circuits to settle, after which the ADC measures each external input in turn. The TEMPREG output turns “off” after measurements are completed. Figure 59 on page 44 shows an example temperature scan with the ISL78610 operating in Scan Continuous mode with a scan interval of 512ms. The preceding voltage and wire scans are shown for comparison. The external temperature inputs are designed such that an open connection results in the input being pulled up to the full scale input level. This function is provided by a switched 10MΩ pull-up from each input to VCC. This feature is part of the fault detection system and is used to detect open pins. The internal IC temperature, along with the Auxiliary Reference Voltage, and multiplexer loopback signals, are sampled in sequence with the external signals using the Scan Temperatures command. The converted value from each temperature input is also compared to the external over-temperature limit and open connection threshold values on condition of the [TST4:1] bits in the Fault Setup register (see “Fault Setup:” on page 85.) If a TSTn bit is set to “1”, then the temperature value is compared to the External Temperature threshold and a Fault occurs if the measured value is lower than the threshold value. If a TSTn bit is set to “0”, then the temperature measurement is not compared to the threshold value and no fault occurs. The [TST4:1] bits are “0” by default. Scan Counter Since the Scan and Measure commands do not have a response, the scan counter is provided to allow confirmation of receipt of the Scan and Measure commands. This is a 4-bit counter located in the Scan Count register (page 1, address 6’h16). The counter increments each time a Scan or Measure command is received. This allows the host microcontroller to compare the counter value before and after the Scan or Measure command was sent to verify receipt. The counter wraps to zero when overflowed. Submit Document Feedback 43 FN8830.1 June 16, 2016 ISL78610 512ms VOLTAGE SCAN 765µs WIRE SCAN 59.4ms TEMPERATURE SCAN 2.69ms 2.5V TEMPREG PIN Hi-Z Hi-Z Hi-Z 2.5ms ADC SAMPLING FIGURE 59. SCAN TIMING EXAMPLE DURING SCAN CONTINUOUS MODE AND SCAN ALL MODE Sleep Command TABLE 13. MAXIMUM WAIT TIME FOR DEVICES ENTERING SLEEP MODE Sleep mode is entered in response to a Sleep command. Only the communications input circuits, low speed oscillator and internal registers are active in Sleep mode, allowing the part to perform timed scan and balancing activity and to wake up in response to communications. Using a Sleep command does not require that the devices in a daisy chain stack be identified first. They do not need to know their position in the stack. In a daisy chain system, the Sleep command must be written using the Address All stack address. The command is not recognized if sent with an individual device address and causes the addressed device to respond NAK. The top stack device responds ACK on receiving a valid Sleep command. Having received a valid Sleep command, devices wait before entering the Sleep mode. This is to allow time for the top stack device in a daisy chain to respond ACK, or for all devices that don’t recognize the command to respond NAK, and for the host microcontroller to respond with another command. Receipt of any valid communications on Port 1 of the ISL78610 before the wait period expires cancels the Sleep command. Receipt of another Sleep command restarts the wait timers. Table 13 provides the maximum wait time for various daisy chain data rates. The communications fault checking timeout is not applied to the Sleep command. A problem with the communications is indicated by a lack of response to the host microcontroller. The host microcontroller may choose to do nothing if no response is received, in which case, devices that received the Sleep command go to sleep when the wait time expires. Devices that do not receive the message go to sleep when their watchdog timer expires (as long as this is enabled). Devices exit Sleep mode on receipt of a valid Wake-up command. Submit Document Feedback 44 MAXIMUM WAIT TIME FROM TRANSMISSION OF SLEEP COMMAND (DAISY CHAIN ONLY) DAISY CHAIN DATA RATE (kHz) Time to Enter Sleep mode (µs) 500 250 125 62.5 500 1000 2000 4000 Wake Command The communications pins are monitored when the device is in Sleep mode, allowing the part to respond to communications. The host microcontroller wakes up a sleeping device, or a stack of sleeping devices, by sending the Wake-up command to a stand-alone or a master stack device. In a daisy chain configuration, the Wake-up command must be written using the Address All stack address. The command is not recognized if sent with an individual device address and causes the master device to respond NAK. Using a Wake-up command does not require that the devices in a stack be identified first. They do not need to know their position in the stack. The master exits Sleep mode on receipt of a valid Wake-up command and proceeds to transmit the Wake-up signal to the next device in the stack. The Wake-up signal is a few cycles of a 4kHz clock. Each device in the chain wakes up on receipt of the Wakeup signal and proceeds to send the signal onto the next device. Any communications received on Port 1 by a device which is transmitting the Wake-up signal on Port 2 are ignored. The top stack device, after waking up, waits for some time before sending an ACK response to the master. This wait time is necessary to allow receipt of the Wake-up signal being originated by a stack device other than the master. See “Fault Response in Sleep Mode” on page 76 for more information. FN8830.1 June 16, 2016 ISL78610 The master device passes the ACK on to the host microcontroller to complete the Wake-up sequence. The total time required to wake up a complete stack of devices is dependent on the number of devices in the stack. Table 14 gives the maximum time from Wake-up command transmission to receipt of ACK response (DATA READY asserted low) for stacks of 8 devices and 14 devices at various daisy chain data rates (interpolate linearly for different number of devices). TABLE 14. MAXIMUM WAKE-UP TIMES FOR STACKS OF 8 DEVICES AND 14 DEVICES (WAKE-UP COMMAND TO ACK RESPONSE) MAXIMUM WAKE-UP TIMES DAISY CHAIN DATA RATE (kHz) 500 250 125 62.5 Stack of 8 Devices (ms) 63 63 63 63 Stack of 14 Devices (ms) 100 100 100 100 CELL BALANCING FUNCTIONS Cell balancing is performed using external MOSFETs and external current balancing resistors (see Figure 51 on page 31). Each MOSFET is controlled independently by the CB1 to CB12 pins of the ISL78610. The CB1 to CB12 outputs are controlled either directly, or indirectly by an external microcontroller through bits in various control registers. There are three cell balance modes, Manual, Timed and Auto. TABLE 15. REGISTERS CONTROLLING BALANCE REGISTER BALANCE MODE REFERENCE Balance Setup Manual, Timed, Auto Table 16 on page 46 Balance Status Manual, Timed, Auto Table 16 on page 46 Watchdog/Balance Time Timed, Auto Table 18 on page 47 Device Setup Timed, Auto “Set-Up Registers” on page 87 Balance Value Auto only Table 19 on page 49 There is no additional checking for communications faults while devices are waking up. A communications fault is indicated by the host microcontroller not receiving an ACK response within the expected time. BALANCE MODE Reset Command Set the Balance mode with the BMD1 and BMD0 bits in the Balance Setup Register (see Table 16). All digital registers can be reset to their power-up condition using the Reset Command. In Manual mode, the host microcontroller directly controls the state of each MOSFET output. Daisy chain devices must be reset in sequence from top stack device to stack bottom (master) device. Sending the Reset command to all devices using the Address All stack address has no effect. There is no response from the stack when sending a Reset command. In Timed mode, the host microcontroller programs a balance duration value and selects which cells are to be balanced, then starts the balance operation. The ISL78610 turns all the FETs off when the balance duration has been reached. All stack address and stack size information is set to zero in response to a Reset command. Once all devices have been reset it is necessary to reprogram the stack address and stack size information using the Identify command. A Reset command should be issued following a “hard reset” in which the EN pin is toggled. Balance Enable Command The Balance Enable command sets the BEN bit, which starts the balancing operation. However, before this command becomes operational and before balancing can commence, the balance operation needs to be specified. See “Cell Balancing Functions”. The Balance Enable command can be sent to all devices with one command using Address All addressing. Balance Inhibit Command In Auto Balance mode, the host microcontroller programs the ISL78610 to control the balance MOSFETs to remove a programmed “charge delta” value from each cell. The ISL78610 does this by controlling the amount of charge removed from each cell over a number of cycles, rather than trying to balance all cells to a specific voltage. BALANCE WAIT TIME The balance wait time is the interval between balancing operations in Auto Balance mode (see Table 16). BALANCE ENABLE When all of the other balance control bits are properly set, setting the balance Enable bit to “1” starts the balance operation. The BEN bit can be set by writing directly to the Balance Setup register or by sending a Balance Enable command. See Table 16. The Balance Inhibit command clears the BEN bit, which stops the balancing operation. The Balance Inhibit command can be sent to all devices with one command using Address All addressing. Submit Document Feedback 45 FN8830.1 June 16, 2016 ISL78610 TABLE 16. BALANCE SETUP REGISTER REGISTER BITS 7 6 5 4 BEN BALANCE BSP3 BSP2 BSP1 BSP0 Off 0 0 0 0 Balance Status 0 9 8 7 6 5 4 3 2 1 Set bit to 1 to enable balance 1 On 2 1 0 SECONDS BALANCE BETWEEN BALANCE CYCLES BMD1 BMD0 MODE BWT2 BWT1 BWT0 POINT TO REGISTER 12 11 10 0 3 0 0 0 0 0 0 Off Manual/ Timed 8 0 0 0 1 Balance Status 1 0 0 1 1 0 1 Manual 0 0 1 0 Balance Status 2 0 1 0 2 1 0 Timed 0 0 1 1 Balance Status 3 0 1 1 4 1 1 Auto 0 1 0 0 Balance Status 4 1 0 0 8 0 1 0 1 Balance Status 5 1 0 1 16 0 1 1 0 Balance Status 6 1 1 0 32 0 1 1 1 Balance Status 7 1 1 1 64 1 0 0 0 Balance Status 8 1 0 0 1 Balance Status 9 1 0 1 0 Balance Status 10 1 0 1 1 Balance Status 11 1 1 0 0 Balance Status 12 BALANCE STATUS POINTER The Balance Status register is a “multiple instance” register (see “Balance Status Register” on page 46. There are 13 locations within this register and only one location may be accessed at a time. The Balance Status Pointer points to one of these 13 locations. (See Table 16). Manual Balance mode and Timed Balance mode requires a balance status pointer value of ‘0’. In this case, the bits in the Balance Status Register directly select the cells to be balanced. Auto Balance Mode Only 9 bit 11 [BAL12] controls the FET for cell 12. Bits are set to ‘1’ to enable the balancing for that cell and cleared to ‘0’ to disable balancing. Manual Balance Mode In Manual Balance mode, the host microcontroller specifies which cell is balanced and controls when balancing starts and stops. To manually control the cells to be balanced: The Auto Balance mode uses Balance Status register locations 1 to 12 (see Table 16). In Auto Balance mode, the ISL78610 increments the Balance Status pointer on each auto balance cycle to step through Balance Status register locations 1 to 12. This allows the programming of up to twelve different balance profiles for each Auto Balance operation. When the operation encounters a zero value at a pointer location, the auto balance operation returns to the pattern at location 1 and resumes balancing with that pattern. • Set the Balance Mode bits to ‘01’ for “Manual” More information about the Auto Balance mode is provided in “Auto Balance Mode” on page 47. Example balancing setup information is provided in “Auto Balance Mode Cell Balancing Example” on page 80. The Balance Enable and Balance Inhibit commands may be used with the “Address All” device address to control all devices in a stack simultaneously. BALANCE STATUS REGISTER The Balance Status register contents control which external balance FET is turned on during a balance event. Each of the 12 bits in the Balance Status register controls one external balancing FET, such that bit 0 [BAL1] controls the cell 1 FET and Submit Document Feedback 46 • Set the balance status pointer to zero • Set bits in the Balance Status register to program the cells to be balanced (e.g., to balance cell 5, set the BAL5 bit to 1) • Enable balancing, either by setting the BEN bit in the Balance Setup register or by sending a Balance Enable command • Disable balancing either by resetting the BEN bit or by sending a Balance Inhibit command Manual Balance mode cannot operate while the ISL78610 is in Sleep mode. If the watchdog timer is off and the Sleep command is received during Manual balance, then balancing stops immediately and the device goes into Sleep mode. FN8830.1 June 16, 2016 ISL78610 TABLE 17. BALANCE, SLEEP, WAKE, WATCHDOG TIMER OPERATION RECEIVE SLEEP COMMAND WATCHDOG TIMES OUT ALL BALANCE MODES ALL BALANCE MODES Off Stop balancing Device enters the Sleep mode. N/A N/A N/A N/A On N/A Stop balancing. Stop balancing. Device enters the Sleep mode. Device enters the Sleep mode. Set the WDTM bit. Set the WDTM bit when the watchdog timer expires. N/A N/A N/A N/A OPERATING WATCHDOG IN TIMER Normal Mode Sleep Mode RECEIVE WAKE COMMAND MANUAL BALANCE N/A If the watchdog timer is active during manual balance and the device receives the Sleep command, then balancing stops immediately and the device goes into Sleep mode, but the WDTM bit is set when the watchdog timer expires (see Table 17). The ISL78610 has a watchdog timer function that protects the battery from excess discharge due to balancing. In the event that communications is lost the watchdog begins a count down. If the timeout value is exceeded while the part is in Manual Balance mode all balancing ceases and the device goes into Sleep mode. See Table 17. If the device was performing a manual balance operation prior to a Sleep command, then receiving a Wake command resumes balancing. TIMED BALANCE Resume Balancing Resume Balancing, Balance time reduced by the time spent in Sleep AUTO BALANCE Resume Balancing with Auto Balance settings suspended during Sleep TABLE 18. WATCHDOG/BALANCE TIME REGISTER REGISTER BITS 13 12 11 10 9 8 7 BTM6 BTM5 BTM4 BTM3 BTM2 BTM1 BTM0 BALANCE TIME (MINUTES) 0 0 0 0 0 0 0 Disabled 0 0 0 0 0 0 1 0.33 0 0 0 0 0 1 0 0.67 0 0 0 0 0 1 1 1.00 ••• - 1 1 1 1 1 0 1 41.67 Timed Balance Mode 1 1 1 1 1 1 0 42.00 In Timed Balance mode, the host microcontroller specifies which cell is balanced and sets a balance time-out period. Balancing starts by control of the microcontroller and stops at the end of a time-out period (or by command from the microcontroller.) 1 1 1 1 1 1 1 42.33 To set up a timed balance operation: • Set the Balance mode bits to ‘10’ for “Timed” • Set the Balance Status Pointer to zero • Set bits in the Balance Status register to program the cells to be balanced (e.g., to balance cells 7 and 10, set BAL7 and BAL10 bits to 1) • Set the balance on time. The balance on time is programmable in 20 second intervals from 20 seconds to 42.5 minutes using BTM[6:0] bits. See Table 18. • Enable balancing, either by setting the BEN bit in the Balance Setup register or by sending a Balance Enable command. When BEN is reasserted, or when a new Balance Enable command is received, balancing resumes, using the full time specified by the BTM[6:0] bits. • Disable balancing either by resetting the BEN bit or by sending a Balance Inhibit command. Resetting BEN stops the balancing functions and resets the timer values. • When the balance timeout period is met, the End Of Balance (EOB) bit in the Device Setup register is set and BEN is reset. Submit Document Feedback 47 Timed Balance mode cannot operate while the ISL78610 is in Sleep mode. If the watchdog timer is off and the Sleep command is received during Manual balance, then balancing stops immediately and the device goes into Sleep mode. If the watchdog timer is active during Timed balance and the device receives the Sleep command, then balancing stops immediately and the device goes into Sleep mode, but the WDTM bit is set when the watchdog timer expires (see Table 17). If the watchdog timeout value is exceeded while the part is in Manual Balance mode all balancing ceases and the device goes into Sleep mode (see Table 17). If the device was performing a Timed balance operation prior to a Sleep command, then receiving a Wake command resumes balancing. However, the balance timer continues during the Sleep mode, so if the Balance timer expires before a Wake command, then Balance will not resume until the host microcontroller starts another balance cycle. Auto Balance Mode In Auto Balance mode, the host microcontroller specifies an amount of charge to be removed from each cell to be balanced. Balancing starts by control of the microcontroller and stops when all cells have had the specified charge removed (or by command from the microcontroller.) FN8830.1 June 16, 2016 ISL78610 Auto Balance mode performs balancing autonomously and in an intelligent manner. Thermal issues are accommodated by the provision of auto balance sequencing (see “Auto Balance Sequencing” on page 48), a multiple instance Balance Status register and a balance wait time. During Auto Balance mode the ISL78610 cycles through each Balance Status register instance, which turns on the balancing outputs corresponding to the bits set in each Balance Status register instance. While each cell is being balanced, the amount of charge withdrawn is calculated. Balancing stops for a cell when the specified amount of charge has been removed. See “Auto Balance SOC Adjustment value” on page 48. When Auto Balancing is complete, the End Of Balance (EOB) bit in the Device Setup register is set and BEN bit is reset. To set up an auto balance operation: • Set the Balance Mode bits to ‘11’ for Auto • Set the Balance Status Pointer to ‘1’ • Set bits in the Balance Status register to program the cells to be balanced in the first cycle (e.g., to balance odd cells, set bits 1, 3, 5, 7, 9 and 11) • Set the Balance Status Pointer to ‘2’ • Set bits in the Balance Status register to program the cells to be balanced in the second cycle (e.g., to balance even cells, set bits 2, 4, 6, 8, 10 and 12) • Set the Balance Status Pointer to ‘3’ • Set bits in the Balance Status register at this location to zero to terminate the sequence. The next cycle will go back to balance at status pointer = 1. • Write the B values into the Balance Value Registers for each cell to be balanced. • Enable balancing, either by setting the BEN bit in the Balance Setup register or by sending a Balance Enable command. Once enabled, the ISL78610 cycles through each instance of the Balance Status register for the duration given by the balance timeout. Between each Balance Status register instance, the device does a Scan All operation and inserts a delay equal to the balance wait time. The process continues with the balance status pointer wrapping back to 1, until all the Balance Value registers equal zero. If one cell Balance Value register reaches zero before the others, balancing for that cell stops, but the others continue. • Disable balancing either by resetting the BEN bit or by sending a Balance Inhibit command. Resetting BEN, either directly or by using the Balance Inhibit command, stops the balancing functions but maintains the current Balance Value register contents. Auto Balancing continues from Balance Status register location 1 when BEN is reasserted. AUTO BALANCE SEQUENCING Balance Status register instance at balance status pointer location 1. For example, using two Balance Status registers, the ISL78610 can balance odd numbered cells during the first cycle and even numbered cells on the second cycle. Between each cycle, there is a delay time. This delay is set by the balance wait time bits (see Table 16 on page 46) Cells are balanced with periodic measurements being performed during the balance time interval (see Table 18). These measurements are used to calculate the reduction in State of Charge (SOC) with each balancing cycle. As individual cells reach their programmed SOC adjustment, that cell balance terminates, but the balance operation continues cycling through all instances until all cells have met their SOC adjustment value. AUTO BALANCE SOC ADJUSTMENT VALUE The balance value (delta SOC) is the difference between the present charge in a cell and the desired charge for that cell. The method for calculating the state of charge for a cell is left to the system designer. Typically, determining the state of charge is dependent on the chosen cell type and manufacturer, is dependent on cell voltage, charge and discharge rates, temperature, age of the cell, number of cycles and other factors. Tables for determining SOC are often available from the battery cell manufacturer. The balance value itself is a function of the current SOC, required SOC, balancing leg impedance and sample interval. This value is calculated by the host microcontroller for each cell. The balancing leg impedance is made up of the external balance FET and balancing resistor. The sample interval is equal to the balance cycle on-time period (e.g., each cell voltage is sampled at the end of the balance on-time). The balancing value B for each cell is calculated using the formula shown in Equation 1 (see also “Balance Value Calculation Example” on page 80): 8191 Z B = ------------- CurrentSOC – T arg etSOC ----5 dt (EQ. 1) Where: B = The balance register value CurrentSOC = The present SOC of the cell (Coulombs) TargetSOC = The required SOC value (Coulombs) Z = The balancing leg impedance (ohms) dt = The sampling time interval (Balance cycle on time in seconds) 8191/5 = A voltage to Hex conversion value The balancing leg impedance is normally the sum of the balance FET rDS(ON) and the balance resistor. The first cycle of the auto balance operation begins with the balance status pointer at location 1, specifying the first Balance Status register instance. For the next auto balance cycle, the balance status pointer increments to location 2. For each subsequent cycle, the pointer increments to the next Balance Status register instance, until a zero value instance is encountered. At this point the sequence repeats from the Submit Document Feedback 48 FN8830.1 June 16, 2016 ISL78610 The balancing value (B) can also be defined as in the set of equations following. Auto balance is guided by Equations 2 and 3: V SOC = I t = ---- t Z (EQ. 2) Z V Z V B = SOC ----- = ---- t ----- = ----- t dt Z dt dt (EQ. 3) dt = Balance cycle on time t = Total balance time Looking at Equations 2 and 3, the impedance drops out of the equation, leaving only voltage and time elements. So, “B” becomes a collection of voltages that integrate during the balance cycle on time, and accumulate over the total balance time period, to equal the programmed delta capacity. TABLE 19. BALANCE VALUES REGISTER CELL1 AND CELL2 8 7 6 5 4 3 6’20 Cell 1 Balance Value Bits [13:0] 6’21 Cell 1 Balance Value Bits [27:14] 6’22 Cell 2 Balance Value Bits [13:0] 6’23 Cell 2 Balance Value Bits [27:14] 2 1 0 At the end of each balance cycle on time interval the ISL78610 measures the voltage on each of the cells that were balanced during that interval. The measured values are then subtracted from the balance values for those cells. This process continues until the balance value for each cell is zero, at which time the auto balancing process is complete. Auto Balance mode cannot operate while the ISL78610 is in Sleep mode. If the Sleep command is received while the device is auto balancing (and the watchdog timer is off) then balancing continues until it is finished and then the device enters Sleep mode. If the watchdog timer is active during the Auto Balance mode and the device receives the Sleep command, then balancing stops immediately, the device enters Sleep mode immediately. The WDTM bit is set when the watchdog timer expires (see Table 17). If the device was performing an Auto balance operation prior to a Sleep Command, then receiving a Wake command resumes balancing with the same SOC calculations that were in place when the device entered the Sleep Mode. BALANCING IN SCAN CONTINUOUS MODE Cell balancing may be active while the ISL78610 is operating in Scan Continuous mode. In Scan Continuous mode the ISL78610 scans cell voltages, temperatures and open-wire conditions at a rate determined by the Scan Interval bits in the Fault Setup register. (See Table 11 on page 42). The behavior of the Submit Document Feedback 49 7 6 5 4 3 2 CBEN8 CBEN7 CBEN6 CBEN5 CBEN4 CBEN3 1 0 CBEN1 8 CBEN2 9 CBEN9 10 CBEN11 CBEN12 11 CBEN10 TABLE 20. CELLS BEING BALANCED REGISTER Twelve 28-bit registers are provided for the balance value for each cell. The balance values are programmed for all cells as needed using Balance Value registers 6’h20 to 6’h37. (See Table 19 for the contents of the Cell 1 and Cell 2 Balance Values registers.) 9 MONITORING CELL BALANCE To facilitate the system monitoring of the cell balance operation, the ISL78610 has a Cells Being Balanced register that shows the present state of the balance drivers If the bit is “1” it indicates that the CBn output is enabled. A “0” indicates that the CBn output is disabled. Where: ADDR 13 12 11 10 balancing functions while operating in Scan Continuous mode is controlled by the BDDS bit in the Device Setup register. If BDDS is set, then cell balancing is inhibited during cell voltage measurements and for 10ms before the cell voltage scan to allow the balance devices to turn off. Balancing is re-enabled automatically at the end of the scan. Daisy Chain Commands Daisy chain devices require some special commands that are not needed by a stand-alone device. These commands are Identify, ACK and NAK. Identify is needed to enumerate the devices in the stack. ACK is used as a command to check the communications hardware and to indicate proper communications status. A NAK response indicates that there was some problem with the addressed device recognizing the command. Identify Command Identify mode is a special case mode that must be executed before any other communications to daisy chained devices, except for the Sleep command and Wake-up command. The Identify command initiates address assignments to the devices in the daisy chain stack. While in Identify mode devices determine their stack position. Identify mode is entered on receipt of the “base” Identify command (this is the Identify command with the device address set to 6’h00). The top stack device responds ACK on receiving the base Identify command and then enters the Identify mode. Other stack devices wait to allow the ACK response to be relayed to the host microcontroller, then they enter Identify mode. Once in Identify mode, all stack devices except the master, load address 4’h0 to their stack address register. The master (identified by the state of the Comms Select pins = 2’b01) loads 4’h1 to its stack address. On receiving the ACK response the host microcontroller then sends the Identify command with stack address 6’h2 (i.e., 24’h0000 0011 0010 0100 0010 0110). The stack address is bolded. The last four bits are the corresponding CRC value. The master passes the command onto the stack. The device at stack position 2 responds by setting the stack address bits (ADDR[3:0]) and stack size bits (SIZE[3:0]) in the Comms Setup register to 4’h2 and returns the Identify response with CRC and an address of 6’h32 (i.e., 32’b0000 0011 0010 0111 0010 0000 0000 1111). The address bits are bolded. The address bits contains the normal stack address (2’h0010) and the state of the Comms FN8830.1 June 16, 2016 ISL78610 Select pins (2’b11). Note that the in an Identify response, the data LSBs are always zero. Identify command sent with a nonzero stack address causes a NAK response from the addressed device(s). The host microcontroller then sends the Identify command with stack address 6’h3. Device 3 responds by setting its stack address and stack size information to 4’h3 and returning the Identify response with address 6’h33. Devices 1 and 2 set their stack size information to 4’h3. IDENTIFY TIMING The process continues with the host microcontroller incrementing the stack address until all devices in the stack have received their stack address. Identified devices update their stack size information with each new transmission. The stack top device (identified by the state of the Comms Select pins = 10) loads the stack address and stack size information and returns the Identify response with address 6’h2x, where x corresponds to the stack position of the top device. The host microcontroller recognizes the top stack response and loads the total number of stack devices to local memory. The host microcontroller then sends the Identify command with data set to 6’h3F. Devices exit Identify mode on receipt of this command. The stack top device responds ACK. An example Identify transmit and receive sequence for a stack of 3 devices is shown in Figure 60. When in Normal mode, only the base Identify command is recognized by devices. Any other Identify command variant or an Send Identify Command Send Identify Device 2 Send Identify Device 3 Send Identify Complete To determine the time required to complete an Identify operation, refer to Table 21 on page 51. In the table are two SPI Command columns showing the time required to send the Identify command and receive the response (with an SPI clock of 1MHz.) In the case of the master, there are no daisy chain clocks, so all three bytes of the send and four bytes of the receive are accumulated. For the daisy chain devices, the daisy communication overlaps with two of the SPI send bytes and with three of the SPI receive bytes, so there is no extra time needed for these bits. Once the device receives the Identify command, it adds a Delay time before sending the response back to the master. Then, on receiving the daisy response, the master sends the response to the host through the SPI port. There is a column showing the time for each Identify command and, in the second column from the right, is a column showing the total accumulated time required to send all Identify commands for each of the cell configurations. The final column on the right adds the identify complete timing to the total. The Identify Complete command takes the same number of clock cycles as the last Identify command. Tx 0000 0011 0010 0100 0000 0100 03 24 04 Rx 0000 0011 0011 0000 0000 0000 0000 1100 03 30 00 0C Tx 0000 0011 0010 0100 0010 0110 03 24 26 Rx 0000 0011 0010 0111 0010 0000 0000 1111 03 27 20 0F Tx 0000 0011 0010 0100 0011 0111 03 24 37 Rx 0000 0011 0010 0110 0011 0000 0000 0101 03 26 30 05 Tx 0000 0011 0010 0111 1111 1110 03 27 FE Rx 0011 0011 0011 0000 0000 0000 0000 0001 33 30 00 01 FIGURE 60. IDENTIFY EXAMPLE, STACK OF 3 DEVICES Submit Document Feedback 50 FN8830.1 June 16, 2016 ISL78610 . TABLE 21. IDENTIFY TIMING WITH DAISY CHAIN OPERATING AT 500kHz IDENTIFY IDENTIFY + IDENTIFY TIME FOR DAISY RESPONSE DAISY NUMBER OF SPI COMMAND COMPLETE TIME RECEIVE TIME SPI COMMAND EACH DEVICE TOTAL TIME DELAY TRANSMIT TIME SEND TIME DEVICES (µs) (µs) (µs) (µs) RECEIVE TIME (µs) (µs) (μs) (μs) (2 MINIMUM) 1 (Master) 24 0 0 0 32 56 56 56 2 8 50 18 66 8 150 206 356 3 8 52 18 68 8 154 360 514 4 8 54 18 70 8 158 518 676 5 8 56 18 72 8 162 680 842 6 8 58 18 74 8 166 846 1012 7 8 60 18 76 8 170 1016 1186 8 8 62 18 78 8 174 1190 1364 9 8 64 18 80 8 178 1368 1546 10 8 66 18 82 8 182 1550 1732 11 8 68 18 84 8 186 1736 1922 12 8 70 18 86 8 190 1926 2116 13 8 72 18 88 8 194 2120 2314 14 8 74 18 90 8 198 2318 2516 . TABLE 22. IDENTIFY TIMING WITH DAISY CHAIN OPERATING AT 250kHz IDENTIFY TIME FOR DAISY RESPONSE DAISY NUMBER OF SPI COMMAND RECEIVE TIME SPI COMMAND EACH DEVICE TOTAL TIME IDENTIFY + IDENTIFY DELAY TRANSMIT TIME SEND TIME DEVICES (µs) COMPLETE TIME (µs) (µs) (µs) RECEIVE TIME (µs) (μs) (μs) (µs) (2 MINIMUM) 1 (Master) 24 0 0 0 32 56 56 56 2 8 100 34 132 8 282 338 620 3 8 104 34 136 8 290 628 918 4 8 108 34 140 8 298 926 1224 5 8 112 34 144 8 306 1232 1538 6 8 116 34 148 8 314 1546 1860 7 8 120 34 152 8 322 1868 2190 8 8 124 34 156 8 330 2198 2528 9 8 128 34 160 8 338 2536 2874 10 8 132 34 164 8 346 2882 3228 11 8 136 34 168 8 354 3236 3590 12 8 140 34 172 8 362 3598 3960 13 8 144 34 176 8 370 3968 4338 14 8 148 34 180 8 378 4346 4724 ACK (Acknowledge) Command NAK (Not Acknowledge) Command ACK is used by daisy chain devices to acknowledge receipt of a valid command. ACK is also useful as a communications test command: the stack top device returns ACK in response to successful receipt of the ACK command. No other action is performed in response to an ACK. Receipt of an unrecognized command by either the target device or the top stack device, results in a NAK being returned by that device. If a command addressed to all devices using the Address All stack address 1111 or the identify stack address 0000 is not recognized by any devices, then all devices not recognizing the command respond NAK. In this case, the host microcontroller receives the NAK response from the lowest stack device that failed to recognize the command. An incomplete command (e.g., one that is less than the length required) also causes a NAK to be returned. Submit Document Feedback 51 FN8830.1 June 16, 2016 ISL78610 Communications All communications are conducted through the SPI port in single 8-bit byte increments. The MSB is transmitted first and the LSB is transmitted last. Maximum operating data rates are 2Mbps for the SPI interface. When using the daisy chain communications system it is recommended that the synchronous communications data rate be at least twice that of the daisy chain system. (See Table 4.) In stand-alone applications (non-daisy chain) data is sent without additional address information. This maximizes the throughput for full duplex SPI operation. In daisy chain applications all measurement data is sent with the corresponding device stack address (the position within the daisy chain), parameter identifier and data address. Daisy chain communication throughput is maximized by allowing streamed data (accessed by a “read all data” address). SPI Interface The ISL78610 operates as an SPI slave capable of bus speeds up to 2Mbps. Four lines make up the SPI interface: SCLK, DIN, DOUT and CS. The SPI interface operates in either full duplex or half duplex mode depending on the daisy chain status of the part. HALF DUPLEX (DAISY CHAIN) OPERATION The SPI operates in half duplex mode when configured as a daisy chain application (see Table 3 on page 26). Data flow is controlled by a handshake system using the DATA READY and CS signals. DATA READY is controlled by the ISL78610. CS is controlled by the host microcontroller. This handshake accommodates the delay between command receipt and device response due to the latency of the daisy chain communications system. There is a timeout period associated with the CS inactive (high) condition which resets all the communications counters. This effectively resets the SPI port to a known starting condition. If CS stays high for more than 100µs then the SPI state machine resets. Responses from stack devices are received by the stack master (stack bottom device). The stack master then asserts its DATA READY output once the first full data byte is available. The host microcontroller responds by asserting CS and clocking the data out of the DOUT port. The DATA READY line is then cleared and DOUT is tri-stated in response to CS being taken high. In this mode the DIN and DOUT lines may be connected externally. Half duplex communications are conducted using the DATA READY/CS handshake as follows: The DOUT line is normally tri-stated (high impedance) to allow use in a multidrop bus. DOUT is only active when CS is low. 1. The host microcontroller sends a command to the ISL78610 using the CS line to select the ISL78610 and clocking data into the ISL78610 DIN pin. An additional output DATA READY is used in the daisy chain configuration to notify the host microcontroller that responses have been received from a device in the chain. 2. The ISL78610 asserts DATA READY low when it is ready to send data to the host microcontroller. When DATA READY is low, the ISL78610 is in transmit mode and will ignore any data on DIN. FULL DUPLEX (STAND-ALONE) SPI OPERATION In non-daisy chain applications, the SPI bus operates as a standard, full duplex, SPI port. Read and write commands are sent to the ISL78610 in 8-bit blocks. CS is taken high between each block. Data flow is controlled by interpreting the first bit of each transaction and counting the requisite number of bytes. It is the responsibility of the host microcontroller to ensure that commands are correctly formulated, as an incorrect formulation, (e.g., read bit instead of write bit), would cause the port to lose synchronization. There is a timeout period associated with the CS inactive (high) condition, which resets all the communications counters. This effectively resets the SPI port to a known starting condition. If CS stays high for more than 100µs then the SPI state machine resets. A pending device response from a previous command is sent by the ISL78610 during the first 2 bytes of the 3-byte Write transaction. The third byte from the ISL78610 is then discarded by the host microcontroller. This maintains sequencing during 3-byte (Write) transactions. Interface timing for full duplex SPI transfers are shown in Figure 3 on page 14. 3. The host microcontroller asserts CS low and clocks 8 bits of data out of DOUT using SCLK. 4. The host microcontroller then raises CS. The ISL78610 responds by raising DATA READY and tri-stating DOUT. 5. The ISL78610 reasserts DATA READY for the next byte, and so on. The host microcontroller must service the ISL78610 if DATA READY is low before sending further commands. Any data sent to DIN while DATA READY is low is ignored by the ISL78610. A 4-byte data buffer is provided for SPI communications. This accommodates all single transaction responses. Multiple responses, such as those that may be produced by a device detecting an error, would overflow this buffer. It is important therefore that the host microcontroller reads the first byte of data before a fifth byte arrives on the master device’s daisy chain port so as not to risk losing data. The DATA READY output from the ISL78610 is not asserted if CS is already asserted. It is possible for the microcontroller to interrupt a sequential data transfer by asserting CS before the ISL78610 asserts DATA READY. This causes a conflict with the communications and is not recommended. A conflict created in this manner would be recognized by the microcontroller either not receiving the expected response or receiving a communications failure notification. Interface timing for half duplex SPI transfers are shown in Figure 4 on page 14. Submit Document Feedback 52 FN8830.1 June 16, 2016 ISL78610 Non-Daisy Chain Communications Action commands, such as scan and communications administration operations are treated as reads. In non-daisy chain (Stand-Alone) systems, all communications sent from the master are 2 or 3 bytes in length. Data read and action commands are 2 bytes. Data writes are 3 bytes. Device responses are 2 bytes in length and contain data only. Non-daisy chain devices do not generate a response to write or system level commands. Data integrity may be verified by reading register contents after writing. The ISL78610 does nothing in response to a write or administration command that is not recognized. An unrecognized read command returns 16’h0000. An incomplete command, such as may occur if communications are interrupted, is registered as an unrecognized command either when CS is taken high or after a timeout period. The communications interface is reset after the timeout period. Write commands in non-daisy chain systems are composed of a read/write bit, page address (3 bits), data address (6 bits) and data (14 bits) - three bytes. Read commands in non-daisy chain systems are composed of a read/write bit, page address (3 bits), data address (6 bits), fill (6 bits) and 16 bits of returned data (ignore the first most significant bits of data returned) - four bytes. Non-daisy chain communications are conducted without CRC (Cyclical Redundancy Check) error detection. The following commands have no meaning in non-daisy chain systems: Identify, ACK, NAK. The ISL78610 responds to read commands by loading the requested data to its output buffer. The output buffer contents are then loaded to the shift register when CS goes low and are shifted out on the DOUT line on the falling edges of SCLK. This sequence continues until all the requested data has been sent. The rules for non-daisy chain installations are shown in Table 23. Examples of full duplex SPI read and write sequences are shown in Figures 61, 62 and 63. An example Device Read (cell 7), with response, is shown in Figure 63. Commands and data are memory mapped to 14-bit data locations. The memory map is arranged in pages. Pages 1 and 2 are used for volatile data. Page 3 contains the action and communications administration commands. Page 4 accesses nonvolatile memory. Page 5 is used for factory test. TABLE 23. ISL78610 DATA INTERPRETATION RULES FOR NON-DAISY CHAIN INSTALLATIONS FIRST BIT IN SEQUENCE PAGE ADDR DATA ADDRESS 0 011 001000 Measure command. Last six bits of transmission contain element address. 0 Any All other Device read or action command. Last six bits of transmission are zero. 1 Any Any INTERPRETATION Device write command. CS 30µs max 30µs max 30µs max SCLK DOUT Note 15 Note 15 HIGH IMPEDANCE MSB DIN 1 R W 0 1 PAGE ADDR 1 0 0 0 0 DATA ADDRESS 1 0 0 0 0 0 0 0 NOT DETERMINED ACTIVE FILL WITH 0 FIGURE 61. SPI FULL DUPLEX (STAND-ALONE) MEASURE COMMAND EXAMPLE: EXT4 VOLTAGE Submit Document Feedback 53 FN8830.1 June 16, 2016 ISL78610 CS 30µs max 30µs max 30µs max SCLK DOUT Note 15 Note 15 Note 16 LSB MSB DIN 1 0 R W NOTES: 1 0 0 1 PAGE ADDR 0 0 0 1 0 DATA ADDRESS 0 1 1 1 0 0 1 1 0 0 1 1 0 HIGH IMPEDANCE CELL UNDERVOLTAGE THRESHOLD DATA NOT DETERMINED 15. Last data byte pair from previous command. ACTIVE 16. Not defined. FIGURE 62. SPI FULL DUPLEX (STAND-ALONE) WRITE COMMAND EXAMPLE: WRITE UNDERVOLTAGE THRESHOLD DATA CS 30µs max 30µs max 30µs max 30µs max SCLK Note 17 DOUT Note 17 0 0 0 1 0 1 1 1 LEADING ZEROS MSB 0 0 0 1 R W NOTES: 0 0 0 1 PAGE ADDR 1 1 0 0 0 0 0 0 1 0 1 0 CELL7 DATA RESPONSE COMMAND DIN 0 0 0 0 Note 18 Note 18 DATA ADDRESS HIGH IMPEDANCE 17. Last data byte pair from previous command. NOT DETERMINED 18. Next command (or 8’h00 if no command). ACTIVE 19. Host should start to clock data out within 30µs of CS going low. FIGURE 63. SPI FULL DUPLEX (STAND-ALONE) READ COMMAND EXAMPLE: READ CELL 7 DATA Submit Document Feedback 54 FN8830.1 June 16, 2016 ISL78610 Daisy Chain Communications Examples of the various command structures for non-daisy chain installations are shown in Figures 64A through 64E. Commands in daisy chain systems are transmitted and received via the SPI port and are composed of a device address (4 bits), a read/write bit, page address (3 bits), data address (6 bits), data (6 bits) and CRC (4 bits). R/W EXAMPLE NON-DAISY COMMUNICATIONS DATA ADDRESS (11, 6) PAGE (14, 12) 0 0 1 MSB 1 0 0 1 0 1 TRAILING ZEROS (5, 0) 0 0 BYTE 1 0 0 0 0 BYTE 0 Device commands and data are memory mapped to 14-bit data locations. The memory map is arranged in pages. Pages 1 and 2 are used for volatile data. Page 3 contains the action and communications administration commands. Page 4 accesses nonvolatile memory. Page 5 is used for factory test. 0 LSB R/W FIGURE 64A. DEVICE LEVEL COMMAND: SLEEP 0 DATA ADDRESS (11, 6) PAGE (14, 12) 0 1 MSB 1 0 0 1 1 1 The daisy chain communication is intended for use with large stacks of battery cells where a number of ISL78610 devices are used. TRAILING ZEROS (5, 0) 1 0 BYTE 1 0 0 0 Communications Protocol 0 BYTE 0 All daisy chain communications are passed from device to device such that all devices in the stack receive the same information. Each device then decodes the message and responds as needed. The originating device (master in the case of commands, addressed device or top stack device in the case of responses) generates the system clock and data stream. Each device delays the data stream by one clock cycle. Each device knows its stack location (see the Identify command on page 49). Each device knows the total number of devices in the stack. Each originating device adds a number of clock pulses to the daisy chain data stream to allow transmission through the stack. 0 LSB R/W FIGURE 64B. DEVICE LEVEL COMMAND: WAKE-UP 0 DATA ADDRESS (11, 6) PAGE (14, 12) 0 1 MSB 1 0 0 0 0 0 TRAILING ZEROS (5, 0) 1 0 BYTE 1 0 0 0 0 BYTE 0 0 LSB All communications from the host microcontroller are passed from device to device to the last device in the chain (top device). The top device responds to read and write messages with an “ACK” (or with the requested data if this is the addressed device and the message was a read command). The addressed device then waits to receive the “ACK” before responding, either with data, in the case of a read, or with an “ACK” in the case of a write. Action commands such as the Scan commands do not require a response. R/W FIGURE 64C. DEVICE LEVEL COMMAND: SCAN VOLTAGES 0 DATA ADDRESS (11, 6) PAGE (14, 12) 0 1 MSB 1 0 0 1 0 0 BYTE 1 ELEMENT ADDRESS (5, 0) 0 0 0 0 BYTE 0 1 0 1 LSB R/W FIGURE 64D. DEVICE LEVEL COMMAND: MEASURE CELL 5 VOLTAGE PAGE (22, 20) DATA ADDRESS (19, 14) DATA (13, 0) 1 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 MSB BYTE 2 BYTE 1 BYTE 0 FIGURE 64E. DEVICE WRITE: WRITE EXTERNAL TEMPERATURE LIMIT = 14’h0FFF FIGURE 64. NON-DAISY CHAIN DEVICE COMMAND AND WRITE EXAMPLES LSB A read or write communications transmission is only considered to be complete following receipt of a response from the target device or the identification of a communications fault condition. The host microcontroller should not transmit further data until either a response has been received from the target stack device or a communications fault condition has been identified. A normal daisy chain communications sequence for a stack of 10 devices: read device 4, cell 7 data, is illustrated in Figure 65 on page 56. The maximum response time: time from the rising edge of CS at the end of the first byte of a read/write command, sent by the host microcontroller, to the assertion of DATA READY by the master device, is given in Table 24 for various daisy chain data rates. TABLE 24. MAXIMUM RESPONSE TIMES FOR DAISY CHAIN READ AND WRITE COMMANDS. STACK OF 10 DEVICES MAXIMUM TIME TO ASSERTION OF DATA READY Submit Document Feedback 55 DAISY CHAIN DATA RATE (kHz) 500 250 125 62.5 UNIT Response time 240 480 960 1920 µs FN8830.1 June 16, 2016 ISL78610 SCLK DIN SPI A A A DOUT B B B B CS DATA READY 10 EXTRA CLOCKS PACKET A MASTER Tx MASTER Rx PACKET B 4 EXTRA CLOCKS 4 DAISY CLOCK PULSES DAISY CHAIN DEVICE 4 Tx PACKET B 6 EXTRA CLOCKS ACK PACKET A DEVICE 4 Rx ACK DEVICE 10 Tx DEVICE 10 Rx PACKET A NO EXTRA CLOCKS 10 EXTRA CLOCKS 5 EXTRA CLOCKS NO EXTRA CLOCKS 10 DAISY CLOCK PULSES • Host microcontroller sends “Read device 4, cell 7” = Packet A • Master begins relaying Packet A following receipt of the first byte of A. Master adds 10 extra clock cycles to allow all stack devices to relay the message. • Device 4 receives and decodes “Read device 4, cell 7” and waits for a response from top stack device. • Top of stack (device 10) receives and decodes Packet A. • Device 10 responds “ACK”. Device 10 adds 10 clock cycles to allow all stack devices to relay the message. • Device 4 receives and decodes ACK. • Device 4 transmits the cell 7 data = Packet B. Device 4 subtracts one clock cycle to synchronize timing for lower stack devices to relay the message. • Master asserts DATA READY after receiving the first byte of Packet B. • Host responds by asserting CS and clocking out 8 bits of data from DOUT. CS is taken high following the 8th bit. The master responds by taking DATA READY high and tri-stating DOUT. Master asserts DATA READY after receiving the next byte and so on. FIGURE 65. DAISY CHAIN READ EXAMPLE “READ DEVICE 4, CELL 7”. STACK OF 10 DEVICES TABLE 25. ISL78610 DATA INTERPRETATION RULES FOR DAISY CHAIN INSTALLATIONS 5TH BIT (R/W) PAGE DATA ADDRESS Stack address [3:0] (nonzero) 0 011 001000 Measure command. Data address is followed by 6-bit element address. 0000 0 011 001001 Identify command. Data address is followed by device count data. Stack address [3:0] (nonzero) 0 Any All other Device Read command. Data address is followed by 6 zeros. Stack address [3:0] (nonzero) 1 Any Any FIRST 4 BITS IN SEQUENCE Communication Sequences All daisy chain device responses are 4-byte sequences, except for the responses to the Read All command. All responses start with the device stack address. All responses use a 4-bit CRC. The response to the “Read All Commands” is to send a normal 4-byte data response for the first data segment and continue sending the remaining data segments in 3-byte sections composed of data address, data and CRC. This creates an anomaly with the normal CRC usage in that the first 4 bytes have a 4-bit CRC at the end (operating on 3.5 bytes of data) while the remaining bytes have a CRC which only operates on 2.5 bytes. The host microcontroller, having requested the data, must be prepared for this. Daisy chain devices require device stack address information to be added to the basic command set. Daisy chain writes are Submit Document Feedback 56 INTERPRETATION Device Write command. 4-byte sequences. Daisy chain reads are 3 bytes. Action commands, such as scan and communications administration commands are treated as reads. Daisy chain communications employ a 4-bit CRC (Cyclic Redundancy Check) using a polynomial of the form 1 + X + X4. The first four bits of each daisy chain transmission contain the stack address, which can be any number from 0001 to 1110. All devices respond to the Address All (1111) and Identify (0000) stack addresses. The fifth bit is set to ‘1’ for write and ‘0’ for read. The rules for daisy chain installations are shown in Table 25. CRC Calculation Daisy chain communications employ a 4-bit CRC using a polynomial of the form 1 + X + X4. The polynomial is implemented as a 4-stage internal XOR standard linear feedback FN8830.1 June 16, 2016 ISL78610 shift register as shown in Figure 66. The CRC value is calculated using the base command data only. The CRC value is not included in the calculation. The host microcontroller calculates the CRC when sending commands or writing data. The calculation is repeated in the ISL78610 and checked for compliance. The ISL78610 calculates the CRC when responding with data (device reads). The host microcontroller then repeats the calculation and checks for compliance. DIN + + FF0 FF1 FF2 FF3 FIGURE 66. 4-BIT CRC CALCULATION Attribute VB_Name = "isl78610evb_crc4_lib" ' File - isl78610evb_crc4_lib.bas ' Copyright (c) 2010 Intersil ' ----------------------------------------------------------------------------Option Explicit '*********************************************************** ' CRC4 Routines '*********************************************************** Public Function CheckCRC4(myArray() As Byte) As Boolean 'returns True if CRC4 checksum (low nibble of last byte in myarray) 'is good. Array can be any length Dim crc4 As Byte Dim lastnibble As Byte lastnibble = myArray(UBound(myArray)) And &HF crc4 = CalculateCRC4(myArray) 'initialize bits bit0 = False bit1 = False bit2 = False bit3 = False 'simple implementation of CRC4 (using polynomial 1 + X + X^4) For i = LBound(arraycopy) To UBound(arraycopy) 'last nibble is ignored for CRC4 calculations If i = UBound(arraycopy) Then k=4 Else k=8 End If For j = 1 To k 'shift left one bit carry = (arraycopy(i) And &H80) > 0 arraycopy(i) = (arraycopy(i) And &H7F) * 2 If lastnibble = crc4 Then CheckCRC4 = True Else CheckCRC4 = False End If End Function Public Sub AddCRC4(myArray() As Byte) 'adds CRC4 checksum (low nibble in last byte in array) 'array can be any length Dim crc4 As Byte crc4 = CalculateCRC4(myArray) myArray(UBound(myArray)) = (myArray(UBound(myArray)) And &HF0) Or crc4 End Sub Public Function CalculateCRC4(ByRef myArray() As Byte) As Byte 'calculates/returns the CRC4 checksum of array contents excluding 'last low nibble. Array can be any length Dim size As Integer Dim i As Integer Dim j As Integer Dim k As Integer Dim bit0 As Boolean, bit1 As Boolean, bit2 As Boolean, bit3 As Boolean Dim ff0 As Boolean, ff1 As Boolean, ff2 As Boolean, ff3 As Boolean Dim carry As Boolean Dim arraycopy() As Byte Dim result As Byte 'copy data so we do not clobber source array ReDim arraycopy(LBound(myArray) To UBound(myArray)) As Byte For i = LBound(myArray) To UBound(myArray) arraycopy(i) = myArray(i) Next 'see ISL78610 datasheet, Fig 11: 4-bit CRC calculation ff0 = carry Xor bit3 ff1 = bit0 Xor bit3 ff2 = bit1 ff3 = bit2 bit0 = ff0 bit1 = ff1 bit2 = ff2 bit3 = ff3 Next j Next i 'combine bits to obtain CRC4 result result = 0 If bit0 Then result = result + 1 End If If bit1 Then result = result + 2 End If If bit2 Then result = result + 4 End If If bit3 Then result = result + 8 End If CalculateCRC4 = result End Function FIGURE 67. EXAMPLE CRC CALCULATION ROUTINE (VISUAL BASIC) Submit Document Feedback 57 FN8830.1 June 16, 2016 ISL78610 Daisy Chain Addressing The state of the COMMS SELECT 1, COMMS SELECT 2, COMMS RATE 0, and COMMS RATE 1 pins can be checked by reading the CSEL[2:1] and CRAT[1:0] bits in the Comms Setup register, (see Table 26). The SIZE[3:0] bits show the number of devices in the daisy chain and the ADDR[3:0] bits indicate the location of a device within the daisy chain. When used in a daisy chain system each individual device dynamically assigns itself a unique address (see “Identify Command” on page 49). In addition, all daisy chain devices respond to a common address allowing them to be controlled simultaneously (e.g., when using the Scan Voltages and Balance Enable commands). See “Communication Timing” on page 60. Examples of the various read and write command structures for daisy chain installations are shown in Figures 69C to 69G. The MSB is transmitted first and the LSB is transmitted last. TABLE 26. COMMS SETUP REGISTER (ADDRESS 6’h18) 11 10 9 8 7 6 5 4 3 2 1 0 CRAT1 CRAT0 CSEL2 CSEL1 SIZE3 SIZE2 SIZE1 SIZE0 ADDR3 ADDR2 ADDR1 ADDR0 These bits show the status of the COMMS RATE 1 and COMMS RATE 0 pins These bits show the daisy chain stack size (i.e., the total number of stacked devices) These bits show the status of the COMMS SEL 2 and COMMS SEL 1 pins These bits show this devices position within the daisy chain stack CS 30µs max 30µs max 30µs max 30µs max SCLK DOUT TRI-STATE COMMAND DIN 0 0 0 1 DEVICE ADDR 1 0 1 0 1 0 0 1 R /W PAGE ADDR 0 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 DATA TO WRITE DATA ADDRESS CRC DEVICE ADDRESS (23, 20) 1 1 1 MSB 1 R/W FIGURE 68. SPI HALF DUPLEX (DAISY CHAIN) WRITE REGISTER COMMAND EXAMPLE: WRITE DEVICE 1, DEVICE SETUP REGISTER 0 DATA ADDRESS (15, 10) PAGE (18, 16) 0 1 1 0 0 1 BYTE 2 0 1 CRC (3, 0) ZERO (9, 4) 0 0 0 0 0 0 BYTE 1 0 1 1 1 0 LSB BYTE 0 DEVICE ADDRESS (23, 20) 1 MSB 1 1 1 R/W FIGURE 69A. DEVICE LEVEL COMMAND: SLEEP 0 BYTE 2 DATA ADDRESS (15, 10) PAGE (18, 16) 0 1 1 0 0 1 1 1 BYTE 1 ZERO (9, 4) 1 0 0 0 0 CRC (3, 0) 0 0 0 BYTE 0 1 1 1 LSB FIGURE 69B. DEVICE LEVEL COMMAND: WAKE-UP Submit Document Feedback 58 FN8830.1 June 16, 2016 ISL78610 1 0 0 MSB R/W DEVICE ADDRESS (23, 20) 1 0 DATA ADDRESS (15, 10) PAGE (18, 16) 0 1 1 0 0 0 BYTE 2 0 ZERO (9, 4) 0 1 0 0 0 0 CRC (3, 0) 0 0 1 1 1 LSB BYTE 0 BYTE 1 1 FIGURE 69C. DEVICE LEVEL COMMAND: DEVICE 9, SCAN VOLTAGES 1 0 0 MSB R/W DEVICE ADDRESS (23, 20) 1 0 DATA ADDRESS (15, 10) PAGE (18, 16) 0 0 1 0 0 0 BYTE 2 1 CRC (3, 0) ZERO (9, 4) 1 1 0 0 0 0 0 BYTE 1 0 1 1 0 0 LSB BYTE 0 FIGURE 69D. DEVICE READ: DEVICE 9, GET CELL 7 DATA 0 1 0 MSB R/W DEVICE ADDRESS (23, 20) 0 0 DATA ADDRESS (15, 10) PAGE (18, 16) 0 1 1 0 0 1 BYTE 2 0 ELEMENT ADDRESS (9, 4) 0 0 0 0 0 1 CRC (3, 0) 0 BYTE 1 1 0 1 0 1 LSB BYTE 0 FIGURE 69E. ELEMENT LEVEL COMMAND: DEVICE 4, MEASURE CELL 5 VOLTAGE 0 0 0 MSB R/W DEVICE ADDRESS (23, 20) 0 0 DATA ADDRESS (15, 10) PAGE (18, 16) 0 1 1 0 0 1 BYTE 2 0 DEVICE COUNT (9, 4) 0 1 0 0 0 0 CRC (3, 0) 0 BYTE 1 0 0 1 0 0 LSB BYTE 0 DEVICE ADDRESS (31, 28) 0 1 1 MSB 1 R/W FIGURE 69F. IDENTIFY COMMAND 1 BYTE 3 DATA ADDRESS (23, 18) PAGE (26, 24) 0 1 0 0 1 0 0 DATA (17, 4) 1 BYTE 2 0 0 0 1 1 1 1 1 1 CRC (3, 0) 1 1 1 BYTE 1 1 1 1 1 BYTE 0 0 0 0 LSB FIGURE 69G. DEVICE WRITE: DEVICE 7, WRITE EXTERNAL TEMPERATURE LIMIT = 14’h0FFF FIGURE 69. DAISY CHAIN DEVICE READ AND WRITE EXAMPLES Submit Document Feedback 59 FN8830.1 June 16, 2016 ISL78610 Response examples are shown in Figures 70A to 70D. 1 0 0 R/W DEVICE ADDRESS (31, 28) 1 MSB 0 DATA ADDRESS (23, 18) PAGE (26, 24) 0 0 1 0 0 0 BYTE 3 1 CRC (3, 0) DATA (17, 4) 1 1 0 1 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 LSB BYTE 0 BYTE 1 BYTE 2 0 FIGURE 70A. DEVICE DATA RESPONSE: DEVICE 9, CELL 7 VOLTAGE = 14’h170A (3.6V) 1 0 1 R/W DEVICE ADDRESS (31, 28) 0 MSB 0 DATA ADDRESS (23, 18) PAGE (26, 24) 0 1 1 0 0 1 BYTE 3 1 ZEROS (17, 4) 0 0 0 0 0 0 0 BYTE 2 0 0 0 CRC (3, 0) 0 0 0 0 0 0 0 1 0 LSB BYTE 0 BYTE 1 0 DEVICE ADDRESS (31, 28) 0 0 0 0 MSB R/W FIGURE 70B. DEVICE COMMUNICATIONS ADMINISTRATION RESPONSE: DEVICE 10, ACK 0 DATA ADDRESS (23, 18) PAGE (26, 24) 0 1 1 0 0 1 BYTE 3 0 DEVICE TYPE/ ADDRESS (17, 4) 0 1 0 0 0 0 BYTE 2 0 0 0 0 1 CRC (3, 0) 1 BYTE 1 0 1 0 0 0 1 BYTE 0 1 0 LSB DEVICE ADDRESS (319, 316) R/W FIGURE 70C. DEVICE COMMUNICATIONS ADMINISTRATION RESPONSE: IDENTIFY, DEVICE 4, MIDDLE STACK DEVICE PAGE (314, 312) CELL 12 DATA (305, 292) DATA ADDRESS 0CH (311, 306) CRC (291,288) 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 0 MSB BYTE 39 BYTE 38 DATA ADDRESS 0AH (263, 258) BYTE 37 CELL 10 DATA (257, 244) BYTE 36 CRC (243, 240) 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1 BYTE 32 BYTE 31 BYTE 30 DATA ADDRESS 0BH (287, 282) CELL 11 DATA (281, 268) CRC (287, 264) 0 0 1 0 1 1 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 BYTE 35 DATA ADDRESS 00H (23, 18) BYTE 34 PACK VOLTAGE DATA (17, 4) BYTE 33 CRC (3, 0) 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1 BYTE 2 BYTE 1 BYTE 0 LSB FIGURE 70D. DEVICE DATA RESPONSE: DEVICE 9, READ ALL CELL VOLTAGE DATA FIGURE 70. DAISY CHAIN DEVICE RESPONSE EXAMPLES Communication Timing Collecting voltage and temperature data from daisy chained ISL78610 devices consists of three separate types of operations: A command to initiate measurement, the measurement itself, and a command and response to retrieve data. Commands are the same for all types of operations, but the timing is dependent on the number of devices in the stack, the daisy chain clock rate, and the SPI clock rate. Submit Document Feedback 60 Actual measurement operations occur within the device and start with the last bit of the command byte and end with data being placed in a register. Measurement times are dependent on the ISL78610 internal clock. This clock has the same variations (and is related to) the daisy chain clock. Responses have different timing calculations, based on the position of the addressed device in the daisy chain stack and the daisy chain and SPI clock rates. FN8830.1 June 16, 2016 ISL78610 Measurement Timing Diagrams All measurement timing is derived from the ISL78610’s internal oscillators. Figures given in the following as typical are those obtained with the oscillators operating at their nominal frequencies and with any synchronization timing also at nominal value. Maximum figures are those obtained with the oscillators operating at their minimum frequencies and with the maximum time for any synchronization timing. Measurement timing begins with a Start Scan signal. This signal is generated internally by the ISL78610 at the last clock falling edge of the Scan or Measure command. (This is the last falling edge of the SPI clock in the case of a stand-alone or master device, or the last falling edge of the daisy chain clock, in the case of a daisy chain device.) Daisy chain middle or top devices impose additional synchronization delays. Communications sent on the SPI port are passed on to the master device’s daisy chain port at the end of the first byte of data. Then, for each device, there is an additional delay of one daisy chain clock cycle. On receiving the Start Scan signal, the device initializes measurement circuits and proceeds to perform the requested measurement(s). Once the measurements are made, some devices perform additional operations, such as checking for overvoltage conditions. The measurement command ends when registers are updated. At this time the registers may be read using a separate command. A detailed timing breakdown is provided for each measurement type below. See Figure 71 for the measurement timing for a Stand-Alone device. See Figure 72 for the measurement timing for daisy chain devices. Tables 30 through 35 give the typical and maximum timing for the critical elements of measurement process. Each table shows the timing from the last edge of the Scan command clock. SCAN COMMAND READ REGISTER COMMAND DIN SCK DOUT DIN INTERNAL SCAN MEASURE INTERNAL OPERATION UPDATE REGISTERS See Tables 30 through 35 FIGURE 71. SCAN/MEASURE COMMAND TIMING WITH RESPONSE (STAND-ALONE) SPI SCAN COMMAND DIN SCK SCAN/MEASURE INTERNAL OPERATION (MASTER) UPDATE REGISTERS See Tables 30 through 35 See Figure 73 on page 62, Table 27 and Table 28 on page 66 DAISY CHAIN SCAN COMMAND UNIT 2 UNIT 6 4 DAISY CHAIN CLOCKS SCAN/MEASURE INTERNAL OPERATION (DAISY CHAIN UNIT 6) UPDATE REGISTERS See Tables 30 through 35 FIGURE 72. MEASUREMENT TIMING (6 DEVICE DAISY CHAIN) Submit Document Feedback 61 FN8830.1 June 16, 2016 ISL78610 Command Timing Diagram SPI COMMAND DOUT tCS:WAIT CS MASTER SCK tLEAD tLAG tSPI tD t1A DAISY CLOCK (P2 TRANSMIT) 8* tD 8* tD 8* tD DEVICE 2 2 * tD (P1 RECEIVE) 8* tD 8* tD 8* tD 8* tD 8* tD 12 * tD SCAN 2µs 2 * tD 4 * tD DEVICE 6 12 * tD (Note 20) (Note 21) 8* tD (P1 RECEIVE) (FROM DEVICE 5) 8* tD 8* tD 8* tD 8 * tD SCAN 2µs 2 * tD DEVICE 14 8 * tD (P1 RECEIVE) (FROM DEVICE 13) 8* tD 8* tD 8* tD 8* tD SCAN 2µs 2 * tD t1B t1C To Start of Scan (master) COMMANDS: t1A = t SPI 8 + t LEAD + t LAG 3 + 2 t CSWAIT • • • • • • • • • • • To Start of Scan (top/middle) t1B = t SPI 8 + t LEAD + t LAG + t D 28 + n – 2 + 2s To End of command t1C = t SPI 8 + t LEAD + t LAG + t D 34 + N – 2 Where: tSPI = SPI clock period tD = Daisy chain clock period tCS:WAIT = CS High time tLEAD = CS Low to first SPI Clock tLAG = Last SPI Clock CS High n = stack position of target device N = stack position of TOP device Scan Voltages Scan Temperatures Scan Mixed Scan Wires Scan All Measure Read Write Scan Continuous Scan Inhibit Sleep NOTES: 20. Master adds extra byte of zeros as part of daisy protocol. 21. Master adds N-2 clocks to allow communication to the end of the chain. FIGURE 73. COMMAND TIMING Submit Document Feedback 62 FN8830.1 June 16, 2016 ISL78610 Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in Figures 74, 75, and 76. DIN CS MASTER SCK tCS 2µs DEVICE 2 (P2 RECEIVE) DEVICE 6 tLAG tLEAD DATA READY (P1 TRANSMIT) tDR:WAIT 8* tD 2µs 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 4 * tD 8* tD (P1 TRANSMIT) 2*tD DEVICE 14 tDR:SP 8 * tD 8* tD 8* tD 8* tD 8* tD 4*tD 8 * tD 8* tD (P1 TRANSMIT) 8* tD 8* tD 12 * tD DAISY CHAIN ACK RESPONSE 2µs t2 t2 = 8 t SPI + t DRSP + t DRWAIT + t CS + t LEAD + t LAG D – t DRSP + t D 42 + N – 2 + 8 + 4s Where: tSPI = SPI clock period tD = Daisy chain clock period tCS = Host delay from DATA READY Low to the CS Low tDRSP = CS High to DATA READY High tDRWAIT = DATA READY High time tLEAD = CS Low to first SPI Clock tLAG = Last SPI clock CS High N = Stack position of top device D = Number of data bytes D = 4 for one register read (or ACK/NAK response) D = 40 for read all voltages D = 22 for read all temperatures D = 22 for read all faults D = 43 for read all setup FIGURE 74. RESPONSE TIMING (MASTER DEVICE) Submit Document Feedback 63 FN8830.1 June 16, 2016 ISL78610 Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in Figures 74, 75, and 76. (Continued) tCS DIN CS MASTER tLEAD tLAG SCK tDR:SP DATA READY 2µs DEVICE 2 (P2 RECEIVE) (P1 TRANSMIT) 2µs 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 4* tD DEVICE 6 (P1 TRANSMIT) 8* tD n 8* tD (P2 RECEIVE) (FROM DEVICE 7) 8* tD DEVICE 14 2*tD N (P1 TRANSMIT) 8* tD 8* tD 8* tD 4*tD Note 22 DAISY CHAIN READ DATA RESPONSE 8* tD 7*tD (= N - n - 1) 8* tD 8 * tD 8* tD 2µs 8* tD 8* tD 8* tD 8* tD 7* tD DAISY CHAIN ACK RESPONSE Note 23 2µs COMMAND RESPONSE t3 t4 t3 = t D 50 + N – n – 1 + 4s t4 = t SPI 8 + t CS + t LEAD + t LAG + t DRSP + t D D 8 + n – 2 + 2s Where: tD = Daisy chain clock period tSPI = SPI Clock Period N = Stack position of top device n = Stack position of middle stack device tCS = Delay imposed by host from DATA READY to the first SPI clock cycle D = Number of bytes in the middle stack device response e.g. read all cell data = 40 bytes, Register or ACK response = 4 bytes. NOTES: 22. Top device adds (N - n - 1) daisy clocks to allow communications to the targeted middle stack device. 23. Middle stack device adds (n - 2) daisy clocks to allow communications to the master device. FIGURE 75. RESPONSE TIMING (MIDDLE STACK DEVICE) Submit Document Feedback 64 FN8830.1 June 16, 2016 ISL78610 Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in Figures 74, 75, and 76. (Continued) tCS DIN CS MASTER tLEAD tDR:SP DATA READY 2µs DEVICE 6 DEVICE 2 (P2 RECEIVE) (P1 TRANSMIT) 2µs 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 8* tD 4 * tD 8* tD (P1 TRANSMIT) 2*tD DEVICE 14 tLAG SCK 8 * tD 8* tD 8* tD 8* tD 8* tD 4*tD 8 * tD 8* tD (P1 TRANSMIT) 8* tD 8* tD 12 * tD DAISY CHAIN DATA RESPONSE 2µs t5 t5 = t SPI 8 + t LEAD + t LAG + t DRSP + t CS + t D D 8 + 10 + N – 2 + 4s Where: tSPI = SPI clock period tD = Daisy chain clock period tCS = Host delay from DATA READY to the first SPI clock tDRSP = CS High to DATA READY High tLEAD = CS Low to first SPI Clock tLAG = Last SPI Clock CS High N = Stack position of top device D = Number of bytes in response FIGURE 76. RESPONSE TIMING (TOP DEVICE) Submit Document Feedback 65 FN8830.1 June 16, 2016 ISL78610 System Timing Tables TABLE 28. COMMAND TIMING TIME TO END OF COMMAND FOR NUMBER OF DEVICES (µs) Command Timing Tables The command timing (Table 27) includes the time from the start of the command to the start of an internal operation for each device in a stack. Table 28 shows the time required for the command to complete. For a stand-alone device, the two values are the same since the internal operation starts at the end of the command. For a daisy chain operation, the internal operation begins before the end of the command. SPI CLOCK = 2MHz NUMBER OF DEVICES DAISY CLOCK = 500kHz DAISY CLOCK = 250kHz 1 17.5 17.5 2 82.0 157.6 3 84.2 162.0 When calculating overall timing for a command, start with the time from start of the command to the start of the internal operation for the target device. Add to this the time for the internal operation, see “Measurement Timing Tables” on page 67. Add to this the time it takes to read back the data. See times shown in “Response Timing Tables” on page 68. Also needed is a wait time between sending each command (see Table 29). 4 86.5 166.5 5 88.7 170.9 6 90.9 175.3 7 93.1 179.8 8 95.3 184.2 9 97.6 188.7 When using the Address All option, the command timing for the top device in the stack determines when the command ends, but use the Time to Start of Scan for each device to determine when that device begins its internal operation. For example, in a stack of six devices, it takes 90.9µs for the command to complete, but internal operations start at 13.8µs for the master, 68.7µs for device 2, 70.9µs for device 3, etc. 10 99.8 193.1 11 102.0 197.6 12 104.2 202.0 13 106.5 206.5 14 108.7 210.9 In Tables 27 and 28, the calculation assumes a daisy chain (and internal) clock that is 10% slower than the nominal and an SPI clock that is running at the nominal speed (since the SPI clock is normally crystal controlled.) For the 500kHz daisy setting, timing assumes a 450kHz clock. TABLE 27. TIME TO START OF INTERNAL OPERATION TIME TO START OF INTERNAL OPERATION FOR TARGET DEVICE (µs) SPI CLOCK = 2MHz TARGET DEVICE DAISY CLOCK = 500kHz DAISY CLOCK = 250kHz 1 17.5 17.5 2 68.7 130.9 3 70.9 135.4 4 73.2 139.8 5 75.4 144.3 6 77.6 148.7 7 79.8 153.2 8 82.1 157.6 9 84.3 162.1 10 86.5 166.5 11 88.7 170.9 12 90.9 175.4 13 93.2 179.8 14 95.4 184.3 Submit Document Feedback 66 SEQUENTIAL DAISY CHAIN COMMUNICATIONS When sending a sequence of commands to the master device, the host must allow time after each response and before sending the next command, for the daisy chain ports of all stack devices (other than the master) to switch to receive mode. This wait time is equal to 8 daisy chain clock cycles and is imposed from the time of the last edge on the master’s input daisy chain port to the last edge of the first byte of the subsequent command on the SPI, (see Figure 77). The minimum recommended wait time between the host receiving the last edge of a response and sending the first edge of the next command, is given for the various daisy chain data rates in Table 29. TABLE 29. MINIMUM RECOMMENDED COMMUNICATIONS WAIT TIME MAXIMUM TIME FOR DAISY CHAIN PORTS TO CLEAR UNIT DAISY CHAIN DATA RATE 500 250 125 62.5 kHz Communications Wait Time 18 36 72 144 µs FN8830.1 June 16, 2016 ISL78610 SPI COMMAND NEXT SPI COMMAND SPI RESPONSE DIN SCK DATA READY Minimum Wait time between commands. See Table 29 UNIT 2 UNIT n FIGURE 77. MINIMUM WAIT BETWEEN COMMANDS (DAISY CHAIN RESPONSE - TOP DEVICE) Measurement Timing Tables SCAN TEMPERATURES SCAN VOLTAGES The Scan Voltages command initiates a sequence of measurements starting with a scan of each cell input from cell 12 to cell 1, followed by a measurement of pack voltage. Additional measurements are then performed for the internal temperature and to check the connection integrity test of the VSS and VBAT inputs. The process completes with the application of calibration parameters and the loading of registers. Table 30 shows the times after the start of scan that the cell voltage inputs are sampled. The voltages are held until the ADC completes its conversion. TABLE 30. SCAN VOLTAGES FUNCTION TIMING - DAISY CHAIN MASTER OR STAND-ALONE DEVICE EVENT The Scan Temperatures command turns on the TEMPREG output and, after a 2.5ms settling interval, samples the ExT1 to ExT4 inputs. TEMPREG turns off on completion of the ExT4 measurement. The Reference voltage, IC Temperature and Multiplexer loopback function are also measured. The sequence is completed with respective registers being loaded. TABLE 31. SCAN TEMPERATURES FUNCTION TIMING – DAISY CHAIN MASTER OR STAND-ALONE DEVICE ELAPSED TIME (µs) EVENT Turn on TEMPREG Sample ExT1 TYP MAX 2 2 2518 2770 ~ TYP (µs) MAX (µs) Sample Cell 12 17 19 Sample ExT4 2564 2820 Sample Cell 11 38 42 Sample refeRence 2584 2842 Sample Cell 10 59 65 Measure Internal Temperature 2689 2958 Sample Cell 9 81 89 Load Registers 2689 2958 Sample Cell 8 102 112 Sample Cell 7 123 135 Sample Cell 6 144 159 Sample Cell 5 166 182 Sample Cell 4 187 206 Sample Cell 3 208 229 Sample Cell 2 229 252 Sample Cell 1 251 276 Complete Cell Voltage Capture (ADC complete). Sample VBAT 304 334 Complete VBAT Voltage Capture 318 349 Measure Internal Temperature 423 465 Complete VSS Test 550 605 Complete VBAT Test 726 799 Load Registers 766 842 Submit Document Feedback 67 FN8830.1 June 16, 2016 ISL78610 SCAN MIXED SCAN ALL The Scan Mixed command performs all the functions of the Scan Voltages command but interposes a measurement of the ExT1 input between the cell 7 and cell 6 measurements. The Scan All command combines the Scan Voltages, Scan Wires and Scan Temperatures commands into a single scan function. TABLE 32. SCAN MIXED FUNCTION TIMING – DAISY CHAIN MASTER OR STAND-ALONE DEVICE EVENT TABLE 34. SCAN ALL FUNCTION TIMING – DAISY CHAIN MASTER OR STAND-ALONE DEVICE ELAPSED TIME (ms) TYP (µs) MAX (µs) Sample Cell 12 17 19 Sample Cell 11 38 42 Sample Cell 10 59 65 Sample Cell 9 80 88 Sample Cell 8 101 111 Sample Cell 7 122 134 MEASURE COMMAND Complete Cell Voltage Capture 12-7 Sample Ext1 176 194 Complete Ext1 Capture 192 211 Single parameter measurements of the cell voltages, pack voltage, ExT1 to ExT4 inputs, IC temperature and reference voltage are performed using the Measure command. Sample Cell 6 207 228 Sample Cell 5 228 251 Sample Cell 4 249 274 Sample Cell 3 270 297 Sample Cell 2 291 321 Sample Cell 1 312 344 Complete Cell Voltage Capture 6-1 Sample VBAT 367 404 Complete VBAT Voltage Capture 381 419 Load Registers 829 911 SCAN WIRES The Scan Wires command initiates a sequence in which each input is loaded in turn with a test current for a duration of 4.5ms (default). At the end of this time the input voltage is checked and the test current is turned off. The result of each test is recorded and the Open-wire Fault and Fault Status registers are updated (data latched) at the conclusion of the tests. TABLE 33. SCAN WIRES FUNCTION TIMING – DAISY CHAIN MASTER OR STAND-ALONE DEVICE ELAPSED TIME (ms) EVENT TYP MAX Turn On VC0 Current 0.03 0.05 Test VC0 4.5 5.0 Turn On Vc1 Current 4.6 5.1 Test VC1 9.1 10.0 TYP MAX 0 0 Start Scan Wires 0.8 0.9 Start Scan Temperatures 60.1 66.2 Complete Sequence 62.8 69.1 Start Scan Voltages TABLE 35. VARIOUS MEASURE FUNCTION TIMINGS – DAISY CHAIN MASTER OR STAND-ALONE DEVICE ELAPSED TIME (µs) EVENT TYP MAX Measure Cell Voltage 178 196 Measure Pack Voltage 122 134 Measure ExT input 2517 2768 Measure IC Temperature 106 116 Measure Reference Voltage 106 116 Response Timing Tables Response timing depends on the number of devices in the stack, the position of the device in the stack, and how many bytes are read back. There are four “sizes” of read responses. There are the following four types of responses: 1. Single register read or ACK/NAK responses, where four bytes are returned by the Read Command 2. Read All Voltage response, which returns 40 bytes 3. Read all Temps or Read All Faults responses, which returns 22 bytes 4. Read All Setup Registers response, which returns 43 bytes In the Tables 36 through 41, the master, middle, and top device response times for any number of daisy chain devices are included with the command timing for that configuration. The right hand column shows the total time to complete the read operation. This is calculated as follows: N T COMMAND + N – 2 T MID + T TOP + T MASTER (EQ. 4) Where N = Number of devices in the stack. ~ Turn On VC12 Current 54.9 60.3 Test VC12 59.4 65.3 Load Registers 59.4 65.3 Submit Document Feedback EVENT 68 FN8830.1 June 16, 2016 ISL78610 In the following tables, internal and daisy clocks are assumed to be slow by 10% and the SPI clock is assumed to be at the stated speed. For an example, consider a stack of 6 devices. To get the full scan time with a daisy clock of 500kHz and SPI clock of 2MHz, it takes 77.6µs from the start of the Scan All command to the start of the internal scan of the top device (see Table 27), 842µs to complete an internal scan of all voltages (see Table 30 on page 67), 5.337ms to read all cell voltages from all devices (see Table 38 on page 70) and 18µs delay before issuing another command. In this case, all cell voltages in the host controller can be updated every 6.28ms. 4-BYTE RESPONSE Tables 36 and 37 show the calculated timing for read operations for 4 byte responses. This is the timing for an ACK or NAK, as well as Read Register command. TABLE 36. READ TIMING (MAX): 4-BYTE RESPONSE, DAISY CLOCK = 500kHz, SPI CLOCK = 2MHz TOP STACK DEVICE COMMAND TIME TO START OF RESPONSE (EACH DAISY DEVICE) (µs) MASTER DEVICE (µs) 2 80 139 3 82 142 4 85 144 TIME TO COMPLETE RESPONSE (DAISY CHAIN) TOP DEVICE (µs) ALL DEVICES (µs) COMMAND + RESPONSE ALL DEVICES (µs) 110 250 410 201 113 455 702 203 115 666 1004 MIDDLE DEVICE (µs) 5 87 146 206 117 880 1314 6 89 148 208 119 1099 1633 7 91 151 210 121 1323 1961 8 93 153 212 124 1550 2298 9 96 155 215 126 1783 2643 10 98 157 217 128 2020 2998 11 100 159 219 130 2261 3361 12 102 162 221 133 2506 3734 13 105 164 223 135 2757 4115 14 107 166 226 137 3011 4505 TABLE 37. READ TIMING (MAX): 4-BYTE RESPONSE, DAISY CLOCK = 250kHz, SPI CLOCK = 2MHz TIME TO COMPLETE RESPONSE (DAISY CHAIN) TOP DEVICE (µs) ALL DEVICES (µs) COMMAND + RESPONSE ALL DEVICES (µs) 204 432 743 383 208 824 1304 237 388 213 1226 1884 169 242 392 217 1636 2480 6 173 246 397 221 2055 3095 7 178 251 401 226 2483 3727 8 182 255 406 230 2919 4378 9 187 259 410 235 3365 5045 10 191 264 415 239 3820 5731 11 196 268 419 244 4283 6435 12 200 273 423 248 4755 7156 13 205 277 428 253 5237 7895 14 209 282 432 257 5727 8652 TOP STACK DEVICE COMMAND TIME TO START OF RESPONSE (EACH DAISY DEVICE) (µs) MASTER DEVICE (µs) 2 156 228 3 160 233 4 165 5 Submit Document Feedback 69 MIDDLE DEVICE (µs) FN8830.1 June 16, 2016 ISL78610 40-BYTE RESPONSE Tables 38 and 39 show the calculated timing for read operations for 40-byte responses. Specifically, this is the timing for a Read All Voltages command. TABLE 38. READ TIMING (MAX): 40-BYTE RESPONSE, DAISY CLOCK = 500kHz, SPI CLOCK = 2MHz TIME TO COMPLETE RESPONSE (DAISY CHAIN) TOP DEVICE (µs) ALL DEVICES (µs) COMMAND + RESPONSE ALL DEVICES (µs) 750 1394 1554 841 753 2239 2486 648 843 755 3090 3428 87 650 846 757 3944 4378 6 89 652 848 759 4803 5337 7 91 655 850 761 5667 6305 8 93 657 852 764 6534 7282 9 96 659 855 766 7407 8267 10 98 661 857 768 8284 9262 11 100 663 859 770 9165 10265 12 102 666 861 773 10050 11278 13 105 668 863 775 10941 12299 14 107 670 866 777 11835 13329 TOP STACK DEVICE COMMAND TIME TO START OF RESPONSE (EACH DAISY DEVICE) (µs) MASTER DEVICE (µs) 2 80 643 3 82 646 4 85 5 MIDDLE DEVICE (µs) TABLE 39. READ TIMING (MAX): 40-BYTE RESPONSE, DAISY CLOCK = 250kHz, SPI CLOCK = 2MHz TIME TO COMPLETE RESPONSE (DAISY CHAIN) TOP DEVICE (µs) ALL DEVICES (µs) COMMAND + RESPONSE ALL DEVICES (µs) 1484 2216 2527 1663 1488 3888 4368 741 1668 1493 5570 6228 169 746 1672 1497 7260 8104 6 173 750 1677 1501 8959 9999 7 178 755 1681 1506 10667 11911 8 182 759 1686 1510 12383 13842 9 187 763 1690 1515 14109 15789 10 191 768 1695 1519 15844 17755 11 196 772 1699 1524 17587 19739 12 200 777 1703 1528 19339 21740 13 205 781 1708 1533 21101 23759 14 209 786 1712 1537 22871 25796 TOP STACK DEVICE COMMAND TIME TO START OF RESPONSE (EACH DAISY DEVICE) (µs) MASTER DEVICE (µs) 2 156 732 3 160 737 4 165 5 Submit Document Feedback 70 MIDDLE DEVICE (µs) FN8830.1 June 16, 2016 ISL78610 22-BYTE RESPONSE Tables 40 and 41 show the calculated timing of read operations for 22-byte responses. This is the timing for Read All Temperature or Read All Faults command. TABLE 40. READ TIMING (MAX): 22-BYTE RESPONSE, DAISY CLOCK = 500kHz, SPI CLOCK = 2MHz TOP STACK DEVICE COMMAND TIME TO START OF RESPONSE (EACH DAISY DEVICE) (µs) MASTER DEVICE (µs) 2 80 391 3 82 394 4 85 5 TIME TO COMPLETE RESPONSE (DAISY CHAIN) TOP DEVICE (µs) ALL DEVICES (µs) COMMAND + RESPONSE ALL DEVICES (µs) 430 822 982 521 433 1347 1594 396 523 435 1878 2216 87 398 526 437 2412 2846 6 89 400 528 439 2951 3485 7 91 403 530 441 3495 4133 8 93 405 532 444 4042 4790 9 96 407 535 446 4595 5455 10 98 409 537 448 5152 6130 11 100 411 539 450 5713 6813 12 102 414 541 453 6278 7506 13 105 416 543 455 6849 8207 14 107 418 546 457 7423 8917 MIDDLE DEVICE (µs) TABLE 41. READ TIMING (MAX): 22-BYTE RESPONSE, DAISY CLOCK = 250kHz, SPI CLOCK = 2MHz TIME TO COMPLETE RESPONSE (DAISY CHAIN) TOP DEVICE (µs) ALL DEVICES (µs) COMMAND + RESPONSE ALL DEVICES (µs) 844 1324 1635 1023 848 2356 2836 489 1028 853 3398 4056 169 494 1032 857 4448 5292 6 173 498 1037 861 5507 6547 7 178 503 1041 866 6575 7819 8 182 507 1046 870 7651 9110 9 187 511 1050 875 8737 10417 10 191 516 1055 879 9832 11743 11 196 520 1059 884 10935 13087 12 200 525 1063 888 12047 14448 13 205 529 1068 893 13169 15827 14 209 534 1072 897 14299 17224 TOP STACK DEVICE COMMAND TIME TO START OF RESPONSE (EACH DAISY DEVICE) (µs) MASTER DEVICE (µs) 2 156 480 3 160 485 4 165 5 Submit Document Feedback 71 MIDDLE DEVICE (µs) FN8830.1 June 16, 2016 ISL78610 System Diagnostics Functions There are four types of faults that the system uses to determine the overall health of the system. These are: 1. Automatic Fault detection within the IC. 2. Fault detection that is automatic, but requires the host microcontroller to initiate an operation. 3. Faults that are detected by the host microcontroller during normal communication. This includes lack of response or responses that indicate a fault condition. 4. Faults that are detected by the host microcontroller following a series of commands and responses that check various internal and external circuits. Hardware Fault Detection The ISL78610 is always checking the internal V3P3, V2P5 and VREF power supplies using window comparators. If any of these voltages exceed a programmed limit (either too high or too low), then a REG fault exists. This immediately starts an alarm response. See “Alarm Response” on page 75. The ISL78610 also checks the two oscillators continually. The high speed and low speed oscillators are compared against limits and against each other. If there is a deviation greater than programmed, then an OSC fault exists. This immediately starts an alarm response. See “Alarm Response” on page 75. System Out of Limit Detection Bits are set in the fault data registers for detection of: The Overvoltage, undervoltage, over-temperature, and open-wire conditions have individual fault bits for each cell input. These bits are OR’d and reflected to bits in the Fault Status register (one bit per data register). The Open VBAT and Open VSS have one bit each in the Fault Status register. These conditions are not detected unless the host initiates a scan operation. The cell overvoltage, cell undervoltage, VBAT open and VSS open faults are sampled at the same time at the end of a Scan Voltages command. The cell undervoltage and cell overvoltage signals are also checked following a Measure Cell Voltage command. These conditions are also checked during a Scan Continuous operation. If the host initiates a Scan Continuous operation, then the status is checked automatically every scan cycle, without further host involvement. For any other Scan command, the host needs to periodically send the command to perform another check of the system. FAULT SIGNAL FILTERING Filtering is provided for the cell overvoltage, cell undervoltage, VBAT open and VSS open tests. These fault signals use a totalizing method in which an unbroken sequence of positive results is required to validate a fault condition. The sequence length (number of sequential positive samples) is set by the [TOT2:0] bits in the Fault Setup register. See Table 43 on page 73. If the host sends a Scan Continuous command, then the Scan Interval and the Totalizer value set the Fault Detection time. See Table 42. Each cell input, VBAT and VSS open circuits have separate filter functions. The filter is reset whenever a test results in a negative result (no fault). All filters are reset when the Fault Status register bits are changed. When a fault is detected, the bits must be rewritten. • Overvoltage • Undervoltage • Open-wires • Over-temperature Any out of limit condition generates an Alarm response. See “Alarm Response” on page 75. • Open VBAT • Open VSS TABLE 42. FAULT DETECTION TIME AS A FUNCTION OF SCAN INTERVAL AND NUMBER OF TOTALIZED SAMPLES SCAN SCAN INTERVAL INTERVAL (ms) CODE FAULT DETECTION TIME 000 001 010 011 100 101 110 111 FAULT SETUP REGISTER 1 2 4 8 16 32 64 128 TOTALIZER VALUE 0000 16 16 32 64 128 256 512 1024 2048 0001 32 32 64 128 256 512 1024 2048 4096 0010 64 64 128 256 512 1024 2048 4096 8192 0011 128 128 256 512 1024 2048 4096 8192 16384 0100 256 256 512 1024 2048 4096 8192 16384 32768 0101 512 512 1024 2048 4096 8192 16384 32768 65536 0110 1024 1024 2048 4096 8192 16384 32768 65536 131072 0111 2048 2048 4096 8192 16384 32768 65536 131072 262144 1000 4096 4096 8192 16384 32768 65536 131072 262144 524288 1001 8192 8192 16384 32768 65536 131072 262144 524288 1048576 1010 16384 16384 32768 65536 131072 262144 524288 1048576 2097152 1011 32768 32768 65536 131072 262144 524288 1048576 2097152 4194304 1100 65536 65536 131072 262144 524288 1048576 2097152 4194304 8388608 Submit Document Feedback 72 FN8830.1 June 16, 2016 ISL78610 TABLE 43. FAULT SETUP REGISTER REGISTER BITS 12 11 10 9 8 7 6 5 4 INTERNAL TOTALIZER TST4 TST3 TST2 TST1 ENABLE TST0 TEMP TOT2 TOT1 TOT0 COUNT WSCN 3 SCAN WIRES 2 1 0 SCAN INTERVAL SCN1 SCN0 SCN1 SCN0 TIME (ms) 0 0 0 0 None 0 Disable 0 0 0 1 0 Track Voltage Scan 0 0 0 0 16 x x x 1 ExT1 1 Enable 0 0 1 2 1 Track Temp Scan 0 0 0 1 32 x x 1 x ExT2 0 1 0 4 0 0 1 0 64 x 1 x x ExT3 0 1 1 8 0 0 1 1 128 1 x x x ExT4 1 0 0 16 0 1 0 0 256 1 0 1 32 0 1 0 1 512 1 1 0 64 0 1 1 0 1024 1 1 1 128 0 1 1 1 2048 1 0 0 0 4096 1 0 0 1 8192 1 0 1 0 16384 1 0 1 1 32768 1 1 0 0 65536 Diagnostic Activity Settling Time The majority of diagnostic functions within the ISL78610 do not affect other system activity and there is no requirement to wait before conducting further measurements. The exceptions to this are the open-wire test and cell balancing functions. OPEN-WIRE TEST The open-wire test loads each VCn pin in turn with 150µA or 1mA current. This disturbs the cell voltage measurement while the test is being applied e.g., a 1mA test current applied with an input path resistance of 1kΩ reduces the pin voltage by 1V. The time required for the cell voltage to settle following the open-wire test is dependent on the time constant of components used in the cell input circuit. The standard input circuit (Figure 51 on page 31) with the components given in Table 8 on page 38 provide settling to within 0.1mV in approximately 2.8ms. This time should be added at the end of each open-wire scan to allow the cell voltages to settle. CELL BALANCING The standard applications circuit (Figure 51 on page 31) configures the balancing circuits so that the cell input measurement reads close to zero volts when balancing is activated. There are time constants associated with the turn-on and turn-off characteristics of the cell balancing system that must be allowed for when conducting cell voltage measurements. The turn-on time of the balancing circuit is primarily a function of the 25µA drive current of the cell balancing output and the gate charge characteristic of the MOSFET and needs to be determined for a particular setup. Turn-on settling times to within 2mV of final “on” value are typically less than 5ms. Submit Document Feedback 73 The turn-off time is a function of the MOSFET gate charge and the VGS connected resistor and capacitor values (for example R27 and C27 in Figure 51 on page 31) and is generally longer than the turn-on time. As with the turn-on case, the turn-off time needs to be determined for the particular components used. Turn-off settling times in the range 10ms to 15ms are typical for settling to within 0.1mV of final value. Memory Checksum There are two checksum operations available to the host microcontroller for checking memory integrity, one for the EEPROM and one for the Page 2 registers. Two registers are provided to verify the contents of EEPROM memory. One (Page 4, address 6’h3F) contains the correct checksum value, which is calculated during factory testing at Intersil. The other (Page 5, address 6’h00) contains the checksum value calculated each time the nonvolatile memory is loaded to shadow registers, either after a power cycle or after a device reset. An inequality between these two numbers indicates corruption of the shadow register contents (and possible corruption of EEPROM data). The external microcontroller needs to compare the two registers, since it is not automatic. Resetting the device (using the Reset command) reloads the shadow registers. A persistent difference between these two register values indicates EEPROM corruption. All Page 2 registers (device configuration registers) are subject to a checksum calculation. A Calculate Register Checksum command calculates the Page 2 checksum and saves the value internally (it is not accessible). The Calculate Register Checksum command may be run any time, but should be sent whenever a Page 2 register is changed. FN8830.1 June 16, 2016 ISL78610 A Check Register Checksum command recalculates the Page 2 checksum and compares it to the internal value. The occurrence of a Page 2 checksum error sets the PAR bit in the Fault Status register and causes a Fault response accordingly. The normal response to a PAR error is for the host microcontroller to rewrite the Page 2 register contents. A PAR fault also causes the device to cease any scanning or cell balancing activity. See items 42 through 49 in Table 47 on page 76. Communication Faults There is no specific flag to indicate a communications fault. A fault is indicated by receiving an abnormal communications response or by an absence all communications. Non-daisy chain device commands and responses use CRC (Cyclical Redundancy Check) error detection. (Stand-alone systems do not use the CRC.) If a CRC is not recognized by a target device, a command includes an Address All when it is not allowed, or if there are too few bits in the sequence there is a NAK response. The host can tell where this fault occurred by reading the Device address. If there is no response, then there is a communications failure. Communication Failure All commands except the Scan, Measure and Reset commands require a response from either the stack top device or the target device (see Table 10 on page 40), each device in the stack waits for a response from the stack device above. Correct receipt of a command is indicated by the correct response. Failure to receive a response within a timeout period indicates a communications failure. The timeout value is stack position dependent. The device that detects the fault then transmits the communications failure response which includes its stack address. If the target device receives a communications failure response from the device above then the target device relays the communications failure followed by the requested data (in the case of a read) or simply relays the communications failure only (in the case of a Write, Balance command, etc). The maximum time required to return the communications failure response to the host microcontroller (the time from the falling edge of the 24th clock pulse of an SPI command to receiving a DATA READY low signal) is given for various data rates in Table 44. TABLE 44. MAXIMUM TIME TO COMMUNICATIONS FAILURE RESPONSE MAXIMUM TIME TO ASSERTION OF DATA READY DAISY CHAIN DATA RATE (kHz) 500 250 125 62.5 UNIT Communications Failure Response 5.8 11.6 23.2 46.4 ms A communications fault can be caused by one of three circumstances: • The communications system has been compromised, • The device causing the fault is in Sleep mode, or • A daisy chain input port is in the wrong idle state This latter condition is unlikely but could arise in response to external influence, such as a large transient event. The daisy chain ports are forced to the correct idle condition at the end of Submit Document Feedback 74 each communication. An external event would have the potential to “flip” the input such that the port settles in the inverse state. A flipped input condition recovers during the normal course of communications. If a flipped input is suspected, having received notification of a communications fault condition for example, the user may send a sequence of all 1’s (e.g., FF FF FF FF) to clear the fault. Wait for the resulting NAK response and then send an ACK to the device that reported the fault. The “all 1” sequence allows a device to correct a flipped condition via the normal end of communication process. The command FB FF FF FF also works and contains the correct CRC value (should this be a consideration in the way the control software is set up). If the process above results in a communications failure response, the next step is for the host microcontroller to send a Sleep command, wait for all stack devices to go to sleep, then send a Wake-up command. If successful then the host microcontroller receives an ACK once all devices are awake. In the case where a single stack device was asleep, the devices above the sleeping device would not have received the Sleep command and would respond to the Wake-up sequence with a NAK due to incomplete communications. The host microcontroller would then send a command (e.g., ACK) to check that all devices are awake. This process can be repeated as often as needed to wake up sleeping devices. In the event that the Wake-up command does not generate a response, this is a likely indication that the communications have been compromised. The host microcontroller may send a Sleep command to all units. If the communications watchdog is enabled, then all parts go to Sleep mode automatically when the watchdog period expires as long as there are no valid communications activity. Table 10 on page 40 provides a summary of the normal responses and an indication if the device waits for a response from the various communications commands. Daisy Chain Communications Conflicts Conflicts in the daisy chain system can occur if both a stack device and the host microcontroller are transmitting at the same time, or if more than one stack device transmits at the same time. Conflicts caused by a stack device transmitting at the same time as the host microcontroller are recognized by the absence of the required response (e.g., an ACK response to a write command), or by the scan counter not being incremented in the case of Scan and Measure commands. Conflicts which arise from more than one device transmitting simultaneously can occur if two devices detect faults at the same time. This can occur when the stack is operating normally (e.g., if two devices register an undervoltage fault in response to a Scan Voltages command sent to all devices). It is recommended that the host microcontroller checks the Fault Status register contents of all devices whenever a Fault response is received from one device. Loss of Signal from Host A watchdog timer is provided as part of the daisy chain communications fault detection system. The watchdog has no effect in non-daisy chain systems. FN8830.1 June 16, 2016 ISL78610 Each device must receive a valid communications sequence before its watchdog timeout period is exceeded. A valid communications sequence is one that requires an action or response from the device. Address All commands, such as the Scan and Balance commands provide a simple way to reset the watchdog timers on all devices with a single communication. Single device communications (e.g., ACK) must be sent individually to each device to reset the watchdog timer in that device. A read of the Fault Status register of each device is also a good way to reset the watchdog timer on each device. This functionality guards against situations where a runaway host microcontroller might continually send data. Failure to receive valid communications within the required time causes the WDGF bit to be set in the Fault Status register and the device to be placed in Sleep mode, with all measurement and balancing functions disabled. Daisy chain devices assert the FAULT output in response to a watchdog fault and maintain this asserted state while in Sleep mode. Notice that no watchdog fault response is automatically sent on the daisy chain interface. WATCHDOG FUNCTION The watchdog timeout is settable in two ranges using the lower 7 bits of the Watchdog/Balance time register (see Table 45). The low range (7’b0000001 to 7’b0111111) provides timeout settings in 1 second increments from 1 second to 63 seconds. The high range (7’b1000000 to 7’b1111111) provides timeout settings in 2 minute intervals from 2 minutes to 128 minutes (see Table 45 for details). TABLE 45. WATCHDOG/BALANCE TIME REGISTER REGISTER BITS 6 5 4 3 2 1 0 WDG6 WDG5 WDG4 WDG3 WDG2 WDG1 WDG0 WATCHDOG TIMEOUT 0 0 0 0 0 0 0 Disabled 0 0 0 0 0 0 1 1s 0 0 0 0 0 1 0 2s ••• - 0 1 1 1 1 1 0 62s 0 1 1 1 1 1 1 63s 1 0 0 0 0 0 0 2min 1 0 0 0 0 0 1 4min ••• - 1 1 1 1 1 1 0 126min 1 1 1 1 1 1 1 128min A zero setting (7’b0000000) disables the watchdog function. A watchdog password function is provided to guard against accidental disabling of the watchdog function. The upper 6 bits of the Device Setup register must be set to 6’h3A (111010) to allow the watchdog to be set to zero. The watchdog is disabled by first writing the password to the Device Setup register (see “Set-Up Registers” on page 87) and then writing zero to the lower bits of Submit Document Feedback 75 the Watchdog/Balance time register. The password function does not prevent changing the watchdog timeout setting to a different nonzero value. The watchdog continues to function when the ISL78610 is in Sleep mode. Parts in Sleep mode assert the FAULT output when the watchdog timer expires. WATCHDOG PASSWORD Before writing a zero to the watchdog timer, which turns off the timer, it is necessary to write a password to the [WP5:0] bits. The password value is 6’h3A. Alarm Response If any of the fault bits are set, the FAULT logic output is asserted low in response to the fault condition. The output then remains low until the bits of the Fault Status register are reset. Individual bits in the fault data registers must first be cleared before the associated bits in the Fault Status register can be cleared. If the device is in a daisy chain, the Fault logic also sends an “unprompted” response down the daisy chain to the master, which notifies the host microcontroller that a problem exists. The daisy chain fault response is immediate, so long as there is no communications activity on the device ports, and comprises the normal Fault Status register read response. As such, it includes the contents of the Status Register and includes the device address that is reporting the fault. The Fault response is only sent for the first fault occurrence. Subsequent faults do not activate the Fault response until after the Fault Status register has been cleared. If multiple devices report a fault, the response shows the results from the lowest stack device. If a fault occurs while the device ports are active, then the device waits until communications activity ceases before sending the Fault response. The host microcontroller has the option to wait for this response before sending the next message. Alternately the host microcontroller may send the next message immediately (after allowing the daisy chain ports to clear – see “Sequential Daisy Chain communications” on page 66). Any conflicts resulting from additional transmissions from the stack are recognized by the lack of response from the stack. Table 46 provides the maximum time from DATA READY going low for the last byte of the normal response to DATA READY going low for the first byte of the Fault response in the case where a Fault response is held up by active communications. TABLE 46. MAXIMUM TIME BETWEEN DATA READY SIGNALS – DELAYED FAULT RESPONSE MAXIMUM TIME BETWEEN DATA READY ASSERTIONS DAISY CHAIN DATA RATE (kHz) Fault Response 500 250 125 62.5 UNIT 68 136 272 544 µs Further read communications to the device return the Fault response followed by the requested data. Write communications return only the Fault response. Action commands return nothing. The host microcontroller resets the register bits corresponding to FN8830.1 June 16, 2016 ISL78610 the fault by writing 14’h0000 to the Fault Status register, having first cleared the bits in the Fault Data register(s) if these are set. The device then responds ACK as with a normal write response since the fault status bits are now cleared. This also prevents further Fault responses unless the fault reappears, in which case the Fault response is repeated. Additionally, the fault status of each part may be obtained at any time by reading the Fault Status register. The FAULT logic output is asserted in Sleep mode, if a fault has been detected and has not been cleared. FAULT RESPONSE IN SLEEP MODE When a stand-alone device is in the Sleep mode, the device may still detect faults if operating in Scan Continuous mode. If an error occurs, the FAULT output pin is asserted low. Devices may detect faults if operating in Scan Continuous mode while also in Sleep mode. Daisy chain devices registering a fault in Sleep mode proceed to wake up the other devices in the stack (e.g., middle devices send the Wake-up signal on both ports). Any communications received by a device on one port while it is transmitting the Wake-up signal on its other port are ignored. After receiving the Wake-up signal, the top stack device waits before sending an ACK response on Port 1. This is to allow other stack devices to wake up. The total wait time is dependent on the number of devices in the stack. The time from a device detecting a fault to receipt of the ACK response is also dependent on the stack position of the device. See Table 14 for maximum response times for stacks of 8 and 14 devices. The normal host microcontroller response to receiving an ACK while the stack is in Sleep mode is to read the Fault Status register contents of each device in the stack to determine which device (or devices) has a fault. Fault Diagnostics Table 47 shows a summary of commands and responses for the various fault diagnostics functions. TABLE 47. SUMMARY OF FAULT DIAGNOSTICS COMMANDS AND RESPONSES ITEM DIAGNOSTIC FUNCTION ACTION REQUIRED 1 Static fault detection functions. Check Fault Status (or look for normal fault response) 2 Oscillator check Check for device in Sleep function mode if stack returns a Communications Failure response. 3 Cell overvoltage Set cell overvoltage limit REGISTER READ/WRITE COMMENTS Read Fault Status register The main internal functions of the ISL78610 are monitored continuously. Bits are set in the Fault Status register is response to faults being detected in these functions. Oscillator faults are detected as part of the Static Fault detection functions. The response to an oscillator fault detection is to set the OSC bit in the Fault Status register and then to enter Sleep mode. A sleeping device does not respond to normal communications, producing a Communications Failure notification from the next device down the stack. The normal recovery procedure is send repeated Sleep and Wake-up commands ensure all devices are awake. Write Overvoltage Limit register Full scale value 14'h1FFF = 5V 4 Set fault filter sample value Write TOT bits in Fault Setup register Default is 3'b011 (8 samples) - (see “Fault Setup:” on page 85) 5 Identify which inputs have cells connected Write Cell Setup register A '0' bit value indicates cell is connected. A '1' bit value indicates no cell connected to this input. The overvoltage test is not applied to unconnected cells. 6 Scan cell voltages Send Scan Voltages command A cell overvoltage condition is flagged after a number of sequential overvoltage conditions are recorded for a single cell. The number is programmed above in item 4. 7 Check fault status Read Fault Status register The device sends the Fault Status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 8 Check overvoltage fault register Read Overvoltage Fault register 9 Reset fault bits Reset bits in Overvoltage Fault register followed and bits in Fault Status register. 10 Reset fault filter Change the value of the [TOT2:0] bits in the Fault Setup register and then change back to the required value. This resets the filter. The filter is also reset if a false overvoltage test is encountered. 11 Cell Undervoltage Set cell undervoltage limit Submit Document Feedback 76 Only required if the Fault Status register returns a fault condition. Write Undervoltage Limit Full scale value 14'h1FFF = 5V register FN8830.1 June 16, 2016 ISL78610 TABLE 47. SUMMARY OF FAULT DIAGNOSTICS COMMANDS AND RESPONSES (Continued) ITEM DIAGNOSTIC FUNCTION ACTION REQUIRED REGISTER READ/WRITE COMMENTS 12 Set fault filter sample value Write TOT Bits in Fault Setup register Default is 3'b011 (8 samples) 13 Identify which inputs have cells connected Write Cell Setup register A '0' bit value indicates cell is connected. A '1' bit value indicates no cell connected to this input. The undervoltage test is not applied to unconnected cells. 14 Scan cell voltages Send Scan Voltages command A cell undervoltage condition is flagged after a number of sequential undervoltage conditions are recorded for a single cell. The number is programmed above in item 12. 15 Check fault status Read Fault Status register The device sends the Fault Status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 16 Check undervoltage fault register Read Undervoltage Fault Only required if the Fault Status register returns a fault condition. register 17 Reset fault bits Reset bits in Undervoltage Fault register followed by bits in Fault Status register. 18 Reset fault filter Change the value of the [TOT2:0] bits in the Fault Setup register and then change back to the required value. This resets the filter. The filter is also reset if a false undervoltage test is encountered. 19 VBAT or VSS Set fault filter sample value Write TOT bits in Fault Connection Test Setup register Default is 3'b011 (8 samples) 20 Scan cell voltages Send Scan Voltages command A open condition on VBAT or VSS is flagged after a number of sequential open conditions are recorded for a single cell. The number is programmed above in item 19. 21 Check Fault Status Read Fault Status register The device sends the Fault Status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 22 Reset fault bits Reset bits in the Fault Status register. 23 Reset fault filter Change the value of the [TOT2:0] bits in the Fault Setup register and then change back to the required value. This resets the filter. The filter is also reset if a false open test is encountered. 24 Open-wire Test Set Scan current value Write Device Setup register: ISCN = 1 or 0 Sets scan current to 1mA (recommended) by setting ISCN = 1. Or, set the scan current to 150µA by setting ISCN = 0. 25 Identify which inputs have cells connected Write Cell Setup register A '0' bit value indicates cell is connected. A '1' bit value indicates no cell connected to this input. Cell inputs VC2 to VC12: the open-wire detection system is disabled for cell inputs with a '1' setting in the Cell Setup register. Cell inputs VC0 and VC1 are not affected by the Cell Setup register. 26 Activate Scan Wires function Send Scan Wires command 27 Check Fault Status Read Fault Status register The device sends the Fault Status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 28 Check Open-Wire Fault register Read Open-Wire Fault register 29 Reset fault bits 30 Overtemperature Indication Set external temperature limit Write External Temp Limit Full scale value 14'h3FFF = 2.5V register 31 Identify which inputs are required to be tested Write Fault Setup register A '1' bit value indicates input is tested. A '0' bit value indicates input is Bits TST1 to TST4 not tested. 32 Scan temperature inputs Send Scan Temperatures An over-temperature condition is flagged immediately if the input command voltage is below the limit value. Submit Document Feedback 77 Wait for Scan Wires to complete. Only required if the Fault Status register returns a fault condition. Reset bits in Open-Wire Fault register followed by bits in Fault Status register. FN8830.1 June 16, 2016 ISL78610 TABLE 47. SUMMARY OF FAULT DIAGNOSTICS COMMANDS AND RESPONSES (Continued) ITEM DIAGNOSTIC FUNCTION ACTION REQUIRED REGISTER READ/WRITE COMMENTS 33 Check Fault Status Read Fault Status register The device sends the Fault Status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 34 Check Over-temperature Fault register Read Over-temperature Fault register 35 Reset fault bits Only required if the Fault Status register returns a fault condition. Reset bits in Over-temperature Fault register followed by bits in Fault Status register. 36 Reference Read reference coefficient A Read Reference Check Function Coefficient A register 37 Read reference coefficient B Read Reference Coefficient B register 38 Read reference coefficient C Read Reference Coefficient C register 39 Scan temperature inputs Send Scan Temperatures command 40 Read reference voltage value Read Reference Voltage register 41 Calculate voltage reference value See Voltage Reference Check Calculation in the Worked Examples section of this datasheet. (See “Voltage Reference Check Calculation” on page 79.) 42 Register Checksum Calculate register checksum Send Calculate Register value Checksum command This causes the ISL78610 to calculate a checksum based on the current contents of the page 2 registers. This action must be performed each time a change is made to the register contents. The checksum value is stored for later comparison. 43 Check register checksum value Send Check Register Checksum command The checksum value is recalculated and compared to the value stored by the previous Calculate Register Checksum command. The PAR bit in the Fault Status register is set if these two numbers are not the same. 44 Check Fault Status Read Fault Status register The device sends the Fault Status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 45 Re-write registers Load all page 2 registers This is only required if a PAR fault is registered. It is recommended that with their correct values. the host reads back the register contents to verify values prior to sending a Calc Register Checksum command. 46 Reset fault bits 47 EEPROM MISR Checksum Reset bits in the Fault Status register. Read checksum value stored in EEPROM Read the EEPROM MISR Register 48 Read checksum value calculated by ISL78610 Read the MISR Checksum register 49 Compare checksum values Submit Document Feedback 78 The checksum value is calculated each time the EEPROM contents are loaded to registers, either following the application of power, cycling the EN pin followed by a host initiated Reset command, or simply the host issuing a Reset command. Correct function is indicated by the two values being equal. Memory corruption is indicated by an unequal comparison. In this event the host should send a Reset command and repeat the check process. FN8830.1 June 16, 2016 ISL78610 Worked Examples Cell Balancing – Manual Mode The following worked examples are provided to assist with the setup and calculations associated with various functions. Voltage Reference Check Calculation ADDRESS PARAMETER EXAMPLE: ACTIVATE BALANCING ON CELLS 1, 5, 7 AND 11 Step 1. Write Balance Setup register: Set Manual Balance mode, Balance Status pointer, and turn off balance. TABLE 48. EXAMPLE REGISTER DATA R/W PAGE Refer to “Manual Balance Mode” on page 46. VALUE (HEX) DECIMAL 0 001 010000 IC Temperature 14’h2425 9253 0 001 010101 Reference Voltage 14’h20A7 8359 0 010 111000 Coefficient C 14’h00A4 164 0 010 111001 Coefficient B 14’h3FCD -51 0 010 111010 Coefficient A 9’h006 6 BMD = 01 (Manual Balance mode) BWT = XXX BSP = 0000 (Balance Status Pointer location 0) BEN = 0 (Balancing disabled) Note: Blue text indicates a register change. TABLE 49. BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XX00 000X XX01 Coefficients A, B and C are two’s compliment numbers. B and C have a range +8191 to -8192. A has a range +255 to -256. X = don’t care Coefficient B above is a negative number (Hex value > 1FFF). The value for B is 14’h3FCD - 14h3FFF- 1 or (1633310 – 1638310 - 1) = -51. Step 2. Write Balance Status register: Set bits 0, 4, 6 and 10 Coefficient A occupies the upper 9 bits of register 6’b111010 (6'h3A). One way to extract the coefficient data from this register is to divide the complete register value by 32 and rounding the result down to the nearest integer. With 9'h006 in the upper 9 bits, and assuming the lower 5 bits are 0, the complete register value will be 14'h0C0 = 192 decimal. Divide this by 32 to obtain 6. Coefficients A, B and C are used with the IC temperature reading to calibrate the Reference Voltage reading. The calibration is applied by subtracting an adjustment of the form from the reference voltage reading: 2 B A Adjustment = ----------------------------- dT + ------------- dT + C 8192 256 8192 (EQ. 5) An example calculation using the data of Table 48 is given in Equation 6. 9253 – 9180 dT = -------------------------------- = 36.5 2 (EQ. 6) Where 9180 is the internal temperature monitor reading at +25°C (see the ““MEASUREMENT SPECIFICATIONS” on page 8). 2 51 6 Adjustment = ----------------------------- 36.5 – ------------- 36.5 + 164 = 163.8 8192 256 8192 (EQ. 7) Corrected V REF = 8359 – 163.8 = 8195.2 (EQ. 8) 8195.2 V REF value = ------------------ 5 = 2.5010 16384 (EQ. 9) Submit Document Feedback 79 BAL12:1 = 0100 0101 0001 TABLE 50. BALANCE STATUS REGISTER R/W PAGE ADDRESS DATA 1 010 010100 XX 0100 0101 0001 Step 3. Enable balancing using Balance Enable command TABLE 51. BALANCE ENABLE COMMAND R/W PAGE ADDRESS DATA 0 011 010000 00 0000 Or enable balancing by setting BEN directly in the Balance Setup register: BEN = 1 TABLE 52. BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XX1X XXXX XXXX The balance FETs attached to cells 1, 5, 7 and 11 turn on. Turn balancing off by resetting BEN or by sending the Balance Inhibit command (Page 3, address 6’h11). FN8830.1 June 16, 2016 ISL78610 Cell Balancing – Timed Mode Cell Balancing – Auto Mode Refer to “Timed Balance Mode” on page 47. Refer to “Auto Balance Mode” on page 47. EXAMPLE: ACTIVATE BALANCING ON CELLS 2 AND 8 FOR 1 MINUTE. BALANCE VALUE CALCULATION EXAMPLE Step 1. Write Balance Setup register: Set Timed Balance mode, Balance Status pointer, and turn off balance. BMD = 10 (Timed Balance mode) BWT = XXX BSP = 0000 (Balance Status Pointer location 0) BEN = 0 (BALANCING disabled) TABLE 53. BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XX00 000X XX10 X = don’t care Step 2. Write Balance Status register: Set bits 1 and 7 BAL12:1 = 0000 1000 0010 TABLE 54. BALANCE STATUS REGISTER R/W PAGE ADDRESS DATA 1 010 010100 XX 0000 1000 0010 Step 3. Write balance timeout setting to the Watchdog/Balance Time register (page 2, address 6’h15, bits [13:7]) BTM6:1 = 0000011 (1 minute) This example is based on a cell State of Charge (SOC) of 9360 coulombs, a target SOC of 8890 coulombs, a balancing leg impedance of 31Ω (30Ω resistor plus 1Ω FET on resistance) and a sampling time interval of 5 minutes (300 seconds). The Balance Value is calculated using Equation 10. 8191 31 B = ------------- 9360 – 8890 ---------- = 79562 = 28h00136CA 5 300 The value 8191/5 is the scaling factor of the cell voltage measurement. The value of 28’h00136CA is loaded to the required Cell Balance Register and the value 7’b0001111 (5 minutes) is loaded to the Balance Time bits in the Watchdog/Balance time register. In this example, the total coulomb difference to be balanced is: 470 coulomb (9360 - 8890). At 3.3V/31Ω * 300s = 31.9 coulomb per cycle, it takes about 15 cycles for the balancing to terminate. AUTO BALANCE MODE CELL BALANCING EXAMPLE The following describes a simple setup to demonstrate the Auto Balance mode cell balancing function of the ISL78610. Note that this balancing setup is not related to the balance value calculation in Equation 10. Auto balance cells using the following criteria: • Balance time = 20 seconds TABLE 55. WATCHDOG/BALANCE TIME REGISTER R/W PAGE ADDRESS DATA 1 010 010101 00 0001 1XXX XXXX X = don’t care – the lower bits are the watchdog timeout value and should be set to a time longer than the balance time. A value of 111 1111 is suggested. Step 4. Enable balancing using Balance Enable command TABLE 56. BALANCE ENABLE COMMAND R/W PAGE ADDRESS DATA 0 011 010000 00 0000 Or enable balancing by setting BEN directly in the Balance Setup register: BEN = 1 • Balance wait time (dead time between balancing cycles) = 8 seconds • Balancing disabled during cell measurements. • Balance Values: See Table 58 TABLE 58. CELL BALANCE VALUES (HEX) FOR EACH CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL 1 2 3 4 5 6 7 8 9 10 11 12 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 151 502 6D6 0 290 3D0 0 0 292 3E0 406 3E4 E 6 3 0 F D A • Balance Status Register: Set up balance: Cells 1, 4, 7 and 10 on 1st cycle. Cells 3, 6, 9 and 12 on 2nd cycle. Cells 2, 5, 8 and 11 on 3rd cycle (See Table 59) TABLE 59. BALANCE STATUS SETUP TABLE 57. BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XX1X XXXX XXXX The balance FETs attached to cells 2 and 8 turn on. The FETs turn off after 1 minute. Balancing may be stopped by resetting BEN or by sending the Balance Inhibit command. Submit Document Feedback 80 (EQ. 10) CELL BPS [3:0] 1 0000 Reserved for Manual Balance mode and Timed Balance mode 0001 1 0 0 1 0 0 1 0 0 1 0 0 0010 0 0 1 0 0 1 0 0 1 0 0 1 0011 0 1 0 0 1 0 0 1 0 0 1 0 2 3 4 5 6 7 8 9 10 11 12 FN8830.1 June 16, 2016 ISL78610 Step 1. Write Balance Value registers TABLE 62. DEVICE SETUP REGISTER TABLE 60. BALANCE VALUE REGISTERS R/W PAGE ADDRESS DATA (HEX) CELL 1 010 100000 14’h006A 1 1 010 100001 14’h0001 1 010 100010 14’h3E4D 1 010 100011 14’h0000 1 010 100100 14’h0000 1 010 100101 14’h0000 1 010 100110 14’h292F 1 010 100111 14’h0000 1 010 101000 14’h3E00 1 010 101001 14’h0000 1 010 101010 14’h0000 1 010 101011 14’h0000 1 010 101100 14’h2903 1 010 101101 14’h0000 1 010 101110 14’h3D06 1 010 101111 14’h0000 1 010 110000 14’h0000 1 010 110001 14’h0000 1 010 110010 14’h151E 1 010 110011 14’h0000 1 010 110100 14’h0502 1 010 110101 14’h0000 1 010 110110 14’h06D6 1 010 110111 14’h0000 2 3 4 5 6 7 8 9 10 11 12 1 1 0 1 0 1 0 B0113 B0112 B1011 B0110 B0109 B0108 0 6’21 0 0 0 0 0 B0121 B0120 B0119 B0118 B0117 B0116 B0115 B0114 0 0 0 0 0 0 0 0 0 0 DATA 1 010 011001 XX XXXX 1XXX XXXX X = don’t care Step 3. Write balance timeout setting to the Watchdog/Balance Time register: Balance timeout code = 0000001 (20 seconds) BTM6:0 = 000 0001 R/W PAGE ADDRESS DATA 1 010 010101 00 0000 1XXX XXXX X = don’t care – the lower bits are the watchdog timeout value and should be set to a time longer than the balance time. A value 111 1111 is suggested. Step 4. Set up Balance Status register (from Table 59 on page 80) Step 4A. Write Balance Setup register: Set Auto Balance mode, set 8 second Balance wait time, and set balance off: BMD = 11 (Auto Balance mode) BWT = 100 (8 seconds) BEN = 0 (Balancing disabled) TABLE 64. BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XX0X XXX1 0011 X = don’t care Step 4B. Write Balance Setup register: Set Balance Status Pointer = 1 0 TABLE 65. BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XXX0 001X XXXX X = don’t care Step 4C. Write Balance Status register: Set bits 1, 4, 7 and 10 BAL12:1 = 0010 0100 1001 1 B0127 B0126 B0125 B0124 B0123 B0122 0 ADDRESS BSP = 0001 (Balance status pointer = 1) B0107 B0106 B0105 B0104 B0103 B0102 B0101 B0100 0 PAGE TABLE 63. BALANCE TIMEOUT REGISTER TABLE 61. BALANCE VALUE REGISTERS (CELL1) - VALUE 28’h406A 6’20 R/W 0 Step 2. Write BDDS bit in Device Setup register (turn balancing functions off during measurement) TABLE 66. BALANCE STATUS REGISTER R/W PAGE ADDRESS DATA 1 010 010100 XX 0010 0100 1001 Step 4D. Write Balance Setup register: Set Balance Status Pointer = 2 BDDS = 1 Submit Document Feedback 81 FN8830.1 June 16, 2016 ISL78610 Step 5. Enable balancing using Balance Enable command BSP = 0010 (Balance status pointer = 2) TABLE 67. BALANCE SETUP REGISTER BALANCE ENABLE COMMAND R/W PAGE ADDRESS DATA R/W PAGE ADDRESS DATA 1 010 010011 XX XXX0 010X XXXX 0 011 010000 00 0000 X = don’t care Step 4E. Write Balance Status register: Set bits 3, 6, 9 and 12 Or enable balancing by setting BEN directly in the Balance Setup register: BEN = 1 BAL12:1 = 1001 0010 0100 BALANCE SETUP REGISTER BALANCE STATUS REGISTER R/W PAGE ADDRESS DATA 1 010 010100 XX 1001 0010 0100 Step 4F. Write Balance Setup register: Set Balance Status Pointer = 3 BSP = 0011 (Balance status pointer = 3) BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XXX0 011X XXXX X = don’t care Step 4G. Write Balance Status register: Set bits 2, 5, 8 and 11 BAL12:1 = 0100 1001 0010 BALANCE STATUS REGISTER R/W PAGE ADDRESS DATA 1 010 010100 XX 0100 1001 0010 Step 4H. Write Balance Setup register: Set Balance Status Pointer = 4 BSP = 0100 (Balance status pointer = 4) BALANCE SETUP REGISTER R/W PAGE ADDRESS DATA 1 010 010011 XX XXX0 100X XXXX X = don’t care Step 4I. Write Balance Status register: Set bits to all zero to set the end point for the instances. BAL12:1 = 0000 0000 0000 BALANCE STATUS REGISTER R/W PAGE ADDRESS DATA 1 010 010100 XX 0000 0000 0000 R/W PAGE ADDRESS DATA 1 010 010011 XX XX1X XXXX XXXX The balance FETs cycle through each instance of the Balance Status register in a loop, interposing the balance wait time between each instance. The measured voltage of each cell being balanced is subtracted from the balance value for that cell at the end of each Balance Status instance. The process continues until the Balance Value register for each cell contains zero. System Registers System registers contain 14 bits each. All register locations are memory mapped using a 9-bit address. The MSBs of the address form a 3-bit page address. Page 1 (3’b001) registers are the measurement result registers for cell voltages and temperatures. Page 3 (3’b011) is used for commands. Pages 1 and 3 are not subject to the checksum calculations. Page addresses 4 and 5 (3’b100 and 3b’101), with the exception of the EEPROM checksum registers, are reserved for internal functions. All page 2 registers (device configuration registers), together with the EEPROM checksum registers, are subject to a checksum calculation. The checksum is calculated in response to the Calculate Register Checksum command using a Multiple Input Shift Register (MISR) error detection technique. The checksum is tested in response to a Check Register Checksum command. The occurrence of a checksum error sets the PAR bit in the Fault Status register and causes a Fault response accordingly. The normal response to a PAR error is for the host microcontroller to rewrite the page 2 register contents. A PAR fault also causes the device to cease any scanning or cell balancing activity. A description of each register is included in “Register Descriptions” and includes a depiction of the register with bit names and initialization values at power up, when the EN pin is toggled and the device receives a Reset Command, or when the device is reset. Bits which reflect the state of external pins are notated “Pin” in the initialization space. Bits which reflect the state of nonvolatile memory bits (EEPROM) are notated “NV” in the initialization space. Initialization values are shown below each bit name. Reserved bits (indicated by gray areas) should be ignored when reading and should be set to “0” when writing to them. Submit Document Feedback 82 FN8830.1 June 16, 2016 ISL78610 Register Descriptions Cell Voltage Data BASE ADDR (PAGE) 3’b001 ADDRESS RANGE ACCESS DESCRIPTION Read Only 6’h00 - 6’h0C Measured cell voltage and pack voltage values. Address 001111 accesses all cell and Pack Voltage data with and 6’h0F one read operation. See Figure 70D on page 60. Cell values are output as 13-bit signed integers with the 14th bit (MSB) denoting the sign, (e.g., positive full scale is 14’h1FFF, 8191 decimal, negative full scale is 14’h2000, 8192 decimal). VBAT is a 14-bit unsigned integer. ACCESS PAGE ADDR REGISTER ADDRESS Read Only 3’b001 6’h00 VBAT Voltage 6’h01 Cell 1 Voltage 6’h02 Cell 2 Voltage 6’h03 Cell 3 Voltage 6’h04 Cell 4 Voltage 6’h05 Cell 5 Voltage DESCRIPTION 6’h06 Cell 6 Voltage 6’h07 Cell 7 Voltage 6’h08 Cell 8 Voltage 6’h09 Cell 9 Voltage 6’h0A Cell 10 Voltage 6’h0B Cell 11 Voltage 6’h0C Cell 12 Voltage 6’h0F Read all cell voltages HEXvalue 10 – 16384 2 2.5 VCx = ---------------------------------------------------------------------------------------------------8192 HEXvalue 10 2 2.5 VCx = ----------------------------------------------------8192 ifHEXvalue 10 8191 ifHEXvalue 10 8191 HEXvalue 10 15.9350784 2.5 VBAT = -------------------------------------------------------------------------------------------------------------------------8192 Temperature Data, Secondary Voltage Reference Data, Scan Count BASE ADDR (PAGE) 3’b001 ADDRESS RANGE ACCESS DESCRIPTION 6’h10 - 6’h16 Measured temperature, Secondary reference, Scan Count. Address 011111 accesses all these data in a See and 6’h1F continuous read (see Figure 70D on page 60). Temperature and reference values are output as 14-bit individual register unsigned integers, (e.g., full scale is 14’h3FFF (16383 decimal)). HEXvalue 10 2.5 Vtemp = -------------------------------------------16384 ACCESS PAGE ADDR REGISTER ADDRESS Read Only 3’b001 6’h10 DESCRIPTION Internal temperature reading. 6’h11 External temperature input 1 reading. 6’h12 External temperature input 2 reading. 6’h13 External temperature input 3 reading. 6’h14 External temperature input 4 reading. 6’h15 Reference voltage (raw ADC) value. Use to calculate corrected reference value using reference coefficient data. See Page 2 data, address 6’h38 – 6’h3A. Submit Document Feedback 83 FN8830.1 June 16, 2016 ISL78610 ACCESS Read/ Write PAGE ADDR REGISTER ADDRESS 3’h001 6’h16 DESCRIPTION Scan Count: Current scan instruction count. Count is incremented each time a scan command is received and wraps to zero when overflowed. Register may be compared to previous value to confirm scan command receipt. Bit Designations: 13 12 11 10 0 0 0 0 9 8 7 6 5 4 0 0 0 0 RESERVED Read Only 3’h001 6’h1F 0 0 3 2 1 0 SCN3 SCN2 SCN1 SCN0 0 0 0 0 Read all: Temperature Data, Secondary Voltage Reference Data, Scan Count (locations 6’h10 - 6’h16) Fault Registers BASE ADDR (PAGE) 3’h010 ACCESS Read/ Write ACCESS Read/ Write ADDRESS RANGE DESCRIPTION 6’h00 - 6’h05 Fault registers. Fault setup and status information. Address 6’h0F accesses all fault data in a continuous and 6’h0F read (daisy chain configuration only). See Figure 70D on page 60. PAGE ADDR REGISTER ADDRESS 3’h010 6’h00 DESCRIPTION Overvoltage Fault: Overvoltage fault on cells 12 to 1 correspond with bits OF12 to OF1, respectively. Default values are all zero. Bits are set to 1 when faults are detected. The contents of this register may be reset via register write (14’h0000). 13 12 RESERVED 0 Read/ Write 3’h010 6’h01 0 12 RESERVED 0 3’h010 6’h02 9 8 7 6 5 4 3 2 1 0 OF10 OF9 OF8 OF7 OF6 OF5 OF4 OF3 OF2 OF1 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 UF12 UF11 UF10 UF9 UF8 UF7 UF6 UF5 UF4 UF3 UF2 UF1 0 0 0 0 0 0 0 0 0 0 0 0 Open-Wire Fault: Open-Wire fault on Pins VC12 to VC0 correspond with bits OC12 to OC0, respectively. Default values are all zero. Bits are set to 1 when faults are detected. The contents of this register may be reset via register write (14’h0000). 13 12 RESER OC12 VED 0 Submit Document Feedback 10 OF11 Undervoltage Fault: Undervoltage fault on cells 12 to 1 correspond with bits UF12 to UF1, respectively. Default values are all zero. Bits are set to 1 when faults are detected. The contents of this register may be reset via register write (14’h0000). 13 Read/ Write 11 OF12 84 0 11 10 9 8 7 6 5 4 3 2 1 0 OC11 OC10 OC9 OC8 OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 0 0 0 0 0 0 0 0 0 0 0 0 FN8830.1 June 16, 2016 ISL78610 ACCESS Read/ Write PAGE ADDR REGISTER ADDRESS 3’h010 6’h03 Submit Document Feedback DESCRIPTION Fault Setup: These bits control various Fault configurations. Default values are shown below, as are descriptions of each bit. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESER VED TST4 TST3 TST2 TST1 TST0 TOT2 TOT1 TOT0 WSCN SCN3 SCN2 SCN1 SCN0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 SCN0, 1, 2, 3 Scan interval code. Decoded to provide the scan interval setup for the auto scan function. Initialized to 0000 (16ms scan interval). See Table 11 on page 42. WSCN Scan wires timing control. Set to 1 for tracking of the temperature scan interval. Set to 0 for tracking of the cell voltage scan interval above 512ms. Interval is fixed at 512ms for faster cell scan rates. See Table 11 on page 42. TOT0, 1, 2 Fault Totalizer code bits. Decoded to provide the required fault totalization. An unbroken sequence of positive fault results equal to the totalize amount is needed to verify a fault condition. Initialized to 011 (8 sample totalizing.) See Table 42 on page 72. This register must be re-written following an error detection resulting from totalizer overflow. TST0 Controls temperature testing of internal IC temperature. Set bit to 1 to enable internal temperature test. Set to 0 to disable (not recommended). Initialized to 1 (on). TST1 to TST4 Controls temperature testing on the external temperature inputs 1 to 4, respectively. Set bit to 1 to enable the corresponding temperature test. Set to 0 to disable. Allows external inputs to be used for general voltage monitoring without imposing a limit value. TST1 to TST4 are initialized to 0 (off). 85 FN8830.1 June 16, 2016 ISL78610 ACCESS Read/ Write Read/ Write PAGE ADDR REGISTER ADDRESS 3’h010 6’h04 3’h010 6’h05 DESCRIPTION Fault Status: The FAULT logic output is an OR function of the bits in this register: the output will be asserted low if any bits in the Fault Status register are set. 13 12 11 10 MUX REG REF PAR 0 0 0 0 9 8 OVSS OVBAT 0 0 7 6 5 4 3 2 OW UV OV OT WDGF OSC 0 0 0 0 0 0 1 0 RESERVED 0 0 OSC Oscillator fault bit. Bit is set in response to a fault on either the 4MHz or 32kHz oscillators. Note that communications functions may be disrupted by a fault in the 4MHz oscillator. WDGF Watchdog timeout fault. Bit is set in response to a watchdog timeout. OT Over-temperature fault. ‘OR’ of over-temperature fault bits: TFLT0 to TFLT4. This bit is latched. The bits in the Over-temperature Fault register must first be reset before this bit can be reset. Reset by writing 14’h0000 to this register. OV Overvoltage fault. ‘OR’ of Overvoltage fault bits: OF1 to OF12. This bit is latched. The bits in the Overvoltage Fault register must first be reset before this bit can be reset. Reset by writing 14’h0000 to this register. UV Undervoltage fault. ‘OR’ of Undervoltage fault bits: UF1 to UF12. This bit is latched. The bits in the Undervoltage Fault register must first be reset before this bit can be reset. Reset by writing 14’h0000 to this register. OW Open-Wire fault. ‘OR’ of open-wire fault bits: OC0 to OC12. This bit is latched. The bits in the Open-Wire Fault register must first be reset before this bit can be reset. Reset by writing 14’h0000 to this register. OVBAT Open-wire fault on VBAT connection. Bit set to 1 when a fault is detected. May be reset via register write (14’h0000). OVSS Open-wire fault on VSS connection. Bit set to 1 when a fault is detected. May be reset via register write (14’h0000). PAR Register checksum (Parity) error. This bit is set in response to a register checksum error. The checksum is calculated and stored in response to a Calc Register Checksum command and acts on the contents of all page 2 registers. The Check Register Checksum command is used to repeat the calculation and compare the results to the stored value. The PAR bit is then set if the two results are not equal. This bit is not set in response to a nonvolatile EEPROM memory checksum error. See table on page 93. REF Voltage reference fault. This bit is set if the voltage reference value is outside its “power-good” range. REG Voltage regulator fault. This bit is set if a voltage regulator value (V3P3, VCC or V2P5) is outside its “power-good” range. MUX Temperature multiplexer error. This bit is set if the VCC loopback check returns a fault. The VCC loopback check is performed at the end of each temperature scan. Cell Setup: Default values are shown below, as are descriptions of each bit. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FFSN FFSP C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C1 to C12 Enable/disable cell overvoltage, undervoltage and open-wire detection on cells 1 to 12, respectively. Set to 1 to disable OV/UV and open-wire tests. FFSP Force ADC input to Full Scale Positive. All cell scan readings forced to 14'h1FFF. All temperature scan readings forced to 14'h3FFF. FFSN Force ADC input to Full Scale Negative. All cell scan readings forced to 14'h2000. All temperature scan readings forced to 14'h0000. NOTE: The ADC input functions normally if both FFSN and FFSP are set to '1' but this setting is not supported. Submit Document Feedback 86 FN8830.1 June 16, 2016 ISL78610 ACCESS Read/ Write PAGE ADDR REGISTER ADDRESS 3’h010 6’h06 DESCRIPTION Over-Temperature Fault: Over-temperature fault on cells 12 to 1 correspond with bits OF12 to OF1, respectively. Default values are all zero. Bits are set to 1 when fault are detected. The contents of this register may be reset via register write (14’h0000). 13 12 11 10 0 0 0 0 9 8 7 6 5 0 0 0 0 RESERVED Read Only 3’h010 6’h0F 0 4 3 2 1 0 TFLT4 TFLT3 TFLT2 TFLT1 TFLT0 0 0 0 0 0 TFLT0 Internal over-temperature fault. Bit set to 1 when a fault is detected. May be reset via register write (14’h0000). TFLT1 - TFLT4 External over-temperature inputs 1 to 4 (respectively.) Bit set to 1 when a fault is detected. May be reset via register write (14’h0000). Read all Fault and Cell Setup data from locations: 6’h00 - 6’h06. See Figure 70D on page 60. Set-Up Registers BASE ADDR (PAGE) 3’b010 ACCESS Read/ Write ADDRESS RANGE Access DESCRIPTION 6’h10 - 6’h1D Device Set-up registers. All device setup data. and 6’h1F PAGE ADDR REGISTER ADDRESS 3’b010 6’h10 DESCRIPTION Overvoltage Limit: Overvoltage Limit Value Overvoltage limit is compared to the measured values for cells 1 to 12 to test for an overvoltage condition at any of the cells. Bit 0 is the LSB, Bit 12 is the MSB. Bit 13 is not used and must be set to 0. 13 12 RESER OV12 VED 0 Read/ Write 3’b010 6’h11 1 12 RESER UV12 VED 0 3’b010 6’h12 10 9 8 7 6 5 4 3 2 1 0 OV10 OV9 OV8 OV7 OV6 OV5 OV4 OV3 OV2 OV1 OV0 1 1 1 1 1 1 1 1 1 1 1 1 Undervoltage Limit: Undervoltage Limit Value Undervoltage limit is compared to the measured values for cells 1 to 12 to test for an undervoltage condition at any of the cells. Bit 0 is the LSB, Bit 12 is the MSB. Bit 13 is not used and must be set to 0. 13 Read/ Write 11 OV11 0 11 10 9 8 7 6 5 4 3 2 1 0 UV11 UV10 UV9 UV8 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 0 0 0 0 0 0 0 0 0 0 0 0 External Temperature Limit: Over-temperature limit value Over-temperature limit is compared to the measured values for external temperatures 1 to 4 to test for an over-temperature condition at any input. The temperature limit assumes NTC temperature measurement devices (i.e., an over-temperature condition is indicated by a temperature reading below the limit value). Bit 0 is the LSB, Bit 13 is the MSB. 13 12 11 10 ETL13 ETL12 ETL11 ETL10 0 Submit Document Feedback 87 0 0 0 9 8 7 6 5 4 3 2 1 0 ETL9 ETL8 ETL7 ETL6 ETL5 ETL4 ETL3 ETL2 ETL1 ETL0 0 0 0 0 0 0 0 0 0 0 FN8830.1 June 16, 2016 ISL78610 ACCESS Read/ Write PAGE ADDR REGISTER ADDRESS 3’b010 6’h13 DESCRIPTION Balance Setup: Default values are shown below, as are descriptions of each bit. 13 12 11 10 RESERVED 0 0 0 BMD0, 1 0 9 8 7 6 5 BEN BSP3 BSP2 BSP1 BSP0 0 0 0 0 0 3’b010 6’h14 Submit Document Feedback 0 0 0 0 0 0 MODE 0 0 OFF 0 1 Manual 1 0 Timed 1 1 Auto BSP0, 1, 2, 3 Balance Status register pointer. Points to one of the 13 incidents of the Balance Status register. Balance Status register 0 is used for Manual Balance mode and Timed Balance mode. Balance status registers 1 to 12 are used for Auto Balance mode. Reads and writes to the Balance Status register are accomplished by first configuring the Balance Status register pointer (e.g., to read (write) Balance Status register 5, load 0101 to the Balance Status register pointer, then read (write) to the Balance Status register). See Table 16 on page 46. BEN Balance enable. Set to ‘1’ to enable balancing. ‘0’ inhibits balancing. Setting or clearing this bit does not affect any other register contents. Balance Enable and Balance Inhibit commands are provided to allow control of this function without requiring a register write. These commands have the same effect as setting this bit directly. This bit is cleared automatically when balancing is complete and the EOB bit (see “6’h19” on page 89) is set. Balance Status The Balance Status register is a multiple incidence register controlled by the BSP0-4 bits in the Balance setup register. See Table 16 on page 46. Bit 0 is the LSB, Bit 11 is the MSB. 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED BAL 12 BAL 11 BAL 10 BAL 8 BAL 8 BAL 7 BAL 6 BAL 5 BAL 4 BAL 3 BAL 2 BAL 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BAL1 to BAL12 6’h15 1 Balance wait time. Register contents are decoded to provide the required wait time between device balancing. This is to assist with thermal management and is used with the Auto Balance mode. See Table 16 on page 46. 0 3’b010 2 BWT0, 1, 2 13 Read/ Write 3 Balance mode. These bits set balance mode. BMD1 BMD0 Read/ Write 4 BWT2 BWT1 BWT0 BMD1 BMD0 Cell 1 to Cell 12 balance control, respectively. A bit set to 1 enables balance control (turns FET on) of the corresponding cell. Writing this bit enables balance output for the current incidence of the Balance Status register for the cells corresponding to the particular bits, depending on the condition of BEN in the Balance Setup register. Read this bit to determine the current status of each cell’s balance control. Watchdog/Balance Time Defaults are shown below: 13 12 11 10 9 8 BTM6 BTM5 BTM4 BTM3 BTM2 BTM1 0 0 0 0 0 0 88 7 6 5 4 3 2 1 0 BTM0 WDG6 WDG5 WDG4 WDG3 WDG2 WDG1 WDG0 0 1 1 1 1 1 1 1 WDG0 to WDG6 Watchdog timeout setting. Decoded to provide the time out value for the watchdog function. See “Watchdog Function” on page 75 for details. The watchdog may only be disabled (set to 7’h00) if the watchdog password is set. The watchdog setting can be changed to a nonzero value without writing to the watchdog password. Initialized to 7’h7F (128 minutes). BTM0 to BTM6 Balance timeout setting. Decoded to provide the time out value for Timed Balance mode and Auto Balance mode. Initialized to 7’00 (Disabled). See Table 18 on page 47. FN8830.1 June 16, 2016 ISL78610 PAGE ADDR REGISTER ADDRESS Read/ Write 3’b010 6’h16 6’h17 User Register 28 bits of register space arranged as 2 x 14 bits available for user data. These registers have no effect on the operation of the ISL78610. These registers are included in the register checksum function. Read Only 3’b010 6’h18 Comms Setup ACCESS DESCRIPTION 13 Read/ Write 3’b010 6’h19 12 11 0 6’h1B 6’h1C Submit Document Feedback 6 5 4 SIZE 2 SIZE 1 SIZE 0 0 0 0 0 3 2 1 0 ADDR ADDR ADDR ADDR 3 2 1 0 0 0 0 0 ADDR0-3 Device stack address. The stack address (device position in the stack) is determined automatically by the device in response to an “Identify” command. The resulting address is stored in ADDR0-3 and is used internally for communications paring and sequencing. The stack address may be read by the user but not written to. SIZE0-3 Device stack size (top stack device address). Corresponds to the number of devices in the stack. The stack size is determined automatically by the stack devices in response to an “Identify” command. The resulting number is stored in SIZE0-3 and is used internally for communications paring and sequencing. The stack size may be read by the user but not written to. CSEL1, 2 Communications setup bits. These bits reflect the state of the COMMS SELECT 1,2 pins and determine the operating mode of the communications ports. See Table 3 on page 26. CRAT0, 1 Communications rate bits. These bits reflect the state of the COMMS RATE 0,1 pins and determine the bit rate of the daisy chain communications system. Table 4 on page 27. Device Setup 13 12 11 10 9 8 WP5 WP4 WP3 WP2 WP1 WP0 0 0 0 0 0 0 7 6 BDDS RESER VED 0 0 5 4 3 ISCN SCAN EOB 0 0 0 2 1 0 RESER PIN37 PIN39 VED 0 Pin Pin These bits indicate the signal level on pin 37 and pin 39 of the device. End Of Balance. This bit is set by the device when balancing is complete. This function is used in the Timed Balance mode and Auto Balance mode. The BEN bit is cleared as a result of this bit being set. Initialized to 1. SCAN Scan Continuous mode. This bit is set in response to a Scan Continuous command and cleared by a Scan Inhibit command. ISCN Set wire scan current source/sink values. Set to 0 for 150µA. Set to 1 for 1mA. BDDS Balance condition during measurement. Controls the balance condition in Scan Continuous mode and Auto Balance mode. Set to 1 to have balancing functions turned off 10ms prior to and during cell voltage measurement. Set to 0 for normal operation (balancing functions not affected by measurement). WP5:0 Watchdog disable password. These bits must be set to 6’h3A (111010) before the watchdog can be disabled. Disable watchdog by writing 7’h00 to the watchdog bits. Internal Temperature Limit Bit 0 is the LSB, Bit 13 is the MSB. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ITL 13 ITL 12 ITL 11 ITL 10 ITL 8 ITL 8 ITL 7 ITL 6 ITL 5 ITL 4 ITL 3 ITL 2 ITL 1 ITL 0 NV NV NV NV NV NV NV NV NV NV NV NV NV ITL1 to ITL12 3’b010 7 SIZE 3 COMS COMS COMS COMS RATE1 RATE0 SEL2 SEL1 pin pin pin pin NV Read Only 8 CSEL 1 0 EOB 6’h1A 9 CSEL 2 CRAT1 CRAT0 PIN37, PIN39 Read Only 3’b010 Value set in EEPROM 10 RESERVED IC over-temperature limit value. Over-temperature limit is compared to the measured values for internal IC temperature to test for an over-temperature condition. The internal temperature limit value is stored in nonvolatile memory during test and loaded to these register bits at power up. The register contents may be read by the user but not written to. Serial Number The 28b serial number programmed in nonvolatile memory during factory test is mirrored to these 2 x 14 bit registers. The serial number may be read at any time but may not be written. 89 FN8830.1 June 16, 2016 ISL78610 ACCESS PAGE ADDR REGISTER ADDRESS Read Only 3’b010 Value set in EEPROM 6’h1D DESCRIPTION Trim Voltages 13 12 11 10 9 8 TV5 TV4 TV3 TV2 TV1 TV0 RESERVED NV NV NV NV NV NV Ignore the Contents of these bits TV5:0 Read Only 3’h010 6’h1F 7 6 5 4 3 2 1 0 Trim voltage (VNOM). The nominal cell voltage is programmed to nonvolatile memory during test and loaded to the Trim Voltage register at power up. The VNOM value is a 7-bit representation of the 0V to 5V cell voltage input range with 50 (7’h32) representing 5V (e.g., LSB = 0.1V). The parts are additionally marked with the trim voltage by the addition of a two digit code to the part number e.g., 3.3V is denoted by the code 33. (1 bit per 0.1V of trim voltage, so 0 to 50 decimal covers the full range.) Read all Setup data from locations: 6’h10 - 6’h1D. See Figure 70D on page 60. Cell Balance Registers BASE ADDR (PAGE) 3’b010 ACCESS Read/ Write ADDRESS RANGE ACCESS Read/ Write 6’h20 - 6’h37 DESCRIPTION Cell balance registers. These registers are loaded with data related to change in SOC desired for each cell. This data is then used during Auto Balance mode. The data value is decremented with each successive ADC sample until a zero value is reached. The register space is arranged as 2 x 14-bit per cell for 24 x 14-bit total. The registers are cleared at device power up or by a Reset command. See “Auto Balance Mode” on page 47. PAGE ADDR REGISTER ADDRESS 3’b010 6’h20 Cell 1 balance value Bits 0 to 13. 6’h21 Cell 1 balance value Bits 14 to 27. DESCRIPTION ~ 6’h36 Cell 12 balance value Bits 0 to 13. 6’h37 Cell 12 balance value Bits 14 to 27. Reference Coefficient Registers BASE ADDR (PAGE) ACCESS ADDRESS RANGE 3’b010 Read Only 6’h38 - 6’h3A ACCESS Read Only Value set in EEPROM PAGE ADDR REGISTER ADDRESS 3’b010 6’h38 Submit Document Feedback DESCRIPTION Reference Coefficients Bit 13 is the MSB, Bit 0 is the LSB DESCRIPTION Reference Coefficient C Reference calibration coefficient C LSB. Use with coefficients A and B and the measured reference value to obtain the compensated reference measurement. This result may be compared to limits given in the “Electrical Specifications” table to check that the reference is within limits. The register contents may be read by the user but not written to. 90 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC 13 RCC 12 RCC 11 RCC 10 RCC 9 RCC 8 RCC 7 RCC 6 RCC 5 RCC 4 RCC 3 RCC 2 RCC 1 RCC 0 NV NV NV NV NV NV NV NV NV NV NV NV NV NV FN8830.1 June 16, 2016 ISL78610 Read Only Read Only 3’b010 6’h39 3’b010 Reference Coefficient B Reference calibration coefficient B LSB. Use with coefficients A and C and the measured reference value to obtain the compensated reference measurement. This result may be compared to limits given in the “Electrical Specifications” table to check that the reference is within limits. The register contents may be read by the user but not written to. 6’h3A 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCB 13 RCB 12 RCB 11 RCB 10 RCB 9 RCB 8 RCB 7 RCB 6 RCB 5 RCB 4 RCB 3 RCB 2 RCB 1 RCB 0 NV NV NV NV NV NV NV NV NV NV NV NV NV NV Reference Coefficient A Reference calibration coefficient A LSB. Use with coefficients B and C and the measured reference value to obtain the compensated reference measurement. This result may be compared to limits given in the “Electrical Specifications” table to check that the reference is within limits. The register contents may be read by the user but not written to. 13 12 11 10 9 8 7 6 5 RCA 8 RCA 7 RCA 6 RCA 5 RCA 4 RCA 3 RCA 2 RCA 1 RCA 0 4 3 RESERVED 2 1 0 NV NV NV NV NV NV NV NV NV Ignore the content of these bits Cells In Balance Register BASE ADDR (PAGE) ACCESS ADDRESS RANGE 3’b010 Read Only 6’h3B ACCESS PAGE ADDR REGISTER ADDRESS Read Only 3’b010 6’h3B DESCRIPTION Cells In Balance (Valid for non-daisy chain configuration only). DESCRIPTION Cells Balance Enabled This register reports the current condition of the cell balance outputs. Bit 0 is the LSB, Bit 11 is the MSB. 13 12 RESERVED 0 0 11 10 9 8 7 6 5 4 3 2 1 0 CBEN 12 CBEN 11 CBEN 10 CBEN 8 CBEN 8 CBEN 7 CBEN 6 CBEN 5 CBEN 4 CBEN 3 CBEN 2 CBEN 1 0 0 0 0 0 0 0 0 0 0 0 0 BALI1 to BALI12 Submit Document Feedback 91 Indicates the current balancing status of cell 1 to cell 12 (respectively). “1” indicates balancing is enabled for this cell. “0” indicates that balancing is turned off. FN8830.1 June 16, 2016 ISL78610 Device Commands BASE ADDR (PAGE) ACCESS ADDRESS RANGE 3’b011 Read Only 6’h01 - 6’h14 PAGE ADDR 3’b011 REGISTER ADDRESS DESCRIPTION Device commands. Actions and communications administration. Not physical registers but memory mapped device commands. Commands from host and device responses are all configured as reads (BASE ADDR MSB = 0). Write operations breaks the communication rules and produce NAK from the target device. DESCRIPTION 6’h01 Scan Voltages. Device responds by scanning VBAT and all 12-cell voltages and storing the results in local memory. 6’h02 Scan Temperatures. Device responds by scanning external temperature inputs, internal temperature, and the secondary voltage reference, and storing the results in local memory. 6’h03 Scan Mixed. Device responds by scanning VBAT, cell and ExT1 voltages and storing the results in local memory. The ExT1 measurement is performed in the middle of the cell voltage scans to minimize measurement latency between the cell voltages and the voltage on ExT1. 6’h04 Scan Wires. Device responds by scanning for pin connection faults and stores the results in local memory. 6’h05 Scan All. Device responds by performing the functions of the Scan Voltages, Scan temperatures, and Scan Wires commands in sequence. Results are stored in local memory 6’h06 Scan Continuous. Places the device in Scan Continuous mode by setting the Device Setup register SCAN bit. 6’h07 Scan Inhibit. Stops Scan Continuous mode by clearing the Device Setup register SCAN bit. 6’h08 Measure. Device responds by measuring a targeted single parameter (cell voltage/VBAT/external or internal temperatures or secondary voltage reference). 6’h09 Identify. Special mode function used to determine device stack position and address. Devices record their own stack address and the total number of devices in the stack. See “Identify Command” on page 49 for details. 6’h0A Sleep. Places the part in Sleep mode (wake up via daisy comms). See “Communication Timing” on page 60. 6’h0B NAK. Device response if communications is not recognized. The device responds NAK down the daisy chain to the host microcontroller. The host microcontroller typically retransmits on receiving a NAK. 6’h0C ACK. Used by host microcontroller to verify communications without changing anything. Devices respond with ACK. 6’h0E Comms Failure. Used in daisy chain implementations to communicate comms failure. If a communication is not acknowledged by a stack device, the last stack device that did receive the communication responds with Comms Failure. This is part of the communications integrity checking. Devices downstream of a communications fault are alerted to the fault condition by the watchdog function. 6’h0F Wake-up. Used in daisy chain implementations to wake up a sleeping stack of devices. The Wake-up command is sent to the bottom stack device (master device) via SPI. The master device then wakes up the rest of the stack by transmitting a low frequency clock. The top stack device responds ACK once it is awake. See “Wake Command” on page 44. 6’h10 Balance Enable. Enables cell balancing by setting BEN. May be used to enable cell balancing on all devices simultaneously using the address All Stack Address 1111. 6’h11 Balance Inhibit. Disables cell balancing by clearing BEN. May be used to disable cell balancing on all devices simultaneously using the address All Stack Address 1111. 6’h12 Reset. Resets all digital registers to its power-up state (i.e., reloads the factory programmed configuration data from nonvolatile memory. Stops all scan and balancing activity. Daisy chain devices must be reset in sequence starting with the top stack device and proceeding down the stack to the bottom (master) device. The Reset command must be followed by an Identify command (daisy chain configuration) before volatile registers can be rewritten. 6’h13 Calculate register checksum. Calculates the checksum value for the current Page 2 register contents (registers with base address 0010). See “System Hardware Connection” on page 22. 6’h14 Check register checksum. Verifies the register contents are correct for the current checksum. An incorrect result sets the PAR bit in the Fault status register which starts a standard fault response. See “System Hardware Connection” on page 22. Submit Document Feedback 92 FN8830.1 June 16, 2016 ISL78610 Nonvolatile Memory (EEPROM) Checksum A checksum is provided to verify the contents of EEPROM memory. Two registers are provided. The MISR register (Table 68) contains the correct checksum value, which is calculated during factory testing at Intersil. The MISR Shadow register contains the checksum value that is calculated each time the nonvolatile memory is loaded to shadow registers, either after a power cycle or after a device reset. See also “Fault Diagnostics” on page 76. TABLE 68. MISR REGISTER BASE ADDR (PAGE) ACCESS ADDRESS RANGE 100 Read Only 6’h3F Nonvolatile memory Multiple Input Shift Register (MISR) register. This checksum value for the nonvolatile memory contents. It is programmed during factory testing at Intersil. 101 Read Only 6’h00 MISR shadow register checksum value. This value is calculated when shadow registers are loaded from nonvolatile memory either after a power cycle or a reset. DESCRIPTION Register Map R/W + PAGE READ 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 WRITE BIT 7 ADDRESS 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 Submit Document Feedback BIT 6 REGISTER NAME VBAT Voltage Cell 1 Voltage Cell 2 Voltage Cell 3 Voltage Cell 4 Voltage Cell 5 Voltage Cell 6 Voltage Cell 7 Voltage Cell 8 Voltage Cell 9 Voltage Cell 10 Voltage Cell 11 Voltage Cell 12 Voltage 93 VB7 C1V7 C2V7 C3V7 C4V7 C5V7 C6V7 C7V7 C8V7 C9V7 C10V7 C11V7 C12V7 VB6 C1V6 C2V6 C3V6 C4V6 C5V6 C6V6 C7V6 C8V6 C9V6 C10V6 C11V6 C12V6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 VB5 VB4 VB3 VB2 VB1 VB0 VB13 VB12 VB11 VB10 VB9 VB8 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 C1V13 C1V12 C1V11 C1V10 C1V9 C1V8 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 C2V13 C2V12 C2V11 C2V10 C2V9 C2V8 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0 C3V13 C3V12 C3V11 C3V10 C3V9 C3V8 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0 C4V13 C4V12 C4V11 C4V10 C4V9 C4V8 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0 C5V13 C5V12 C5V11 C5V10 C5V9 C5V8 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0 C6V13 C6V12 C6V11 C6V10 C6V9 C6V8 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0 C7V13 C7V12 C7V11 C7V10 C7V9 C7V8 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0 C8V13 C8V12 C8V11 C8V10 C8V9 C8V8 C9V5 C9V4 C9V3 C9V2 C9V1 C9V0 C9V13 C9V12 C9V11 C9V10 C9V9 C9V8 C10V5 C10V4 C10V3 C10V2 C10V1 C10V0 C10V13 C10V12 C10V11 C10V10 C10V9 C10V8 C11V5 C11V4 C11V3 C11V2 C11V1 C11V0 C11V13 C11V12 C11V11 C11V10 C11V9 C11V8 C12V5 C12V4 C12V3 C12V2 C12V1 C12V0 C12V13 C12V12 C12V11 C12V10 C12V9 C12V8 FN8830.1 June 16, 2016 ISL78610 Register Map (Continued) R/W + PAGE READ WRITE BIT 7 ADDRESS REGISTER NAME 0001 001111 All Cell Voltage Data 0001 010000 IC Temperature 0001 010001 010010 0001 0001 010011 010100 0001 010101 0001 External Temperature Input 2 Voltage (ExT2 pin) ET2V7 External Temperature Input 3 Voltage (ExT3 pin) ET3V7 External Temperature Input 4 Voltage (ExT4 pin) ET4V7 Secondary Reference Voltage RV7 Scan Count 0001 011111 All Temperature Data 000000 Overvoltage Fault 0010 0010 0010 0010 0010 0010 1010 1010 1010 1010 1010 1010 1010 0010 0010 1010 000001 000010 000011 000100 000101 Undervoltage Fault Open-Wire Fault Fault Setup Fault Status Cell Setup 000110 Over-Temperature Fault 001111 All Fault Data 010000 Overvoltage Limit Submit Document Feedback ICT7 ET1V7 010110 94 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 Daisy chain configuration only. This command returns all Page 1 data from address 6’h00 through 6’h0C in a single data stream. See “Communication Sequences” on page 56 and “System Out of Limit Detection” on page 72. See example in Figure 70D on page 60. External Temperature Input 1 Voltage (ExT1 pin) 0001 0010 BIT 6 ICT6 ET1V6 ET2V6 ET3V6 ET4V6 RV6 ICT5 ICT4 ICT3 ICT2 ICT1 ICT0 ICT13 ICT12 ICT11 ICT10 ICT9 ICT8 ET1V5 ET1V4 ET1V3 ET1V2 ET1V1 ET1V0 ET1V13 ET1V12 ET1V11 ET1V10 ET1V9 ET1V8 ET2V5 ET2V4 ET2V3 ET2V2 ET2V1 ET2V0 ET2V13 ET2V12 ET2V11 ET2V10 ET2V9 ET2V8 ET3V5 ET3V4 ET3V3 ET3V2 ET3V1 ET3V0 ET3V13 ET3V12 ET3V11 ET3V10 ET3V9 ET3V8 ET4V5 ET4V4 ET4V3 ET4V2 ET4V1 ET4V0 ET4V13 ET4V12 ET4V11 ET4V10 ET4V9 ET4V8 RV5 RV4 RV3 RV2 RV1 RV0 RV13 RV12 RV11 RV10 RV9 RV8 SCN3 SCN2 SCN1 SCN0 Daisy chain configuration only. This command returns all Page 1 data from address 6’h10 through 6’h16 in a single data stream. See “Communication Sequences” on page 56 and “System Out of Limit Detection” on page 72. OF8 UF8 OC7 TOT2 OW C8 OF7 UF7 OC6 TOT1 UV C7 OF6 OF4 OF3 OF2 OF1 OF12 OF11 OF10 OF9 UF4 UF3 UF2 UF1 UF12 UF11 UF10 UF9 OC4 OC3 OC2 OC1 OC0 OC12 OC11 OC10 OC9 OC8 WSCN SCN3 SCN2 SCN1 SCN0 TTST4 TTST3 TTST2 TTST1 TTST0 OV OT WDGF OSC 0 0 MUX REG REF PAR OVSS OVBAT C6 C5 C4 C3 C2 C1 FFSN FFSP C12 C11 C10 C9 TFLT4 TFLT3 TFLT2 TFLT1 TFLT0 UF6 OC5 TOT0 OF5 UF5 Daisy chain configuration only. This command returns all Page 2 data from address 6’h00 through 6’h06 in a single data stream. See “Communication Sequences” on page 56 and “System Out of Limit Detection” on page 72. OV7 OV6 OV5 OV4 OV3 OV2 OV1 OV0 OV13 OV12 OV11 OV10 OV9 OV8 FN8830.1 June 16, 2016 ISL78610 Register Map (Continued) R/W + PAGE BIT 7 READ WRITE ADDRESS 0010 1010 010001 0010 0010 0010 0010 0010 0010 1010 1010 1010 1010 1010 1010 0010 0010 010010 010011 010100 010101 010110 010111 011000 1010 0010 011001 011010 0010 011011 0010 011100 011101 0010 BIT 6 REGISTER NAME Undervoltage Limit External Temp Limit Balance Setup UV7 ETL7 BSP2 Balance Status (Cells to Balance) Watchdog/Balance Time User Register BAL8 BTM0 UR7 User Register UR21 Comms Setup SIZE3 Device Setup BDDS Internal Temp Limit Serial Number 0 Serial Number 1 ITL7 SN7 SN21 UV6 ETL6 BSP1 BAL7 WDG6 UR6 UR20 SIZE2 0 ITL6 SN6 SN20 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 UV5 UV4 UV3 UV2 UV1 UV0 UV13 UV12 UV11 UV10 UV9 UV8 ETL5 ETL4 ETL3 ETL2 ETL1 ETL0 ETL13 ETL12 ETL11 ETL10 ETL9 ETL8 BSP0 BWT2 BWT1 BWT0 BMD1 BMD0 BEN BSP3 BAL6 0010 0010 0010 0010 1010 1010 1010 1010 100000 Cell 1 Balance Value 0 100011 Submit Document Feedback Cell 2 Balance Value 0 Cell 2 Balance Value 1 ~ 95 BAL1 BAL12 BAL11 BAL10 BAL9 WDG3 WDG2 WDG1 WDG0 BTM6 BTM5 BTM4 BTM3 BTM2 BTM1 UR5 UR4 UR3 UR2 UR1 UR0 UR13 UR12 UR11 UR10 UR9 UR8 UR19 UR18 UR17 UR16 UR15 UR14 UR27 UR26 UR25 UR24 UR23 UR22 SIZE1 SIZE0 ADDR3 ADDR2 ADDR1 ADDR0 CRAT1 CRAT0 CSEL2 CSEL1 ISCN SCAN EOB 0 Pin 37 Pin 39 WP5 WP4 WP3 WP2 WP1 WP0 ITL5 ITL4 ITL3 ITL2 ITL1 ITL0 ITL13 ITL12 ITL11 ITL10 ITL9 ITL8 SN5 SN4 SN3 SN2 SN1 SN0 SN13 SN12 SN11 SN10 SN9 SN8 SN19 SN18 SN17 SN16 SN15 SN14 SN27 SN26 SN25 SN24 SN23 SN22 TV2 TV1 TV0 TV4 TV3 Daisy chain configuration only. This command returns all Page 2 data from address 6’h10 through 6’h1D in a single data stream. See “Communication Sequences” on page 56 and “System Out of Limit Detection” on page 72. Cell 1 Balance Value 1 ~ BAL2 RESERVED All Setup Data 100010 BAL3 WDG4 Trim Voltage 011111 100001 BAL4 WDG5 TV5 0010 BAL5 B0107 B0121 B0207 B0221 B0106 B0120 B0206 B0220 B0105 B0104 B0103 B0102 B0101 B0100 B0113 B0112 B1011 B0110 B0109 B0108 B0119 B0118 B0117 B0116 B0115 B0114 B0127 B0126 B0125 B0124 B0123 B0122 B0205 B0204 B0203 B0202 B0201 B0200 B0213 B0212 B1011 B0210 B0209 B0208 B0219 B0218 B0217 B0216 B0215 B0214 B0227 B0226 B0225 B0224 B0223 B0222 ~ FN8830.1 June 16, 2016 ISL78610 Register Map (Continued) R/W + PAGE BIT 7 READ WRITE ADDRESS 0010 1010 110111 0010 0010 0010 0010 111000 111001 111010 111011 BIT 6 REGISTER NAME Cell 12 Balance Value 1 Reference Coefficient C Reference Coefficient B Reference Coefficient A Cell Balance Enabled B1221 RCC7 RCB7 RCA2 CBEN8 B1220 RCC6 RCB6 RCA1 CBEN7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 B1219 B1218 B1217 B1216 B1215 B1214 B1227 B1226 B1225 B1224 B1223 B1222 RCC5 RCC4 RCC3 RCC2 RCC1 RCC0 RCC13 RCC12 RCC11 RCC10 RCC9 RCC8 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 RCB13 RCB12 RCB11 RCB10 RCB9 RCB8 RCA0 RESERVED RCA8 RCA7 RCA6 RCA5 RCA4 RCA3 CBEN6 CBEN5 CBEN4 CBEN3 BAL2 CBEN1 CBEN12 CBEN11 CBEN10 CBEN9 0011 000001 Scan Voltages 0011 000010 Scan Temperatures 0011 000011 Scan Mixed 0011 000100 Scan Wires 0011 000101 Scan All 0011 000110 Scan Continuous 0011 000111 Scan Inhibit 0011 001000 Measure 0011 001001 Identify 0011 001010 Sleep 0011 001011 NAK 0011 001100 ACK 0011 001110 Comms Failure 0011 001111 Wake-up 0011 010000 Balance Enable 0011 010001 Balance Inhibit 0011 010010 Reset 0011 010011 Calc Register Checksum 0011 010100 Check Register Checksum 0100 111111 EEPROM MISR Data Register 14-bit MISR EEPROM checksum value. Programmed during test. 0101 000000 MISR Calculated Checksum 14-bit shadow register MISR checksum value. Calculated when shadow registers are loaded from nonvolatile memory. Submit Document Feedback 96 FN8830.1 June 16, 2016 ISL78610 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE June 16, 2016 FN8830.1 Updated ESD specification references to AEC on page 8. On page 15 in the “Performance Characteristics” tables updated the following MIN/MAX values: Initial Cell Reading Error -Minimum from “-3” to “-3.2” Maximum from “3” to “3.2” Initial VBAT Reading Error -Minimum from “-105” to “-175” Maximum from “105” to “175” -Minimum from “-175” to “-300” Maximum from “175” to “300” Initial Cell Monitor Voltage Error -Minimum from “-15” to “-12” Maximum from “-15” to “12” Initial VBAT Reading Error -Minimum from “-155” to “-250” Maximum from “155” to “250” -Minimum from “-285” to “-425” Maximum from “285” to “425” Replaced Figures 5 through 13 based on new bench board characterization. April 12, 2016 FN8830.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 97 FN8830.1 June 16, 2016 ISL78610 Package Outline Drawing Q64.10x10D 64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE Rev 2, 9/12 12.00 4 5 10.00 D 3 12.00 A 10.00 4 5 B 0.50 3 4X 0.20 C A-B D TOP VIEW 4X 0.20 H A-B D BOTTOM VIEW 1.20 MAX 11/13° 0.05 / / 0.10 C C SIDE VIEW 7 0.08 SEE DETAIL "A" 0° MIN. H 3 0.08 M C A-B D WITH LEAD FINISH 0.22 ±0.05 0.09/0.20 2 1.00 ±0.05 0.05/0.15 0.09/0.16 0.08 R. MIN. 0.20 MIN. 0.20 ±0.03 BASE METAL DETAIL "A" SCALE: NONE 0.25 0-7° GAUGE PLANE 0.60 ±0.15 (1.00) NOTES: 1. All dimensioning and tolerancing conform to ANSI Y14.5-1982. 2. Datum plane H located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Datums A-B and D to be determined at centerline between leads where leads exit plastic body at datum plane H. 4. Dimensions do not include mold protrusion. Allowable mold protrusion is 0.254mm. 5. These dimensions to be determined at datum plane H. 6. Package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. 7. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total at maximum material condition. Dambar cannot be located on the lower radius or the foot. 8. Controlling dimension: millimeter. 9. This outline conforms to JEDEC publication 95 registration MS-026, variation ACD. 10. Dimensions in ( ) are for reference only. Submit Document Feedback 98 FN8830.1 June 16, 2016