SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES295N – JUNE 2000 – REVISED SEPTEMBER 2003 D D D D D D D D D DBV OR DCK PACKAGE (TOP VIEW) Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Input and Open-Drain Output Accept Voltages Up To 5.5 V Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) NC A GND 1 5 VCC 4 Y 2 3 NC – No internal connection YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW) GND A DNU 3 4 Y 2 1 5 VCC DNU – Do not use description/ordering information This single inverter buffer/driver is designed for 1.65-V to 5.5-V VCC operation. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. The output of the SN74LVC1G06 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar – WCSP (DSBGA) 0.17-mm Small Bump – YEA NanoFree – WCSP (DSBGA) 0.17-mm Small Bump – YZA (Pb-free) NanoStar – WCSP (DSBGA) 0.23-mm Large Bump – YEP C –40°C –40 C to 85 85°C SN74LVC1G06YEAR SN74LVC1G06YZAR Reel of 3000 SOT (SC-70) – DCK _ _ _CT_ SN74LVC1G06YEPR NanoFree – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) SOT (SOT-23) – DBV TOP-SIDE MARKING‡ SN74LVC1G06YZPR Reel of 3000 SN74LVC1G06DBVR Reel of 250 SN74LVC1G06DBVT Reel of 3000 SN74LVC1G06DCKR Reel of 250 SN74LVC1G06DCKT C06_ CT_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES295N – JUNE 2000 – REVISED SEPTEMBER 2003 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff.The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUT A OUTPUT Y H L L H logic diagram (positive logic) A 2 4 Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES295N – JUNE 2000 – REVISED SEPTEMBER 2003 recommended operating conditions (see Note 4) VCC VIH Operating Supply voltage Data retention only MAX 5.5 UNIT V 1.5 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage MIN 1.65 1.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V 2 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VIL Low-level input voltage VI VO Input voltage 0 5.5 V Output voltage 0 5.5 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0.3 × VCC VCC = 1.65 V VCC = 2.3 V IOL ∆t/∆v t/ v Low-level output current 4 8 mA 16 VCC = 3 V Input transition rise or fall rate V 0.8 24 VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 32 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 10 20 ns/V 5 TA Operating free-air temperature –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 5.5 V IOL = 100 mA IOL = 4 mA IOL = 8 mA IOL = 16 mA VOL ICC ∆ICC Ci A input TYP† MAX 1.65 V 0.45 2.3 V 0.3 0.4 VI or VO = 5.5 V VI = 5.5 V or GND, One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND 0.55 0 to 5.5 V ±5 mA 0 ±10 mA 1.65 V to 5.5 V 10 mA 3 V to 5.5 V 500 mA VI = VCC or GND VO = VCC or GND Co † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 V 0.55 4.5 V IOL = 32 mA VI = 5.5 V or GND UNIT 0.1 3V IOL = 24 mA II Ioff MIN • DALLAS, TEXAS 75265 3.3 V 4 pF 3.3 V 5 pF 3 SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES295N – JUNE 2000 – REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A Y tpd VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.2 6.5 1.1 4 1.2 4 1 3 ns operating characteristics, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V TYP VCC = 2.5 V TYP f = 10 MHz 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 VCC = 3.3 V TYP 4 VCC = 5 V TYP 6 UNIT pF SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES295N – JUNE 2000 – REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION (OPEN DRAIN) From Output Under Test VLOAD Open S1 RL TEST GND RL CL (see Note A) S1 tPZL (see Notes E and F) tPLZ (see Notes E and G) VLOAD VLOAD tPHZ/tPZH VLOAD LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns VCC VCC 3V VCC VLOAD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC CL RL V∆ 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI VM Input VM th VM Data Input VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input 0V tPHL Output VM VOL Output tPLZ VLOAD/2 VM VM VOL Output Waveform 2 S1 at VLOAD (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ tPZH VOH VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL VOH VM VI Output Control VM tPLH VI VM VLOAD/2 VLOAD/2 – V∆ ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MECHANICAL DATA MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002 DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 5 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-2/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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