SCES467A − JULY 2003 − REVISED MAY 2004 D Qualification in Accordance With D D D D D D Low Power Consumption, 10-µA Max ICC D ±24-mA Output Drive at 3.3 V D Ioff Supports Partial-Power-Down Mode AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D DBV PACKAGE (TOP VIEW) OE A GND † Contact factory for details. Q100 qualification data available on request. 1 5 VCC 4 Y 2 3 description/ordering information This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE‡ PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING§ −40°C to 125°C SOT (SOT-23) − DBV Reel of 3000 1P1G126QDBVRQ1 C26_ ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. § DBV: The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUTS OE A OUTPUT Y H H H H L L L X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES467A − JULY 2003 − REVISED MAY 2004 logic diagram (positive logic) 1 OE A 2 4 Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES467A − JULY 2003 − REVISED MAY 2004 recommended operating conditions (see Note 4) Operating VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI VO Input voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V ∆t/∆v Low-level output current Input transition rise or fall rate 5.5 0.65 × VCC 1.7 V 2 0.7 × VCC 0.35 × VCC 0.7 0.8 V 0.3 × VCC 0 5.5 V 0 VCC −4 V −8 mA −24 −24 4 8 16 VCC = 3 V UNIT V 1.5 −16 VCC = 3 V VCC = 4.5 V VCC = 1.65 V IOL 1.65 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Output voltage High-level output current MAX VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 1.65 V VCC = 2.3 V IOH MIN mA 24 VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 24 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 10 20 ns/V 5 TA Operating free-air temperature −40 125 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES467A − JULY 2003 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −100 mA IOH = −4 mA MIN 1.65 V to 5.5 V 1.65 V VCC−0.1 1.2 2.3 V 1.9 IOH = −8 mA IOH = −16 mA VOH IOL = 100 mA IOL = 4 mA 0.1 0.45 2.3 V 0.3 0.4 3V VI = 5.5 V or GND VI or VO = 5.5 V 0.55 ±5 mA 0 ±10 mA 3.6 V 10 mA 1.65 V to 5.5 V 10 mA 500 mA 0 to 5.5 V VO = 0 to 5.5 V VI = 5.5 V or GND, ∆ICC One input at VCC − 0.6 V, Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. IO = 0 Other inputs at VCC or GND V 0.55 4.5 V IOL = 24 mA IOZ ICC 3.8 1.65 V IOL = 24 mA A or OE inputs V 1.65 V to 5.5 V IOL = 8 mA IOL = 16 mA UNIT 2.3 4.5 V IOH = −24 mA II Ioff MAX 2.4 3V IOH = −24 mA VOL TYP† VCC 3 V to 5.5 V 3.3 V 4 pF switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) FROM (INPUT) TO (OUTPUT) tpd A ten tdis PARAMETER VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX Y 1 5.8 1 4.5 ns OE Y 1.2 5.8 1 5 ns OE Y 1 6 1 4.2 ns operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd 4 Outputs enabled Power dissipation capacitance Outputs disabled POST OFFICE BOX 655303 f = 10 MHz • DALLAS, TEXAS 75265 VCC = 3.3 V TYP VCC = 5 V TYP 19 21 3 4 UNIT pF SCES467A − JULY 2003 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf 3V VCC ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ 1.5 V VCC/2 6V 2 × VCC 50 pF 50 pF 500 Ω 500 Ω 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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