74CBTLV3253-Q100 Dual 1-of-4 multiplexer/demultiplexer Rev. 1 — 3 April 2013 Product data sheet 1. General description The 74CBTLV3253-Q100 provides a dual 1-of-4 high-speed multiplexer/demultiplexer with two common select inputs (S0, S1) and two output enable inputs (1OE, 2OE). The low ON resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. When pin nOE = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin nOE = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 and S1. To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the VCC through a pull-up resistor. The current-sinking capability of the driver determines the minimum value of the resistor. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A IOFF circuitry provides partial Power-down mode operation Multiple package options 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number Package 74CBTLV3253D-Q100 Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74CBTLV3253PW-Q100 40 C to +125 C 40 C to +125 C 74CBTLV3253BQ-Q100 DHVQFN16 plastic dual-in-line compatible thermal SOT763-1 enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm 4. Functional diagram 1A 6 7 5 4 3 2A 10 9 11 12 13 S0 S1 1OE 2OE 1B1 1B2 1B3 1B4 2B1 2B2 2B3 2B4 14 2 1 15 001aal208 Fig 1. Logic diagram 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 2 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 5. Pinning information 5.1 Pinning % 6 % % % % % % $ % *1' $ &%7/94 9&& 2( 6 2( 6 2( 9&& % 6 2( % % % 6 % % % % % % % % % $ $ % *1' $ % % DDD 7UDQVSDUHQWWRSYLHZ DDD DDD *1' $ 6 WHUPLQDO LQGH[DUHD 9&& *1' 2( 2( &%7/94 &%7/94 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 2. Pin configuration SOT109-1 (SO16) Fig 3. Pin configuration SOT403-1 (TSSOP16) Fig 4. Pin configuration SOT763-1 (DHVQFN16) 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE 1, 15 output enable input (active LOW) S0, S1 14, 2 select input 1B1 to 1B4 6, 5, 4, 3 B input/output 2B1 to 2B4 10, 11, 12, 13 B input/output GND 8 ground (0 V) 1A, 2A 7, 9 A input/output VCC 16 supply voltage 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 3 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 6. Functional description Table 3. Function table[1] Inputs Function switch 1OE 2OE S1 S0 X H X X disconnect 2A and 2Bn H X X X disconnect 1A and 1Bn L L L L 1A to 1B1 and 2A to 2B1 L L L H 1A to 1B2 and 2A to 2B2 L L H L 1A to 1B3 and 2A to 2B3 L L H H 1A to 1B4 and 2A to 2B4 [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage input voltage VI Conditions Min Max Unit 0.5 +4.6 V control inputs [1] 0.5 +4.6 V [2] VSW switch voltage enable and disable mode 0.5 VCC + 0.5 V IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.5 V 50 - mA ISW switch current VSW = 0 V to VCC - 128 mA ICC supply current - +100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot Tamb = 40 C to +125 C [3] [1] The minimum input voltage rating may be exceeded if the input clamping current ratings are observed. [2] The switch voltage ratings may be exceeded if switch clamping current ratings are observed [3] For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN16 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC VI VSW switch voltage Tamb ambient temperature t/V [1] Conditions Min Max Unit supply voltage 2.3 3.6 V input voltage 0 3.6 V 0 VCC V 40 +125 C 0 200 ns/V enable and disable mode input transition rise and fall rate VCC = 2.3 V to 3.6 V [1] Applies to control signal levels. 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 4 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - V LOW-level input VCC = 2.3 V to 2.7 V voltage VCC = 3.0 V to 3.6 V - - 0.7 - 0.7 V - - 0.9 - 0.9 V II input leakage current - - 1 - 20 A IS(OFF) OFF-state VCC = 3.6 V; see Figure 5 leakage current - - 1 - 20 A IS(ON) ON-state VCC = 3.6 V; see Figure 6 leakage current - - 1 - 20 A IOFF power-off VI or VO = 0 V to 3.6 V; leakage current VCC = 0 V - - 10 - 50 A ICC supply current VI = GND or VCC; IO = 0 A; VSW = GND or VCC; VCC = 3.6 V - - 10 - 50 A ICC additional supply current pin nOE; VI = VCC 0.6 V; VSW = GND or VCC; VCC = 3.6 V - - 300 - 2000 A CI input capacitance pin nOE; VCC = 3.3 V; VI = 0 V to 3.3 V - 0.9 - - - pF CS(OFF) OFF-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 5.2 - - - pF CS(ON) ON-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 20.0 - - - pF HIGH-level input voltage VIH VIL pin nOE; VI = GND to VCC; VCC = 3.6 V [1] All typical values are measured at Tamb = 25 C. [2] One input at 3 V, other inputs at VCC or GND. [2] 9.1 Test circuits VCC VCC nOE VIH A Vl nOE VIL Is nBn nA Is Is A A GND VO Vl 001aai101 Product data sheet GND VO VI = VCC or GND and VO = open circuit. Test circuit for measuring OFF-state leakage current (one switch) 74CBTLV3253_Q100 nBn 001aai103 VI = VCC or GND and VO = GND or VCC. Fig 5. nA Fig 6. Test circuit for measuring ON-state leakage current (one switch) All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 5 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 9.2 ON resistance Table 7. Resistance RON At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter RON Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 64 mA; VI = 0 V - 4.2 8.0 - 15.0 ISW = 24 mA; VI = 0 V - 4.2 8.0 - 15.0 ISW = 15 mA; VI = 1.7 V - 8.4 40.0 - 60.0 ISW = 64 mA; VI = 0 V - 4.0 7.0 - 11.0 ISW = 24 mA; VI = 0 V - 4.0 7.0 - 11.0 ISW = 15 mA; VI = 2.4 V - 6.2 15.0 - 25.5 [2] ON resistance VCC = 2.3 V to 2.7 V; see Figure 8 to Figure 10 VCC = 3.0 V to 3.6 V; see Figure 11 to Figure 13 [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 9.3 ON resistance test circuit and graphs 001aai109 11 RON (Ω) 9 VSW V 7 VCC (1) nOE VIL (2) 5 nA Vl nBn GND (3) (4) ISW 3 0 0.5 1.0 1.5 2.0 2.5 VI (V) 001aai104 (1) Tamb = 125 C. RON = VSW / ISW. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 7. Test circuit for measuring ON resistance (one switch) 74CBTLV3253_Q100 Product data sheet Fig 8. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 15 mA All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 6 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 001aai110 11 001aai111 11 RON (Ω) RON (Ω) 9 9 7 7 (1) (1) (2) 5 (2) 5 (3) (3) (4) (4) 3 3 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 9. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 24 mA Fig 10. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 64 mA 001aai105 8 2.5 VI (V) 001aai106 8 RON (Ω) RON (Ω) 6 6 (1) (1) (2) (2) (3) 4 (3) 4 (4) (4) 2 2 0 1 2 3 4 0 1 VI (V) (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 11. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 15 mA Product data sheet 3 4 VI (V) (1) Tamb = 125 C. 74CBTLV3253_Q100 2 Fig 12. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 24 mA All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 7 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 001aai107 7.5 RON (Ω) 6.5 5.5 (1) (2) 4.5 (3) 3.5 (4) 2.5 0 1 2 3 4 VI (V) (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 8 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 16 Symbol Parameter tpd Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - - 0.15 - 0.25 ns - - 0.15 - 0.25 ns 1.0 2.2 6.8 1.0 7.5 ns 1.0 2.0 5.5 1.0 6.1 ns 1.0 2.1 5.0 1.0 5.5 ns 1.0 1.9 4.8 1.0 5.3 ns VCC = 2.3 V to 2.7 V 1.0 2.1 4.3 1.0 4.7 ns VCC = 3.0 V to 3.6 V 1.0 1.9 4.0 1.0 4.4 ns VCC = 2.3 V to 2.7 V 1.0 2.6 5.5 1.0 6.1 ns VCC = 3.0 V to 3.6 V 1.0 3.2 5.4 1.0 5.9 ns VCC = 2.3 V to 2.7 V 0.8 2.0 4.8 0.8 5.3 ns VCC = 3.0 V to 3.6 V 1.0 2.0 4.5 1.0 5.0 ns propagation delay nA to nBn or nBn to nA; see Figure 14 [2][3] VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Sn to nA; see Figure 14 [3] VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V ten enable time [4] nOE to nA or nBn; see Figure 15 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Sn to nBn; see Figure 15 tdis disable time [4] [5] nOE to nA or nBn; see Figure 15 Sn to nBn; see Figure 15 [5] [1] All typical values are measured at Tamb = 25 C and at nominal VCC. [2] The propagation delay is the calculated RC time constant of the on-state resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance). [3] tpd is the same as tPLH and tPHL. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPHZ and tPLZ. 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 9 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 11. Waveforms VI input VM VM 0V tPHL tPLH VOH VM output VM VOL 001aai367 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 14. The data input (nA or nBn) to output (nBn or nA) propagation delays Table 9. Measurement points Supply voltage Input VCC VM VI tr = tf Output VM VX VY 2.3 V to 2.7 V 0.5VCC VCC 2.0 ns 0.5VCC VOL + 0.15 V VOH 0.15 V 3.0 V to 3.6 V 0.5VCC VCC 2.0 ns 0.5VCC VOL + 0.3 V VOH 0.3 V VI VM nOE, Sn input VM GND tPZL tPLZ VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPZH tPHZ VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND switch enabled switch disabled switch enabled 001aal212 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 15. Enable and disable times 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 10 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 16. Test circuit for measuring switching times Table 10. Test data Supply voltage Load VCC CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 2.3 V to 2.7 V 30 pF 500 open GND 2VCC 3.0 V to 3.6 V 50 pF 500 open GND 2VCC 74CBTLV3253_Q100 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 11 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT109-1 (SO16) 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 12 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 18. Package outline SOT403-1 (TSSOP16) 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 13 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 19. Package outline SOT763-1 (DHVQFN16) 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 14 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date 74CBTLV3253_Q100 v.1 20130403 74CBTLV3253_Q100 Product data sheet Data sheet status Change notice Supersedes Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 15 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74CBTLV3253_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 16 of 18 74CBTLV3253-Q100 NXP Semiconductors Dual 1-of-4 multiplexer/demultiplexer No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74CBTLV3253_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 April 2013 © NXP B.V. 2013. All rights reserved. 17 of 18 NXP Semiconductors 74CBTLV3253-Q100 Dual 1-of-4 multiplexer/demultiplexer 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 9.1 9.2 9.3 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 April 2013 Document identifier: 74CBTLV3253_Q100