ISL1903 Datasheet

ODUCT
OBSOLETE PR
MENT
DED REPLACE
NO RECOMMEN
enter at
nical Support C
contact our Tech www.intersil.com/tsc
or
1-888-INTERSIL
Dimmable Buck LED Driver - AC Mains or DC Input LED
Driver
ISL1903
Features
The ISL1903 is a high-performance, critical conduction mode
(CrCM), single-ended buck LED driver controller. It may be used
with DC input converters, but also supports single-stage
conversion of the AC mains to a constant current source with
power factor correction (PFC). The ISL1903 supports buck
converter topologies, such as isolated forward converters or
non-isolated source return buck converters. Operation in CrCM
allows near zero-voltage switching (ZVS) for improved
efficiency while maximizing magnetic core utilization.
• Excellent LED current regulation over line, load, and
temperature
The ISL1903 is compatible with both leading and trailing edge
modulated AC mains dimmers. It provides all of the features
required for high-performance dimmable LED ballast designs.
• Supports Universal AC Mains Input
Applications
• Monitors FET switching current for load regulation
• 0 - 100% dimming with leading-edge (triac) and
trailing-edge dimmers
• Power factor correction for up to 0.995 power factor and
less than 20% harmonic content
• Critical conduction mode (CrCM) operation for
quasi-resonant high efficiency performance
• Configurable for PWM or DC current dimming control of
LEDs
• Industrial and commercial LED lighting
• Supports isolated and non-isolated buck topologies
• Retrofit LED lamps with triac dimming
• Closed loop soft-start for no overshoot
• Universal AC mains input LED retrofit lamps
• OFFREF feature to set dimming off-point to improve fixture
performance matching
• AC or DC input LED ballasts
• -40°C to +125°C operation
• Pb-free (RoHS compliant)
100
90
14
5
VDD
CS+
LED CURRENT (%)
80
1
Dimmer
AC Mains
8
DELADJ
13
GND
3
VREF
60
AC
12
OUT
16
OC
6
VERR
9
20
FB
7
10
DHC
ISL1903
EMI Filter
70
RAMP
IOUT
10
4
50
40
30
0
100
90
80
70
60
50
40
30
20
10
0
CONDUCTION ANGLE (%)
FIGURE 1A. BOOST-RETURN (BUCK) TOPOLOGY
FIGURE 1B. CURRENT vs AC CONDUCTION ANGLE
FIGURE 1. ISL1903 APPLICATION PERFORMANCE
September 20, 2012
FN8285.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram - ISL1903
VREF
BIAS AND
REFERENCE
GENERATOR
VDD
UVLO
+
OTP
SHUTDOWN
150°C TO 170°C
BG
GND
BIAS/UVLO/OTP
DHC
2
DUTY CYCLE TO
VOLTAGE CONVERTER
LOW PASS FILTER
REFERENCE OUT
DIMMING PWM
MASTER
OSCILLATOR
PWMOUT
+
REF
PEAK
DETECTOR
AC DETECTION
REFINBUFF
AC-PRESENT
+
MINIMUM DIMMING LEVEL
CONTROL
OFFREF
OUT
+
-
PRIMARY CURRENT
SENSE PROCESSOR
IOUT
CS+
-
INHIBIT
INHIBIT
+
IOUT
-
REFERENCE SS
+
+
_
ISENSE
+
- 1.50V
REFERENCE
SS BUFFER
DELADJ
SS
QUASI-ZVS
DELAY
+
CRCM
DETECTOR
OC
LEADING
EDGE
BLANKING
600mV
+
-
PRIMARY OC
RAMP
200mV
FMIN
CLAMP
FMAX
CLAMP
SS/5
VERR/5
+
-
PWM
S
Q
R
Q
300ms
SOFT-START
ENABLE
VERR CLAMP
+
PWM LATCH
SS LOW
PWM
COMPARATOR
+
-
0.25V
SS
1/5
1/5
FAULT LATCH
REFINBUFF
FN8285.1
September 20, 2012
EA1
+
VERR
CRCM OSCILLATOR/PWM/ERROR AMPLIFIERS
VERR
FB1
SOFT-START/POR/OVP
S
Q
R
Q
OVP
ISL1903
AC
TRIANGLE WAVE
GENERATOR
CLK
CLK
Typical Application - Dimmable Buck LED Driver
3
DIMMER
AC
MAINS
EMI
FILTER
ISL1903
1 VDD
OUT 16
2 OFFREF PWMOUT 15
3 VREF
DHC 14
4 IOUT
GND 13
5 CS+
ISL1903
AC 12
6 OC
OVP 11
7 FB
RAMP 10
8 DELADJ
VERR 9
FN8285.1
September 20, 2012
Typical Application - DC Input Dimmable Buck LED Driver
4
9V TO 26V
ISL1903
OUT 16
1 VDD
2 OFFREF PWMOUT 15
3 VREF
DHC 14
4 IOUT
GND 13
5 CS+
ISL1903
AC 12
6 OC
OVP 11
7 FB
RAMP 10
8 DELADJ
VERR 9
PWM DIMMING INPUT
90Hz TO 140Hz 0 TO 4V
0 TO 100% DUTY CYCLE
FN8285.1
September 20, 2012
Typical Application - Isolated Dimmable Buck LED Driver
5
DIMMER
AC
MAINS
EMI
FILTER
ISL1903
1 VDD
OUT 16
2 OFFREF PWMOUT 15
3 VREF
DHC 14
4 IOUT
GND 13
5 CS+
ISL1903
AC 12
6 OC
OVP 11
7 FB
RAMP 10
8 DELADJ
VERR 9
FN8285.1
September 20, 2012
ISL1903
Pin Configuration
ISL1903
(16 LD QSOP)
TOP VIEW
1 VDD
OUT 16
2 OFFREF PWMOUT 15
3 VREF
DHC 14
4 IOUT
GND 13
5 CS+
AC 12
6 OC
OVP 11
7 FB
RAMP 10
8 DELADJ
VERR 9
Pin Descriptions
PIN #
SYMBOL
DESCRIPTION
1
VDD
VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to
the VDD and GND pins as possible.
2
OFFREF
Sets the reference level to disable the driver at light loading. The turn-off reference can be set at any level between 0 and 0.6V,
corresponding to 0 to 100% of output loading. This feature is normally used in triac-based wall dimmer applications to disable
the output before the dimmer becomes unstable due to insufficient holding current.
3
VREF
The 5.40V reference voltage output having ±100 mV tolerance over line, load and operating temperature. Bypass to GND with
a 0.1µF to 3.3µF low ESR capacitor.
4
IOUT
A voltage signal proportional to the peak switching current used to determine the inductor current.
5
CS+
The input for the CrCM current sense circuit. This input monitors the winding current or voltage to determine the critical
conduction operating point.
6
OC
The input to the load current sensing circuitry and the peak overcurrent comparator. The signal is sampled at the peak current
level for each switching cycle, amplified, and output on IOUT as a DC signal. It must be scaled before application to the FB pin
of the error amplifier (EA). The overcurrent comparator threshold is set at 600mV nominal. Peak OCP performs cycle-by-cycle
over current protection. OCP includes leading-edge-blanking (LEB), which blocks the signal at the beginning of the OUT pulse
for the duration of the blanking period and when the OUT pulse is low.
7
FB
FB is the inverting input to the error amplifier (EA). The feedback signal from IOUT, after being scaled and filtered, is applied
to the error amplifier.
8
DELADJ
Sets delay before a new switching cycles starts. This adjustment allows the user to delay the next switching cycle until the
switching FET drain-source voltage reaches a minimum value to allow quasi-ZVS (Zero Voltage Switching) operation. A resistor
to ground programs the delay. Pulling DELADJ to VREF disables the CrCM oscillator.
9
VERR
Output of the error amplifiers and the control voltage input to the inverting input of the PWM comparator. VERR cannot source
current and requires an external pull-up resistor to VREF.
10
RAMP
This is the input for the sawtooth waveform for the PWM comparator. Using an RC from VREF, a sawtooth waveform is created
for use by the PWM. It is compared to the error amplifier output, Verr, to create the PWM control signal. The RAMP pin is shorted
to GND at the termination of the PWM signal.
11
OVP
Input to detect an overvoltage (OV) condition on the output. Since the control variable is output current, a fault that results in
an open circuit will cause excessive output voltage. The circuit hysteresis is a switched current source that is active when the
OV threshold is exceeded.
12
AC
Input to sense AC voltage presence and amplitude. A resistor divider from the main FET drain and circuit ground or from an
auxiliary winding on the transformer/inductor is used to detect the AC voltage.
13
GND
Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance
layout is necessary. Ground planes and short traces are highly recommended.
14
DHC
An open drain FET used to load the input voltage to pre-load a triac-based dimmer so that adequate holding current is
maintained.
6
FN8285.1
September 20, 2012
ISL1903
Pin Descriptions (Continued)
PIN #
SYMBOL
DESCRIPTION
15
PWMOUT
The PWM gate drive output for LED dimming. The output level is clamped to ~12V for VDD greater than 12V. PWMOUT has
pull-down capability when UVLO is active or when the IC is not biased. This output is used to drive an external dimming FET.
The PWM operates at ~ 310Hz.
16
OUT
The gate drive output for the external power FET. OUT is capable of sourcing and sinking 1A @ VDD = 8V. The output level is
clamped to ~12V for VDD greater than 12V. OUT has pull-down capability when UVLO is active or when the IC is not biased.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL1903FAZ
1903 FAZ
ISL1903EVAL2Z
Evaluation Board
TEMP. RANGE
(°C)
-40 to +125
PACKAGE
(Pb-free)
16 Ld QSOP
PKG.
DWG. #
M16.15A
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL1903. For more information on MSL please see tech brief TB363.
Related Products
PART NUMBER
KEY DIFFERENTIATORS
ISL1901
Isolated and non-isolated single-stage flyback regulator
ISL1902
Isolated and non-isolated single-stage flyback regulator with inrush control and interface features for temperature and
ambient light sensors
ISL1903
Non-isolated single-stage buck regulator using switch current for regulation
ISL1904
Isolated single-stage flyback regulator with primary side current sense regulation
ISL1907
Non-isolated two-stage cascaded boost PFC + buck regulator eliminates dependency on electrolytic capacitors
ISL1908
Isolated two-stage cascaded boost PFC + flyback regulator eliminates dependency on electrolytic capacitors
7
FN8285.1
September 20, 2012
ISL1903
Absolute Maximum Ratings (Note 4)
Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +28.0V
OUT, PWMOUT, DHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 6.0V
Peak OUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0A
Peak PWMOUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . 2500V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 200V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93). . . . . . . . 1000V
Latch up (Per JESD-78B; Class 1, Level A) . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
16 Lead QSOP (Notes 5, 6) . . . . . . . . . . . . .
85
44
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . . . -65°C to 150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL1903Fxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 125°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . . . . 9 to 20 VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. All voltages are with respect to GND.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram ISL1903” on page 2 and “Typical Application schematics” beginning on page 3. VDD = 17V, RRAMP = 54k, CRAMP = 470pF, TA = -40°C to
+125°C, Typical values are at TA = +25°C; Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
-
-
26
V
SUPPLY VOLTAGE
Supply Voltage
Start-Up Current, IDD
VDD = 5.0V
-
100
200
µA
Operating Current, IDD
RLOAD, COUT = 0
-
6.0
7.8
mA
UVLO START Threshold
8.15
8.55
8.95
V
UVLO STOP Threshold
6.80
7.10
7.50
V
-
1.45
-
V
Hysteresis
REFERENCE VOLTAGE VREF
Overall Accuracy
IVREF = 0 -, -10mA, 8V < VDD< 26V
5.30
5.40
5.50
V
Long Term Stability
TA = +125°C, 1000 hours (Note 8)
-
10
25
mV
Operational Current (Source)
8V < VDD< 26V
-
-
-10
mA
Current Limit
VREF = 5.00V, 8V < VDD< 26V
-100
-
-15
mA
Load Capacitance
(Note 8)
0.1
-
3.3
µF
Current Limit Threshold
VERR = VREF, RAMP = 0V
570
595
616
mV
IOUT Amplifier Gain
VOC = 0.4V, 8V < VDD< 26V
3.90
4.00
4.13
V/V
IOUT High Level Output Voltage (VOH)
VIOUT @ 0µA - [email protected] -100µA,
8V < VDD< 26V
-
-
0.1
V
IOUT Low Level Output Voltage (VOL)
VIOUT @ 100µA, 8V < VDD< 26V
-
-
0.1
V
70
120
146
ns
PEAK CURRENT SENSE (OC)
Leading Edge Blanking (LEB) Duration
OC to OUT Delay + LEB
TA = +25°C
110
170
200
ns
Input Bias Current
VOC = 0.3V
-1.0
-
1.0
µA
8
FN8285.1
September 20, 2012
ISL1903
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram ISL1903” on page 2 and “Typical Application schematics” beginning on page 3. VDD = 17V, RRAMP = 54k, CRAMP = 470pF, TA = -40°C to
+125°C, Typical values are at TA = +25°C; Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
-
-
20
Ω
RAMP
RAMP Sink Current Device Impedance
IRAMP = 10 mA
RAMP to PWM Comparator Offset
TA = +25°C
181
235
287
mV
Input Bias Current
VRAMP = 0.3V
-1.0
-
1.0
µA
PWM Restart Delay Range
8V < VDD< 26V
0.2
-
2.0
µs
PWM Restart Cycle Delay
RDELADJ = 20.0k, 8V < VDD< 26V
240
280
320
ns
RDELADJ = 210k, 8V < VDD< 26V
2.00
2.20
2.40
s
Maximum Frequency Clamp
8V < VDD< 26V, RAMP = 2V,
RRAMP = 100
0.8
1.0
1.2
MHz
Minimum Frequency Clamp
8V < VDD< 26V, RRAMP = 23K
20
25
31
kHz
Minimum On Time
8V < VDD< 26V, FB = 1V, AC = 2V,
RAMP = 0V
173
-
246
ns
VERR to PWM Gain
8V < VDD< 26V
-
0.200
-
V/V
SS to PWM Gain
8V < VDD< 26V
-
0.222
-
V/V
Input Common Mode (CM) Range
(Note 8)
0
-
3.4
V
GBWP
(Note 8)
1.9
-
-
MHz
VERR VOL
IVERR = 6mA, 8V < VDD< 26V
-
-
0.950
V
VERR VOH
IVERR = 1mA (Ext. pull-up),
SS complete
3.90
4.00
4.20
V
Open Loop Gain
(Note 8)
70
-
-
dB
Offset Voltage (VOS)
8V < VDD< 26V
-7.5
-
7.5
mV
Input Bias Current
8V < VDD< 26V
-1.0
-
1.0
µA
Zero Current Detection (CrCM) Threshold, Falling
8V < VDD< 26V
6
18
30
mV
Input Bias Current
8V < VDD< 26V
-1.0
-
1.0
µA
Input Bias Current
8V < VDD< 26V
-50
-
50
nA
Detection Threshold, Falling
8V < VDD< 26V, ACPEAK = 100mV
19
32
51
mV
Detection Threshold Hysteresis
8V < VDD< 26V
-
23
-
mV
Input Operating Range
8V < VDD< 26V
0
-
4.00
V
Clamp Voltage
IACDETECT = 1.0mA
6.8
-
7.6
V
EA Reference Input Range
8V < VDD< 26V
0
-
0.538
V
PULSE WIDTH MODULATOR
ERROR AMPLIFIER
CURRENT SENSE (CS+)
AC DETECTOR
9
FN8285.1
September 20, 2012
ISL1903
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram ISL1903” on page 2 and “Typical Application schematics” beginning on page 3. VDD = 17V, RRAMP = 54k, CRAMP = 470pF, TA = -40°C to
+125°C, Typical values are at TA = +25°C; Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
Duty Cycle () = 98%
523
548
574
mV
Duty Cycle () = 75%
286
318
340
mV
Duty Cycle () = 50%
117
139
156
mV
Duty Cycle () = 25%
16
33
44
mV
Duty Cycle () = 10%
0
3
11
mV
VDHC = 10mA,
VDD = 8V operating
-
-
600
mV
-
4.0
-
µs
289
389
483
ms
11
27
43
mV
-1.0
-
1.0
µA
Operating Range (Excluding Offset)
0
-
0.5
V
Threshold Hysteresis
33
52
70
mV
Threshold Offset
78
104
129
mV
-
32
PARAMETER
EA Reference vs AC Conduction Angle
TEST CONDITIONS
ILPOUT = 0µA, f = 120Hz (rectified),
8V < VDD< 26V
DHC
Low Level Output Voltage (VOL)
Turn-off Delay after AC Returns
SOFT-START
Duration
Reference Soft Start Initial Step
OFFREF
Input Bias Current
AC Dropout Disable Delay
ms
OUT
High Level Output Voltage (VOH)
VOUT @ 0mA - VOUT @ -100mA,
VDD = 8V operating
-
0.35
1.2
V
Low Level Output Voltage (VOL)
VOUT @ 100mA, VDD = 8V operating
-
0.7
1.2
V
Rise Time
CLOAD = 2.2nF, VDD = 8V,
t90% - t10%
-
35
55
ns
Fall Time
CLOAD = 2.2nF, VDD = 8V,
t10% - t90%
-
25
40
ns
Output Clamp Voltage
VDD = 20V, ILOAD = -10µA
10.5
12.0
13.4
V
Unbiased Output Voltage Clamp
VDD = 6V, ILOAD = 5mA
-
-
1.9
V
High Level Output Voltage (VOH)
VOUT @ 0mA - VOUT @ -10mA,
VDD = 8V operating
-
0.8
1.2
V
Low Level Output Voltage (VOL)
VOUT @ 10mA,
VDD = 8V operating
-
0.8
1.2
V
Rise Time
CLOAD = 1nF, VDD = 8V operating,
t90% - t10%
-
160
240
ns
Fall Time
CLOAD = 1nF, VDD = 8V operating,
t10% - t90%
-
160
240
ns
Output Voltage Clamp
VDD = 20V, ILOAD = -10µA
10.5
12.0
13.4
V
PWMOUT
10
FN8285.1
September 20, 2012
ISL1903
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram ISL1903” on page 2 and “Typical Application schematics” beginning on page 3. VDD = 17V, RRAMP = 54k, CRAMP = 470pF, TA = -40°C to
+125°C, Typical values are at TA = +25°C; Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
TEST CONDITIONS
Unbiased Output Voltage Clamp
VDD = 6V, ILOAD = 3mA
Frequency
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
-
-
1.9
V
291
320
349
Hz
Maximum Duty Cycle
REFIN = 0.5V
-
-
100
%
Minimum On-Time
REFIN = 0V
-
-
0.5
s
OVP Threshold
1.46
1.50
1.54
V
OVP Hysteresis
10
20
27
A
Input Bias Current
-1.0
-
1.0
A
IOVP = 1mA
5.4
-
7.0
V
Thermal Shutdown
(Note 8)
150
160
170
°C
Hysteresis
(Note 8)
-
25
-
°C
OVP
OVP Clamp Voltage
THERMAL PROTECTION
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Limits established by characterization and are not production tested.
Test Waveforms and Circuits
8V
OUT 16
1 VDD
2 OFFREF PWMOUT 15
3 VREF
DHC 14
4 IOUT
GND 13
ISL1903
5 CS+
AC 12
6 OC
OVP 11
7 FB
RAMP 10
8 DELADJ
VERR 9
5k
0 TO 1V 120Hz
90%
1nF
2.2nF
OUT
OR
PWMOUT
10%
tR
tF
470pF
54k
FIGURE 2. RISE/FALL TIME TEST CIRCUIT
11
FIGURE 3. RISE/FALL TIMES
FN8285.1
September 20, 2012
ISL1903
Test Waveforms and Circuits (Continued)
OC THRESHOLD
tDELAY
OC
AC
MAINS
LEADING EDGE BLANKING
tDELAY
OC PROPAGATION DELAY
OC + LEB TO OUT DELAY
DHC
OUT
FIGURE 4. OC +LEB TO OUT DELAY
FIGURE 5. AC MAINS TO DHC TIMING
1.001
500
1.000
400
EA REFERENCE (mV)
NORMALIZED VREF
Typical Performance Curves
0.999
0.998
0.997
0.996
-40 -25
-10
5
20
35
50
65
80
95
300
200
100
0
110 125
0
FIGURE 6. REFERENCE VOLTAGE vs TEMPERATURE
30
40
50
60
70
80
90
100
100
PWMOUT DUTY CYCLE (%)
DELAY TIME (µs)
20
FIGURE 7. EA REFERENCE vs AC SIGNAL DUTY CYCLE
2.5
2.0
1.5
1.0
0.5
0
10
AC CONDUCTION ANGLE (% DUTY CYCLE 120Hz)
TEMPERATURE (°C)
0
25
50
75
100
125
150
175
DELAY RESISTANCE (kΩ)
FIGURE 8. DELAY vs DELADJ RESISTANCE
12
200
225
80
60
40
20
0
0
10
20
30
40
50
60
70
80
90
100
AC CONDUCTION ANGLE (% DUTY CYCLE 120Hz)
FIGURE 9. PWMOUT DUTY CYCLE vs AC SIGNAL DUTY CYCLE
FN8285.1
September 20, 2012
ISL1903
Functional Description
Features
The ISL1903 LED driver is an excellent choice for low cost AC
mains powered single conversion LED lighting applications. It
provides active power factor correction (PFC) to achieve high
power factor using critical conduction mode operation, and
incorporates additional features for compatibility with
triac-based dimmers. Furthermore, it senses FET switching
currents to regulate the output current which eliminates the need
to level shift current feedback signal, or for isolated designs, to
cross the isolation boundary to close the feedback control loop.
The ISL1903 includes support for both PWM and DC current
dimming of the output.
Oscillator
The ISL1903 uses a critical conduction mode (CrCM) algorithm to
control the switching behavior of the converter. The ON-time of
the primary power switch is held virtually constant by the low
bandwidth control loop (in PFC applications). The OFF-time
duration is determined by the time it takes the current or voltage
to decay during the flyback period. When the mmf (magneto
motive force) of the transformer decays to zero, the winding
currents are zero and the winding voltages collapse. Either may
be monitored and used to initiate the next switching cycle. The
ISL1903 monitors the CrCM condition using the CS+ signal. It
may be used to monitor either current or voltage.
Additionally, there is a user adjustable delay duration, DELADJ, to
delay the initiation of the next switching cycle to allow the
drain-source voltage of the primary switch to ring to a minimal.
This allows quasi-ZVS operation to reduce capacitive switching
losses and improve efficiency. See “Quasi-Resonant Switching”
on page 17.
By its nature the converter operation is variable frequency. There
are both minimum and maximum frequency clamps that limit
the range of operation. The minimum frequency clamp prevents
the converter from operating in the audible frequency range. The
maximum frequency clamps prevents operating at very high
frequencies that may result in excessive losses.
An individual switching period is the sum of the ON-time, the
OFF-time, and the restart delay duration. The ON-time is
determined by the control loop error voltage, VERR, and the
RAMP signal. As its name implies, the RAMP signal is a linearly
increasing signal that starts at zero volts and ramps to a
maximum of ~VERR/5 - 235mV. RAMP requires an external
resistor and capacitor connected to VREF to form an RC charging
network. If VERR is at its maximum level of VREF, the time
required to charge RAMP to ~850mV determines the maximum
ON-time of the converter. RAMP is discharged every switching
cycle when the ON-time terminates.
The design methodology is similar to designing a discontinuous
mode (DCM) buck converter with the constraint that it must
operate at the DCM/CCM boundary at maximum load and
minimum input voltage. The difference is that the converter will
always operate at the DCM/CCM boundary, whereas a DCM
converter will be more discontinuous as the input voltage
increases or the load decreases. In PFC applications, the design
is further complicated by the input voltage waveform, a rectified
sinewave.
Once the output power, Po, the output current, Io, the output
voltage, Vo, and the minimum input AC voltage are known, the
inductor design can be started. From the minimum AC input
voltage, the minimum DC equivalent (RMS) input voltage must
be determined. In PFC applications, the converter behaves as if
the input voltage is an equivalent DC value due to the low control
loop bandwidth.
A typical minimum operating frequency must be selected. This is
a somewhat arbitrary determination, but does ultimately
determine the inductor size. The typical frequency is what occurs
when the instantaneous rectified input AC voltage is exactly at
the equivalent DC value. The frequency will be higher when the
instantaneous input voltage is lower, and lower when the
instantaneous input voltage is higher. However, the duty cycle at
the equivalent DC input voltage determines the ON-time for the
entire AC half-cycle. The ON-time is constant due to the low
bandwidth control loop, but the OFF-time and duty cycle vary with
the instantaneous input voltage since the peak switch current
follows V = Ldi/dt.
The typical frequency may require adjustment once the initial
calculations are complete to see if the operating frequency at the
peak of the minimum AC input voltage is acceptable. The peak
current will be 1.41 times higher at the AC peak than at the DC
equivalent (RMS) input voltage. So, while the ON-time is nearly
constant due to the low bandwidth control loop, the OFF-time will
be 1.41 times longer.
The effective AC conduction angle must also be considered when
calculating the inductance. Since no current flows to the load
when the instantaneous input voltage is less than the output
voltage, the equivalent DC input voltage (rms) is duty cycle
modulated by the effective AC conduction angle. This results in
higher currents during the portion of the AC half-cycle when the
converter can deliver power to the load. The switching currents
increase and the frequency of operation decreases. Obviously the
higher the output voltage the greater the impact.
The OFF-time duration is determined by the design of the
magnetic element(s), which depends on the required energy
storage/transfer and the inductance of the winding(s). The
transformer/inductor design also determines the maximum
ON-time that can be supported without saturation, so, in reality,
the magnetics design is critical to every aspect of determining
the switching frequency range.
13
FN8285.1
September 20, 2012
ISL1903
TABLE 1. OSCILLATOR DEFINITIONS
VmINrms =
Minimum RMS input voltage
VmaxINrms =
Maximum RMS input voltage
fmin(avg) =
Typical frequency when VIN (instantaneous) =
minimum VIN(rms)
Dmax =
Maximum typical duty cycle desired
Dmin =
Minimum typical duty cycle
tON(MAX) =
ftyp(avg) x Dmax
tON
ON-time of the power FET controlled by OUT
tOFF
OFF-time duration required for CrCM operation
L=
Inductance
Nsp =
Transformer turns ratio, Ns/Np
Ip(peak) =
Peak switch current within a switching cycle
tdelay =
User adjustable delay before the next switching
cycle begins
H
(EQ. 1)
where Lest is the inductance required to achieve the selected
operating frequency at the peak of the AC voltage waveform.
Note that Equation 1 calculates the required inductance when
operating at the DC equivalent input voltage. It does not take into
account the reduction in conduction angle that occurs when the
instantaneous input voltage is less than the output voltage.
Equation 2 corrects for this.
VO

 – 2  sin  ------------------------------------
 2  V IN  rms 
L = L est  -------------------------------------------------------------------------
–1 
(EQ. 2)
H
The maximum ON-time can be found using Equation 3.
2  IO  L
t ON = -------------------------------------V IN  rms  – V O
(EQ. 3)
s
The peak current at the end of the ON-time is shown in
Equation 4:
 2  V IN  rms  – V O   t ON
I p  peak  = --------------------------------------------------------------------L
A
(EQ. 4)
(EQ. 5)
s
The lowest switching frequency is the reciprocal of the sum of the
ON-time, the OFF-time, and the delay time shown by Equation 6.
1
f min = ---------------------------------------------------t ON + t OFF + t delay
Hz
14
s
(EQ. 7)
The highest frequency is determined by the shortest ON-time
summed with tdelay. The shortest ON-time occurs at high line and
minimum load, and occurs at or near the AC zero crossing when
the primary (and secondary) current is zero. The minimum
ON-time the ISL1903 can produce is ~200ns, suggesting an
operating frequency above 1MHz. Regardless, the maximum
frequency clamp limits the frequency to about 1MHz.
Once the inductance is determined, the general formulae to
calculate the ON-time and OFF-time at an equivalent DC input
voltage and load are:
L  2  IO
t OFF = --------------------VO
s
(EQ. 8)
L  2  IO
t ON = -----------------------V IN  rms 
s
(EQ. 9)
It is clear from the equations that there is a linear relationship
between load current and frequency. At some light load the
frequency will be limited by the maximum frequency clamp.
There is an inverse relationship between the input voltage and
frequency and its effect is restricted by the input voltage range of
the application.
It should be noted, however, that Equations 8 and 9 assume full
conduction angle of the AC mains. There are two issues
regarding actual conduction angle. First, there is no power
delivered to the load until the AC mains instantaneous voltage
exceeds the output voltage. Like any buck converter, the input
voltage must be higher than the output voltage. Secondly, when
conduction angle modulating dimmers are used to block a
portion of each AC half-cycle, the switching currents remain
essentially unchanged during the conduction portion of the AC
half-cycle as the conduction angle is reduced. The conduction
angle is reduced, not the amplitude of the waveform envelope.
The result being the steady state frequency behavior will not vary
much as the conduction angle is reduced depending on the
linearity of the conduction angle and the control loop reference
gain. See Figure 7 on page 12.
Soft-Start Operation
And the OFF-time is shown in Equation 5:
L  I p  peak 
t OFF = ----------------------------Vo
  L p   C oss + C other 
t delay  ----------------------------------------------------------------2
If the lowest frequency does not meet the requirements, then
iterative calculations may be required.
The first calculation required is to determine the required
inductance. The desired inductance can be calculated using
Equation 1.
V O   V IN  rms  – V O 
L est = -----------------------------------------------------------------------------------2  f min  avg   I O  2  V IN  rms 
The delay time can be approximated if the equivalent
drain-source capacitance (Coss) of the primary switch is known.
This value should also include any parasitic capacitance on the
drain node. These parameters may not be known during the early
stages of the design, but are typically on the order of 300ns to
500ns.
Soft-start is not user adjustable and is fixed at ~ 400ms. Both the
duty cycle and control loop reference are affected by soft-start.
Soft-starting both the duty cycle and the reference ensures a well
behaved closed loop soft-start that results in virtually no
overshoot.
(EQ. 6)
FN8285.1
September 20, 2012
ISL1903
AC Detection and Reference Generation
The ISL1903 creates a 0 to 0.5V reference for the LED current
control loop by measuring the conduction angle of the AC input
voltage. The reference changes only with conduction angle and is
virtually unaffected by variation in either voltage amplitude or
frequency.
The ISL1903 cannot detect the conduction angle by monitoring
the input voltage directly. The AC voltage does not track the
source voltage on the load side of the dimmer once the input
voltage drops below the output voltage. In the buck topology the
converter stops drawing current from the AC line once the
instantaneous input voltage drops below the output voltage. This
results in commutation of the dimmer triac which leaves a
residual voltage on the input capacitance and impedes/prevents
the detection of the conduction angle. Instead, the conduction
angle is detected indirectly, either by monitoring the drain-source
voltage of the switching FET or by using an auxiliary winding on
the inductor. When the dimmer is blocking, the switching FET,
although switching, has no drain-source voltage and transfers no
power. If an auxiliary winding is present, it is not energized.
reset the soft-start circuit approximately 35ms after the last AC
zero crossing is detected. If AC is held above its detection
threshold for the same duration, the internal reference is forced
to its maximum of ~0.5V.
AC may be directly coupled to a 90Hz to 130Hz PWM signal to
generate a reference if dimming is desired without using an AC
dimmer.
Primary Current Sensing
The ISL1903 is configured to regulate the output current by
monitoring the primary switch current at the OC pin. The peak
primary switch current is captured, processed, and output on
IOUT as a DC signal that is amplitude modulated in proportion to
the output current. The IOUT amplitude is equivalent to 4x the
peak switch current during the previous ON-time. It must be
scaled before being input to the control loop at the FB pin.
The OC pin also provides cycle-by-cycle overcurrent protection.
The ON-time is terminated if OC exceeds 0.6V nominal. There is
~120ns of leading edge blanking (LEB) on OC to minimize or
eliminate external filtering.
Dimming
AC
The ISL1903 supports both PWM and DC current modulation
dimming. In either case, the control loop determines the average
current delivered to the load. PWM dimming is not
recommended for non-isolated applications requiring PFC. The
PWM dimming method will cause high harmonic content due to
the low PWM dimming frequency.
EMI
FILTER
The usual method of dimming an LED string is to modulate the
DC current through the string. DC current dimming is the lower
cost method, but results in a non-linear dimming characteristic
due to the increasing efficacy of the LEDs as current is reduced.
PWM dimming results in linear dimming behavior.
R1
ISL1903
1
16
2
15
3
14
13
4
AC
5
12
6
11
7
10
8
9
R2
C1
FIGURE 10. AC DETECTION
Referring to Figure 10, capacitor C1 is added to filter the scaled
switching waveform of the FET drain-source voltage, and delays
the detection of the loss of AC voltage. This has the effect of
masking the conduction angle reduction caused by the buck
topology as well as that due to variation in maximum dimmer
conduction angles between manufacturers.
The AC pin has an input range of 0 to 4V. The peak of the input
signal should range between 1 and 4 volts for best accuracy. The
AC detection circuit measures both the duration of the AC
conduction angle and the half-cycle duration. By comparing the
two every half-cycle, the detection circuit creates a frequency
independent reference that is updated each AC half-cycle.
In the event of an AC outage, the AC mains frequency reference
is lost. The ISL1903 will force the reference to zero volts and
15
For PWM dimming, an external FET, controlled by PWMOUT, is
required to gate the drive signal to the switching FET. See “Typical
Application - DC Input Dimmable Buck LED Driver” on page 4 for
an example. When PWMOUT is high, the main switching FET
operates normally. When PWMOUT is low, the main switching
FET gate signal is blocked and the converter is effectively off.
Regardless of the dimming method used, the control loop
determines the average current delivered to the load. It does not
matter if the load current is DC or pulsed, the converter control
loop and output capacitance operate to filter and average the
converter output current independently of the actual load current
waveform.
The dimming PWM and control loop are linked together such that
the PWM duty cycle tracks the main control loop reference
setpoint. If the control loop is set for 50% load, for example, the
dimming PWM duty cycle is set for 50%. The LED current will be
at 100% load for 50% of the time and 0% load for 50% of the
time, which averages to the 50% average load setpoint. See
Figures 7 and 9 for a graphical representation of the relationship
between the control loop reference and PWMOUT duty cycle. If
PWM dimming is used, the control loop bandwidth must be
reduced significantly below the PWM dimming frequency. It
should be noted that the PWMOUT duty cycle is not allowed to go
to zero.
FN8285.1
September 20, 2012
ISL1903
Control Loop
The control loop configuration is user adjustable with the
selection of the external compensation components. For
applications requiring power factor correction (PFC), a very low
bandwidth integrator is used, typically 20Hz or less. In other
applications, the control loop bandwidth can be increased as
required like any other externally compensated voltage mode
PWM controller.
For higher BW applications, a Type II configuration may be
required. Figures 11 and 12 show the Type I and Type II
configurations, respectively.
ISL1903
AC
IOUT
REFERENCE
GENERATOR
R1
VREF
LOAD
RPU
RFB1
+
VERR
ISL1903
FB
_
OUT
OC - IOUT
PROCESSOR
OC
R2
CFB1
REFERENCE
GENERATOR
AC
RFB2
FIGURE 12. TYPE II EA CONFIGURATION
RPU
RFB
+
VERR
CFB2
R1
VREF
RS
CFILTER
IOUT
_
FB
OVP
R2
CFB
CFILTER
VREF
MONITORED
VOLTAGE
20µA
R1
FIGURE 11. CONTROL LOOP CONFIGURATION
1
R3
0
+
Referring to Figure 11, the FET switching current flowing through
Rs, is applied to the OC pin of the ISL1903. The peak signal is
sampled, buffered, and output on IOUT with a gain of four. The
voltage on IOUT represents 8x the average load current on a
cycle-by-cycle basis. In PFC applications, IOUT tracks the rectified
AC voltage waveform and must be averaged. For DC input
applications, this is obviously not required.
8  Rs
IOUT = ---------------  I o
N sp
_
R2
FIGURE 13. OV HYSTERESIS
(EQ. 10)
V
where IOUT is the average or DC value of IOUT. Prior to applying
IOUT to the EA at the FB pin it must be scaled such that at
maximum output current the signal is equal to the maximum EA
reference level (nominally 0.530V), while also limiting the
maximum peak primary OC signal to less than the overcurrent
threshold of 0.6V.
V OC
R s = -------------------  I oCL
1.5V
C OPT

The ISL1903 has independent overvoltage protection accessed
through the OV pin. There is a nominal 20µA switched current
source used to create hysteresis. The current source is active only
during an OV fault; otherwise, it is inactive and does not affect
the node voltage. The magnitude of the hysteresis voltage is a
function of the external resistor divider impedance.
 R1 + R2 
V ov  ri sin g  = 1.5  --------------------------R2
(EQ. 12)
V
(EQ. 11)
where IoCL is the output current limit threshold, VOC is the
current limit threshold, and Rs is the current sensing resistor.
Once the value of Rs is determined, Equation 11 can be used to
solve for the maximum level of OC at any steady state current
when Io is substituted for IoCL and solving for Voc.
The EA compensation depends on the bandwidth required for the
application. For PFC applications the BW is necessarily limited to
20Hz or less. For other applications, the BW may be increased as
required up to about 1/5 of the lowest switching frequency
allowed as described in “Oscillator” on page 13. For the low BW
applications a Type I compensation configuration is adequate.
16
If the divider formed by R1 and R2 is sufficiently high
impedance, R3 is not required, and the hysteresis is:
V = 20  10
–6
 R1
(EQ. 13)
V
If that does not result in the desired hysteresis then R3 is
needed, and the hysteresis is:
V = 20  10
–6 
 R1 + R2 
 R1 + R3  ---------------------------

R2

V
(EQ. 14)
If the OV signal requires filtering, the filter capacitor, Copt, should
be placed as shown in Figure 10. The current hysteresis provides
FN8285.1
September 20, 2012
ISL1903
great flexibility in setting the magnitude of the hysteresis voltage,
but it is susceptible to noise due to its high impedance. If the
hysteresis was implemented as a fixed voltage instead, the
signal could be filtered with a small capacitor placed between
the OV pin and signal ground. This technique does not work well
when the hysteresis is a current source because a current source
takes time to charge the filter capacitor. There is no
instantaneous change in the threshold level rendering the
current hysteresis ineffective. To remedy the situation, the filter
capacitor must be separated from the OV pin by R3. The
capacitor and R3 must be physically close to the OV pin.
OFFREF Control
The ISL1903 provides the ability to disable the output based on
the level of the control loop reference, set by the AC conduction
angle on the AC pin. Setting OFFREF to a voltage between 0 and
0.6V determines the threshold voltage that disables the output.
REFIN  off  = OFFREF – 0.100
V
(EQ. 15)
is linear for resistance values greater than ~ 20 kand can be
estimated using Equation 17.
t delay  73.33 + 10.2  R DELADJ  k 
ns
(EQ. 17)
DHC (Dimmer Holding Current)
The DHC pin provides a method to pre-load a triac-based dimmer
during the period of time when the AC is blocked, with overlap at
each edge of the AC conduction period to ensure adequate
holding current. DHC is an open drain FET used to control an
external resistor to act as the load.
DHC controls a resistor on the external high voltage start-up bias
regulator. See “Typical Application - Dimmable Buck LED Driver”
on page 3 for an example of its usage. Note the series resistor
and diode connecting VDD to the gate of the start-up bias FET. It
is required to keep the device on when the AC voltage is near the
zero-crossing.
OFFREF allows the designer to disable the output at a
pre-determined load current to prevent undesirable behavior
such as at light loading conditions when there may be
insufficient current to maintain the holding current in a
triac-based dimmer. Setting OFFREF to less than 100mV disables
this feature. OFFREF has a nominal hysteresis of 50mV.
Gate Drive
REFIN  on  = OFFREF – 0.050
Internal die over-temperature protection is provided. An
integrated temperature sensor protects the device should the
junction temperature exceed +160°C. There is approximately
+10°C of hysteresis.
V
(EQ. 16)
Quasi-Resonant Switching
The ISL1903 uses a critical conduction mode PWM control
algorithm. Near zero voltage switching (ZVS) or quasi-resonant
valley switching, as it is sometimes referred to, can be achieved
in the flyback topology by delaying the next switching cycle after
the transformer current decays to zero (critical conduction
mode). The delay allows the primary inductance and capacitance
to oscillate, causing the switching FET drain-source voltage to
ring down to a minimal. If the FET is turned on at this minimal,
the capacitive switching loss (1/2 CV2) is greatly reduced.
The ISL1903 output (OUT) is capable of sourcing and sinking up
to 1A. The OUT high level is limited to the OUT clamp voltage or
VDD, whichever is lower.
Thermal Protection
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device.
A good ground plane must be employed. VDD and VREF should
be bypassed directly to GND with good high frequency
capacitance.
Winding Current
FET D-S Voltage
FIGURE 14. QUASI-RESONANT NEAR-ZVS SWITCHING
The delay duration is set with a resistor from DELADJ to ground.
Figure 7 presents the graphical relationship between the delay
duration and the value of the DELADJ resistance. The relationship
17
FN8285.1
September 20, 2012
ISL1903
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
August 27, 2012
FN8285.1
Page 14: Equation 2 changed from S to H
Equation 4 changed from H to A, and Equation 5 changed from H to S.
Page 16: Equation 11, changed from V to ohms
August 10, 2012
FN8285.0
Initial release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL1903
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN8285.1
September 20, 2012
ISL1903
Package Outline Drawing
M16.15A
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (QSOP/SSOP)
0.150” WIDE BODY
Rev 3, 8/12
16
INDEX
AREA
3.99
3.81
6.20
5.84
4
0.25(0.010) M
B M
-B-
1
TOP VIEW
DETAIL “X”
SEATING PLANE
-A-
4.98
4.80
GAUGE
PLANE
1.73
1.55
3
-C0.25
0.010
0.249
0.102
0.635 BSC
7
0.89
0.41
0.31
0.20
0.41
x 45° 5
0.25
0.10(0.004)
0.17(0.007) M C A M B S
SIDE VIEW 1
8°
0°
1.55
1.40
7.11
0.249
0.191
SIDE VIEW 2
5.59
4.06
0.38
0.635
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number
95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Package length does not include mold flash, protrusions or gate burrs. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Package width does not include interlead flash or protrusions. Interlead flash and
protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be
located within the crosshatched area.
6. Terminal numbers are shown for reference only.
7. Lead width does not include dambar protrusion. Allowable dambar protrusion shall be
0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.
8. Controlling dimension: MILLIMETER.
TYPICAL RECOMMENDED LAND PATTERN
19
FN8285.1
September 20, 2012