NSC LM2633MTD

LM2633
Advanced Two-Phase Synchronous Triple Regulator
Controller for Notebook CPUs
General Description
Features
The LM2633 is a feature-rich IC that combines three regulator controllers - two current mode synchronous buck regulator controllers and a linear regulator controller.
The two switching regulator controllers operate 180˚ out of
phase. This feature reduces the input ripple RMS current,
resulting in a smaller input filter.
The first switching controller (Channel 1) features an Intel
mobile CPU compatible precision 5-bit digital-to-analog converter which programs the output voltage from 0.925V to
2.00V. It is also compatible with the dynamic VID requirements. The second switching controller (Channel 2) is adjustable between 1.25V to 6.0V.
Use of synchronous rectification and pulse-skip operation at
light load achieves high efficiency over a wide load range.
Fixed-frequency operation can be obtained by disabling the
pulse-skip mode.
Current-mode feedback control assures excellent line and
load regulation and a wide loop bandwidth for good response to fast load transient events. Current mode control is
achieved through sensing the Vds of the top FET and thus
an external sense resistor is not necessary.
A power good signal is available to indicate the general
health of the output voltages.
A unique feature is the analog soft-start for the switching
controllers is independent of the slew rate of the input voltage. This will make the soft start behavior more predictable
and controllable. An internal 5V rail is available externally for
boot-strap circuitry (only) when no 5V is available from other
sources.
Current limit for either of the two switching channels is
achieved through sensing the top FET VDS and the value is
adjustable. The two switching controllers have under-voltage
and over-voltage latch protections, and the linear regulator
has under-voltage latch protection. Under-voltage latch can
be disabled or delayed by a programmable amount of time.
The input voltage for the switching channels ranges from 5V
to 30V, which makes possible the choice of different battery
chemistries and options.
GENERAL
n Three regulated output voltages
n 4.5V to 30V input range
n Power good function
n Input under-voltage lockout
n Thermal shutdown
n Tiny TSSOP package
SWITCHING SECTION
n Two channels operating 180˚ out of phase
n Separate on/off control for each channel
n Current mode control without sense resistor
n Skip-mode operation available
n Adjustable cycle-by-cycle current limit
n Negative current limit
n Analog soft start independent of input voltage slew rate
n Power ground pins separate
n Output UVP and OVP
n Programmable output UVP delay
n 250kHz switching frequency (for Vin < 17V)
n Channel 1 output from 0.925V to 2.00V
n ± 1.5% DAC accuracy from 0˚C to 125˚C
n ± 1.7% initial tolerance for Channel 2
n Dynamic VID change ready
n Power good flags VID changes
n Channel 2 output from 1.3V to 6.0V
LINEAR SECTION
n Output voltage adjustable
n 50mA maximum driving current
n Output UVP
n ± 2% initial tolerance
Applications
n Power supply for CPUs of notebook PCs that require
the SpeedStep™ technique
n Power supply for information appliances
n General low voltage DC/DC buck regulators
SpeedStep™ is a trademark of Intel Corporation.
© 2001 National Semiconductor Corporation
DS200008
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LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs
August 2001
LM2633
PGOOD (Pin 13): : A constant monitor on the output voltages. It indicates the general health of the regulators. For
more information, see Power Good Truth Table (Table 2) and
Power Good Function in Operation Descriptions.
Connection Diagram
TOP VIEW
GND (Pin 16-17): Low-noise analog ground.
G3 (Pin 18): Connect to the base or gate of the linear
regulator pass transistor.
OUT3 (Pin 19): Connect to the output of the linear regulator.
FB3 (Pin 21): The feedback input for the linear regulator,
connected to the center of the external resistor divider.
COMP2 (Pin 22): Channel 2 compensation network connection (it’s the output of the voltage error amplifier).
FB2 (Pin 23): The feedback input for Channel 2. Connect to
the center of the output resistor divider.
SENSE2 (Pin 24): Remote sense pin of Channel 2. This pin
is used for skip-mode operation.
ILIM2 (Pin 25): Current limit threshold setting for Channel 2.
It sinks at a constant 10 µA current. A resistor is connected
between this pin and the top MOSFET drain. The voltage
across this resistor is compared with the VDS of the top
MOSFET to determine if an over-current condition has occurred in Channel 2.
KS2 (Pin 27): The Kelvin sense for the drain of the top
MOSFET of Channel 2.
SW2 (Pin 29): Switch-node connection for Channel 2, which
is connected to the source of the top MOSFET.
HDRV2 (Pin 30): Top gate-drive output for Channel 2.
HDRV2 is a floating drive output that rides on SW2 voltage.
CBOOT2 (Pin 31): Bootstrap capacitor connection for Channel 2 top gate drive. It is the positive supply rail for Channel
2 top gate drive.
VDD2 (Pin 32): The supply rail for Channel 2 bottom gate
drive.
LDRV2 (Pin 33): Bottom gate-drive output for Channel 2.
PGND2 (Pin 34): Power ground for Channel 2.
VIN (Pin 35): The regulator input voltage supply.
VLIN5 (Pin 36): The output of the internal 5V linear regulator. Bypass to the ground with a 1UF ceramic capacitor.
When regulator input voltage is 5V, this pin can be tied to
VIN pin to improve light-load efficiency.
PGND1 (Pin 38-39): Power ground for Channel 1.
LDRV1 (Pin 40-41): Bottom gate-drive output for Channel 1.
VDD1 (Pin 42): The supply rail for the Channel 1 bottom
gate drive.
CBOOT1 (Pin 43): Bootstrap capacitor connection for Channel 1 top gate drive. It is the positive supply rail for Channel
1 top gate drive.
HDRV1 (Pin 44): Top gate-drive output for Channel 1.
HDRV1 is a floating drive output that rides on SW1 voltage.
SW1 (Pin 45): Switch-node connection for Channel 1, which
is connected to the source of the top MOSFET.
KS1 (Pin 46): The Kelvin sense for the drain of the top
MOSFET of Channel 1.
ILIM1 (Pin 48): Current limit threshold setting for Channel 1.
It sinks at a constant 10 µA current. A resistor is connected
between this pin and the top MOSFET drain. The voltage
across this resistor is compared with the VDS of the top
MOSFET to determine if an over-current condition has occurred in Channel 1.
20000801
48-Lead TSSOP (MTD)
Order Number LM2633MTD
See NS Package Number MTD48
Pin Descriptions
FB1 (Pin 1):The feedback input for Channel 1. Connect to
the load directly.
COMP1 (Pin 2): Channel 1 compensation network connection (connected to the output of the voltage error amplifier).
NC (Pins 3, 14, 15, 20, 26, 28, 37 and 47): No internal
connection.
ON/SS1 (Pin 4): Adding a capacitor to this pin provides a
soft-start function which minimizes inrush current and output
voltage overshoot; A lower than 0.8V input (open-collector
type) at this pin turns off Channel 1; also if both ON/SS1 and
ON/SS2 pins are below 0.8V, the whole IC goes into shut
down mode. The soft-start capacitor voltage will eventually
be charged to VIN or 6V, whichever is lower.
ON/SS2 (Pin 5): Adding a capacitor to this pin provides a
soft-start function which minimizes inrush current and output
voltage overshoot; A lower than 0.8V input (open-collector
type) at this pin turns off Channel 2; also if both ON/SS1 and
ON/SS2 pins are below 0.8V, the whole IC goes into shut
down mode. The soft-start capacitor voltage will eventually
be charged to VIN or 6V, whichever is lower.
VID4-0 (Pins 6-10): Voltage identification code. Each pin
has an internal pull-up. They can accept open collector
compatible 5-bit binary code from the CPU. The code table is
shown in Table 3.
UV_ DELAY (Pin 11): A capacitor from this pin to ground
adjusts the delay for the output under-voltage lockout.
FPWM (Pin 12): When FPWM is low, pulse-skip mode operation at light load is disabled. The regulator is forced to
operate in constant frequency mode.
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2
Block Diagrams
20000802
LM2633
3
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4
Block Diagrams
(Continued)
20000886
LM2633
Block Diagrams
(Continued)
20000803
LM2633
5
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LM2633
TABLE 1. Shut Down Latch Truth Table
Input
ovp1
ovp2
uvp1
uvp2
uvplr
new
vid
1
Output
ch1 on
0
1
1
0
ch2 on
fault
ssto2
uv_delay
latch off
Σ=1
0
1
Σ=1
0
1
1
0
1
1
1
cap
0
Σ=1
1
ssto1
0
1
Σ=1
1
cap
1
cap
1
All other combinations
0
Note 1: ’Σ=1’ means at least one variable is high.
Note 2: ’Fault’ is the logic OR of UVLO and thermal shutdown.
Note 3: ’Cap’ means the pin has a capacitor of appropriate value between it and ground.
Note 4: Positive logic is used.
Note 5: For meanings of the variables, refer to the block diagrams.
Note 6: A blank value means ’don’t care’.
TABLE 2. Power Good Truth Table
Input
ovp1
ovp2
uvpg1
uvpg2
uvpglr
Output
new
vid
ch1 on
ch2 on
fault
latch off
PGOOD
1
0
1
0
1
0
1
0
1
0
1
0
π=0
0
1
0
1
0
All other combinations
1
Note 7: ″π = 0″ means at least one variable is low.
Note 8: Positive logic is used.
Note 9: A blank value means ’don’t care’.
Note 10: For meanings of the variables, refer to the block diagrams.
TABLE 3. VID Code and DAC Output
VID4
VID3
VID2
VID1
VID0
DAC Voltage (V)
1
1
1
1
1
No CPU*
1
1
1
1
0
0.925
1
1
1
0
1
0.950
1
1
1
0
0
0.975
1
1
0
1
1
1.000
1
1
0
1
0
1.025
1
1
0
0
1
1.050
1
1
0
0
0
1.075
1
0
1
1
1
1.100
1
0
1
1
0
1.125
1
0
1
0
1
1.150
1
0
1
0
0
1.175
1
0
0
1
1
1.200
1
0
0
1
0
1.225
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6
VID4
VID3
VID2
VID1
VID0
DAC Voltage (V)
1
0
0
0
1
1.250
1
0
0
0
0
1.275
0
1
1
1
1
No CPU
0
1
1
1
0
1.30
0
1
1
0
1
1.35
0
1
1
0
0
1.40
0
1
0
1
1
1.45
0
1
0
1
0
1.50
0
1
0
0
1
1.55
0
1
0
0
0
1.60
0
0
1
1
1
1.65
0
0
1
1
0
1.70
0
0
1
0
1
1.75
0
0
1
0
0
1.80
0
0
0
1
1
1.85
0
0
0
1
0
1.90
0
0
0
0
1
1.95
0
0
0
0
0
2.00
*This code is set to 0.900V for convenience.
7
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LM2633
TABLE 3. VID Code and DAC Output (Continued)
LM2633
Absolute Maximum Ratings
(Note 11)
ESD Rating (Note 14)
Ambient Storage Temperature
Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
−0.3V to 31V
ILIM1, ILIM2
−0.3V to 31V
VID0-VID4
−0.3V to 5V
VLIN, VDD1, VDD2, PGOOD
−0.3V to 6V
FB1, FB2, SENSE2, G3, FB3, OUT3
−0.3V to 6V
−65˚C to +150˚C
Soldering Dwell Time, Temperature (Note 13)
Wave
4 sec, 260˚C
Infrared
10sec, 240˚C
Vapor Phase
75sec, 219˚C
Voltages from the indicated pins to GND/PGND:
VIN, KS1, KS2, SW1, SW2
2kV
Operating Ratings(Note 11)
CBOOT1
−0.3V to SW1+ 7V
VIN (VIN and VLIN5 tied
together)
CBOOT2
−0.3V to SW2+ 7V
VIN (VIN and VLIN5 separate)
4.5V to 5.5V
5.0V to 30V
ON/SS1, ON/SS2
−0.3V to 5V
Junction Temperature 1
0˚C to +125˚C
FPWM
−0.3V to 7V
Junction Temperature 2
−40˚C to +125˚C
Power Dissipation (TA = 25˚C),
(Note 12)
VDD1, VDD2
4.5V to 5.5V
1.56W
Junction Temperature
+150˚C
Electrical Characteristics
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over 0˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SYSTEM
∆Vout1_load
Channel 1 Load
Regulation (Note 17)
VCOMP1 moves from 0.5V to 1.5V,
VID4:0=01101
∆Vout2_load
Channel 2 Load
Regulation (Note 17)
VCOMP2 moves from 0.5V to 1.5V
∆Vfb
Line Regulation (for the
two switching regulators)
5.0V ≤ VIN ≤ 30V, VID4:0=01101
Ivin
Input Supply Current
with the Switching
Channels ON
VFB = 0.9V, no VLIN5 DC Current
(Note 18)
Ivin_sd
Input Supply Current
with the IC Shut Down
VON/SS1 = VON/SS2 = 0V
(Note 19)
Vvlin5
VLIN5 Output Voltage
IVLIN5 = 0 to 25mA, 5.5V < VIN <
30V
Iilim_pos
ILIM1 and ILIM2 Pins
Sink Current
Vilim_neg
Negative Current Limit
(SWx vs PGNDx
voltage)
Iss_sc
Soft Start Charge
Current
mV
1.5
mV
2
mV
1.5
2.4
mA
10
18
µA
4.7
5.0
5.3
V
8
10
12
µA
45
0.5
Iss_sk
Soft Start Sink Current
Vss_on
Soft Start ON Threshold
Vssto
Soft Start Timeout
Threshold
(Note 20)
Vuvd
UV_DELAY Threshold
VLIN5 = 5V (Note 21)
Idelay
UV_DELAY Source
Current
Ivid
VID4:0 Internal Pull Up
Current
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0
In UVLO or thermal shutdown
1.0
8
2.25
mV
5
µA
2
µA
1.2
V
3.5
V
2.1
V
5
9.0
µA
6
13
µA
(Continued)
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over 0˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
4.2
4.5
V
SYSTEM
Vuvlo_thr
VIN Under-voltage
Lockout (UVLO)
Threshold
Rising Edge
Vuvlo_hys
VIN UVLO Hysteresis
Vuvp1
Channel 1 VOUT
Under-voltage Shutdown
Latch Threshold
(Measured at the FB1)
VID4:0 = 01100
Channels 2 and 3 VOUT
Undervoltage Shutdown
Latch Threshold
(Measured at the FB2
and FB3)
VID4:0 = 01100
Vuvp2, 3
Vovp1
Vovp2
Vlreg_thr
300
mV
73
80
83
%VOUT
76
80
86
%VOUT
VOUT Overvoltage
Shutdown Latch
Threshold for Channel 1
(Measured at the FB1)
110
114
119
%VOUT
VOUT Overvoltage
Shutdown Latch
Threshold for Channel 2
(Measured at the FB2)
109
112
115
%VOUT
VOUT Low Regulation
Comparator Enable
Threshold for Channels
1 and 2
91.5
%VOUT
Vlreg_hys
Hysteresis of Low
Regulation Comparator
7
%VOUT
Vpwrbad
Regulator Window
Detector Thresholds
(PGOOD from High to
Low)
Vpwrgd
85
88
%VOUT
(Note 22)
Regulator Window
Detector Thresholds
(PGOOD from Low to
High)
110
112
119
90
93
97
%VOUT
Gate Drive (For Channel 1 Switching Regulator Controller)
Iboot1
CBOOT Leakage
Current
VCBOOT1 = 7V
100
nA
HDRV1 Source Current
VHDRV1 = VSW1 =0V, VCBOOT1 = 5V
1.2
A
HDRV1 Sink Current
VHDRV1 = 5V
1.0
A
LDRV1 Source Current
VLDRV1 = 0V
1.2
A
LDRV1 Sink Current
VLDRV1 = 5V
2.0
A
HDRV1 High-Side FET
On-Resistance
1.84
Ω
LDRV1 High-Side FET
On-Resistance
tbd
Ω
LDRV1 Low-Side FET
On-Resistance
0.5
9
Ω
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LM2633
Electrical Characteristics
LM2633
Electrical Characteristics
(Continued)
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over 0˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Gate Drive (For Channel 2 Switching Regulator Controller)
Iboot2
CBOOT Leakage
Current
VCBOOT2 = 7V
100
nA
HDRV2 Source Current
VHDRV2 = VSW2 =0V, VCBOOT2 = 5V
tbd
A
HDRV2 Sink Current
VHDRV2 = 5V
tbd
A
LDRV2 Source Current
VLDRV2 = 0V
tbd
A
LDRV2 Sink Current
VLDRV2 = 5V
tbd
A
HDRV2 FET
On-Resistance
tbd
Ω
LDRV2 FET
On-Resistance
tbd
Ω
Oscillator
Fosc
Oscillator Frequency
Toff_min
Minimum Off-Time
225
250
400
275
kHz
ns
Ton_min
Minimum On-Time
220
ns
55
µA
18
nA
70
nA
60
µA
1.96
V
576
µmho
Error Amplifier
Ifb1
Feedback Input Bias
Current, Channel 1
VFB1 = 2.4V
Ifb2
Feedback Input Bias
Current, Channel 2
VFB2 = 1.36V
Ifb3
Feedback Input Bias
Current, Channel 3
VFB3 = 1.36V
Icomp1,
Icomp2
COMP Output Sink
Current
VFB1 = 150% of measured 1.4V DAC,
VFB2 = 150% of measured bandgap,
VCOMP1 = VCOMP2 = 1V
Vcomp_max
COMP Pin Maximum
Voltage
Gm
Transconductance
tbd
DAC Output and VFB2
∆Vdac
Channel 1 DAC Output
Voltage Accuracy
VCOMP1 = 1V, DAC codes from 1.3V
to 1.6V
VCOMP1 = 1V, DAC codes from
0.925V to 1.25V and from 1.65V to
2.00V
Vfb2
Channel 2 DC Output
Voltage Accuracy
COMP2 pin from 0.5V to 1.8V
−1.5
1.5
%
−1.7
1.7
1.217
1.238
1.259
V
1.215
1.24
1.265
V
Linear Regulator Controller
Vfb3
Channel 3 DC Output
Voltage Accuracy
Vg3_sk
G3 Sink Current
20
µA
Ig3_sc
G3 Minimum Source
Current
20
mA
Vg3_max
G3 Maximum Voltage
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3.6
10
V
(Continued)
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over 0˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Logic Inputs and Outputs
Vih
Vil
Minimum High Level
Input Voltage (FPWM,
VID0-VID4)
2.0
V
Maximum Low Level
Input Voltage (FPWM,
ON/SS1, ON/SS2,
VID0-VID4)
0.8
Ioh_pg
PGOOD Output High
Current
PGOOD = 5.7V (Note 23)
Vol_pg
PGOOD Output Low
Voltage
PGOOD Sinking 20 µA
11
V
5
µA
0.3
V
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LM2633
Electrical Characteristics
LM2633
Electrical Characteristics
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over −40˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SYSTEM
∆Vout1_load
Channel 1 Load
Regulation (Note 17)
VCOMP1 moves from 0.5V to 1.5V,
VID4:0=01101
∆Vout2_load
Channel 2 Load
Regulation (Note 17)
VCOMP2 moves from 0.5V to 1.5V
∆Vfb
Line Regulation (for the
two switching regulators)
5.0V ≤ VIN ≤ 30V, VID4:0=01101
Ivin
Input Supply Current
with the Switching
Channels ON
VFB = 0.9V, no VLIN5 DC Current
(Note 18)
Ivin_sd
Input Supply Current
with the IC Shut Down
VON/SS1 = VON/SS2 = 0V
(Note 19)
Vvlin5
VLIN5 Output Voltage
IVLIN5 = 0 to 25mA, 5.5V < VIN <
30V
Iilim_pos
ILIM1 and ILIM2 Pins
Sink Current
Vilim_neg
Negative Current Limit
(SWx vs PGNDx
voltage)
Iss_sc
Soft Start Charge
Current
Soft Start Sink Current
Soft Start ON Threshold
Vssto
Soft Start Timeout
Threshold
(Note 20)
Vuvd
UV_DELAY Threshold
VLIN5 = 5V (Note 21)
Idelay
UV_DELAY Source
Current
Ivid
VID4:0 Internal Pull Up
Current
Vuvlo_thr
VIN Under-voltage
Lockout (UVLO)
Threshold
mV
2
mV
2.5
mA
10
18
µA
4.7
5.0
5.3
V
7
10
13
µA
In UVLO or thermal shutdown
1.0
2.25
mV
5
µA
2
µA
1.2
V
3.5
V
2.1
V
5
9.0
µA
6
13
µA
4.2
4.6
V
Rising Edge
Vuvlo_hys
VIN UVLO Hysteresis
Vuvp1
Channel 1 VOUT
Under-voltage Shutdown
Latch Threshold
(Measured at the FB1)
VID4:0 = 01100
Channels 2 and 3 VOUT
Undervoltage Shutdown
Latch Threshold
(Measured at the FB2
and FB3)
VID4:0 = 01100
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1.5
1.5
0.5
Iss_sk
Vovp1
mV
45
Vss_on
Vuvp2, 3
0
300
VOUT Overvoltage
Shutdown Latch
Threshold for Channel 1
(Measured at the FB1)
12
mV
72
80
84
%VOUT
75
80
87
%VOUT
109
114
120
%VOUT
(Continued)
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over −40˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
108
112
116
%VOUT
SYSTEM
Vovp2
Vlreg_thr
VOUT Overvoltage
Shutdown Latch
Threshold for Channel 2
(Measured at the FB2)
VOUT Low Regulation
Comparator Enable
Threshold for Channels
1 and 2
91.5
%VOUT
Vlreg_hys
Hysteresis of Low
Regulation Comparator
7
%VOUT
Vpwrbad
Regulator Window
Detector Thresholds
(PGOOD from High to
Low)
Vpwrgd
84
88
109
112
120
89
93
98
%VOUT
(Note 22)
Regulator Window
Detector Thresholds
(PGOOD from Low to
High)
%VOUT
Gate Drive (For Channel 1 Switching Regulator Controller)
Iboot1
CBOOT Leakage
Current
VCBOOT1 = 7V
100
nA
A
HDRV1 Source Current
VHDRV1 = VSW1 =0V, VCBOOT1 = 5V
1.2
HDRV1 Sink Current
VHDRV1 = 5V
1.0
A
LDRV1 Source Current
VLDRV1 = 0V
1.2
A
LDRV1 Sink Current
VLDRV1 = 5V
2.0
A
HDRV1 High-Side FET
On-Resistance
1.84
Ω
LDRV1 High-Side FET
On-Resistance
tbd
Ω
LDRV1 Low-Side FET
On-Resistance
0.5
Ω
100
nA
tbd
A
Gate Drive (For Channel 2 Switching Regulator Controller)
Iboot2
CBOOT Leakage
Current
VCBOOT2 = 7V
HDRV2 Source Current
VHDRV2 = VSW2 =0V, VCBOOT2 = 5V
HDRV2 Sink Current
VHDRV2 = 5V
tbd
A
LDRV2 Source Current
VLDRV2 = 0V
tbd
A
LDRV2 Sink Current
VLDRV2 = 5V
tbd
A
HDRV2 FET
On-Resistance
tbd
Ω
LDRV2 FET
On-Resistance
tbd
Ω
Oscillator
Fosc
Oscillator Frequency
225
250
275
kHz
Toff_min
Minimum Off-Time
400
ns
Ton_min
Minimum On-Time
220
ns
55
µA
Error Amplifier
Ifb1
Feedback Input Bias
Current, Channel 1
VFB1 = 2.4V
13
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LM2633
Electrical Characteristics
LM2633
Electrical Characteristics
(Continued)
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA
= TJ = +25˚C. Limits appearing in boldface type apply over −40˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Error Amplifier
Ifb2
Feedback Input Bias
Current, Channel 2
VFB2 = 1.36V
Ifb3
Feedback Input Bias
Current, Channel 3
VFB3 = 1.36V
Icomp1,
Icomp2
COMP Output Sink
Current
VFB1 = 150% of measured 1.4V DAC,
VFB2 = 150% of measured bandgap,
VCOMP1 = VCOMP2 = 1V
Vcomp_max
COMP Pin Maximum
Voltage
Gm
Transconductance
tbd
18
nA
70
nA
91
µA
1.96
V
576
µmho
DAC Output and VFB2
∆Vdac
Vfb2
Channel 1 DAC Output
Voltage Accuracy
Channel 2 DC Output
Voltage Accuracy
VCOMP1 = 1V, DAC codes from 1.3V
to 1.6V
−2.0
2.0
VCOMP1 = 1V, DAC codes from
0.925V to 1.25V and from 1.65V to
2.00V
−2.2
2.2
COMP2 pin from 0.5V to 1.8V
%
1.212
1.238
1.264
V
1.209
1.24
1.271
V
Linear Regulator Controller
Vfb3
Channel 3 DC Output
Voltage Accuracy
Vg3_sk
G3 Sink Current
20
µA
Ig3_sc
G3 Minimum Source
Current
20
mA
Vg3_max
G3 Maximum Voltage
3.6
V
Logic Inputs and Outputs
Vih
Vil
Minimum High Level
Input Voltage (FPWM,
VID0-VID4)
2.2
V
Maximum Low Level
Input Voltage (FPWM,
ON/SS1, ON/SS2,
VID0-VID4)
0.7
Ioh_pg
PGOOD Output High
Current
PGOOD = 5.7V (Note 23)
Vol_pg
PGOOD Output Low
Voltage
PGOOD Sinking 20 µA
V
5
µA
0.3
V
Note 11: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table.
Note 12: Maximum allowable power dissipation is calculated by using PDMAX = (TJMAX - TA)/θJA, where TJMAX is the maximum junction temperature, TA is the
ambient temperature and θJA is the junction-to-ambient thermal resistance of the specified package. The 1.56W rating results from using 150˚C, 25˚C, and 80˚C/W
for TJMAX, TA, and θJA respectively. A θJA of 90˚C/W represents the worst-case condition of no heat sinking of the 48-pin TSSOP. Heat sinking allows the safe
dissipation of more power. The Absolute Maximum power dissipation should be derated by 12.5mW per ˚C above 25˚C ambient. The LM2633 actively limits its
junction temperature to about 150˚C.
Note 13: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation.
Note 14: Except for ILIM1 and ILIM2 pins, which are 1.5kV. For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged
through a 1.5kΩ resistor.
Note 15: A typical is the center of characterization data taken with TA = TJ = 25˚C. Typical data are not guaranteed.
Note 16: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TA = TJ = 25˚C. All hot and cold
limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 17: This test simulates heavy load condition by changing COMP pin voltage.
Note 18: This parameter indicates how much current the LM2633 is drawing from the input supply when it is functioning but not driving external MOSFETs or a
bipoloar transistor.
www.national.com
14
LM2633
Electrical Characteristics
(Continued)
Note 19: This parameter indicates how much current the LM2633 is drawing from the input supply when it is completely shut off.
Note 20: When ON/SS1,2 pins are charged above this voltage, the under voltage protection feature is enabled.
Note 21: Above this voltage, the under-voltage protection is enabled.
Note 22: This is the same as over-voltage protection threshold.
Note 23: This is the amount of current PGOOD sinks when PGOOD is high and is forced to the voltage indicated
15
www.national.com
www.national.com
16
Typical Application
20000804
LM2633
LM2633
Typical Application
(Continued)
TABLE 4. Bill of Materials for Typical Application Circuit
ID
Number
Type
Size
Parameters
Qt.
Vendor
C1
25SP56M
Capacitor, OSCON
Radial, Φ x L = 10.5
x 10.5 mm2
25V, 56 µF, 25 mΩ,
3.2A
3
Sanyo
C2
T510E108M004AS
Capacitor, Tantalum
7.3 x 6.0 x 3.6 mm3
4V, 1 mF, 18 mΩ
3
Kemet
3
C3
T510E108M004AS
Capacitor, Tantalum
7.3 x 6.0 x 3.6 mm
4V, 1 mF, 18 mΩ
1
Kemet
C4
VJ1206S105MXJAC
Capacitor, Ceramic
1206
16V, 1 µF, X7S
1
Vishay
C5
VJ1206S105MXJAC
Capacitor, Ceramic
1206
16V, 1 µF, X7S
1
Vishay
C6
VJ0805Y104MXAAB
Capacitor, Ceramic
0805
50V, 0.1 µF, X7R
1
Vishay
C7
VJ0805Y153MXJAB
Capacitor, Ceramic
0805
16V, 0.015 µF, X7R
1
Vishay
C8
VJ0805Y103MXAAB
Capacitor, Ceramic
0805
50V, 0.01 µF, X7R
1
Vishay
C9
VJ0805Y103MXAAB
Capacitor, Ceramic
0805
50V, 0.01 µF, X7R
1
Vishay
C10
VJ0805Y222MXJAB
Capacitor, Ceramic
0805
16V, 2200 pF, X7R
1
Vishay
C11
VJ0805Y681MXJAB
Capacitor, Ceramic
0805
16V, 680 pF, X7R
1
Vishay
C12
VJ0805Y472MXJAB
Capacitor, Ceramic
0805
16V, 4700 pF, X7R
1
Vishay
C13
VJ0805Y472MXJAB
Capacitor, Ceramic
0805
16V, 4700 pF, X7R
1
Vishay
C14
VJ0805Y821MXJAB
Capacitor, Ceramic
0805
16V, 820 pF, X7R
1
Vishay
C15
VJ0805A221MXAAB
Capacitor, Ceramic
0805
50V, 220 pF, X7R
1
Vishay
C16
VJ0805Y474MXJAB
Capacitor, Ceramic
0805
16V, 0.47 µF, X7R
1
Vishay
C17
VJ1206S105MXJAC
Capacitor, Ceramic
1206
16V, 1 µF, X7S
1
Vishay
C18
VJ0805Y104MXJAC
Capacitor, Ceramic
0805
16V, 0.1 µF, X7R
1
Vishay
C19
VJ0805Y104MXJAC
Capacitor, Ceramic
0805
16V, 0.1 µF, X7R
1
Vishay
D1
BAT54
Diode, Schottky
SOT-23
30V, 200 mA
1
Vishay
D2
BAT54
Diode, Schottky
SOT-23
30V, 200 mA
1
Vishay
D3
Diode, Schottky
1
(optional)
D4
Diode, Schottky
1
(optional)
2
L1
CEPH149-1R6MC
Inductor, Power
14.6 x 14.6 mm
1.6 µH, 15.5A, 1.5 mΩ
1
Sumida
L2
CDRH127-100MC
Inductor, Power
12 x 12 mm2
10 µH, 5.4A, 21.6 mΩ
1
Sumida
Q1
IRF7805
MOSFET, N-CHAN
SO-8
30V, 10 mΩ @ 4.5V
1
IR
Q2
IRF7805
MOSFET, N-CHAN
SO-8
30V, 10 mΩ @ 4.5V
2
IR
Q3
IRF7807
MOSFET, N-CHAN
SO-8
30V, 25 mΩ @ 4.5V
1
IR
Q4
IRF7807
MOSFET, N-CHAN
SO-8
30V, 25 mΩ @ 4.5V
1
IR
Q5
MMBT2222ALT1
BJT, NPN
SOT-23
40V, 600 mA
1
Motorola
R1
CRCW0805 100J
Resistor
0805
10Ω, 5%
1
Vishay
R2
CRCW0805 104J
Resistor
0805
100 kΩ, 5%
1
Vishay
R3
CRCW0805 1002F
Resistor
0805
10.0 kΩ, 1%
1
Vishay
R4
CRCW0805 4752F
Resistor
0805
47.5 kΩ, 1%
1
Vishay
R5
CRCW0805 2612F
Resistor
0805
26.1 kΩ, 1%
1
Vishay
R6
CRCW0805 2872F
Resistor
0805
28.7Ω, 1%
1
Vishay
R7
CRCW0805 243J
Resistor
0805
24 kΩ, 5%
1
Vishay
R8
CRCW0805 512J
Resistor
0805
5.1 kΩ, 5%
1
Vishay
R9
CRCW0805 683J
Resistor
0805
68 kΩ, 5%
1
Vishay
R10
CRCW0805 562J
Resistor
0805
5.6 kΩ, 5%
1
Vishay
R11
CRCW0805 1002F
Resistor
0805
10.0 kΩ, 1%
1
Vishay
R12
CRCW0805 1002F
Resistor
0805
10.0 kΩ, 1%
1
Vishay
R13
CRCW0805 100J
Resistor
0805
10Ω, 5%
1
Vishay
R14
CRCW0805 104J
Resistor
0805
100 kΩ, 5%
1
Vishay
U1
LM2633M
IC
TSSOP-48
3-in-1 control
1
National
(For performance, see Typical Performance Curves)
17
www.national.com
LM2633
Typical Performance Characteristics
Efficiency vs Load Current
(Ch1, Typical Application)
Efficiency vs Load Current
(Ch2, Typical Application, FPWM = 0)
200008A1
20000898
Efficiency vs Load Current
(Ch2, Typical Application, FPWM = 1)
Switching Frequency vs Load Current
20000899
20000890
PWM Frequency vs Temperature
Error Amplifier Transconductance vs Temperature
200008A3
www.national.com
200008A4
18
(Continued)
VLIN5 Voltage vs Temperature
Ch2 Reference Voltage vs Temperature
20000894
200008B5
Current Sourcing Capability of
Pin G3 vs Its Voltage
DAC Voltage vs Temperature (Ch 1)
20000897
200008A6
Force-PWM Operation
(Typical Application, Ch 1 Load = 120 mA)
Bias Current of Pin ILMx vs Temperature
200008A2
200008A5
19
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LM2633
Typical Performance Characteristics
LM2633
Typical Performance Characteristics
(Continued)
Skip-Mode Operation
(Typical Application, Ch 1 Load = 120 mA)
Soft Start with Constant Load Current
20000892
200008B3
Soft Start Under No Load
(Ch 1 , Typical Application)
Load Transient Response
(Ch 1 , Typical Application, VOUT1 = 1.6V)
200008B4
200008A9
Control-Output Bode Plot
(Ch1, Typical Application, VIN= 8V, No Load)
Current Limit and UVP
20000891
20000893
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20
LM2633
Typical Performance Characteristics
(Continued)
Loop Bode Plot (Ch1, Typical Application, VIN = 8V,
VOUT1 = 1.6V, No Load,
Compensation: C14 = 390pF, R9 = 100k, C15 = 150pF,
R10 = 8.2k)
Control-Output Bode Plot
(Ch2, Typical Application, VIN = 8V, No Load)
200008B1
20000896
Loop Bode Plot (Ch2, Typical Application, VIN = 8V, No
Load,
Compensation: C10 = 5.6 nF, R7 = 30k, C11 = 560pF,
R8 = 5.1k)
200008B2
21
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LM2633
When the ON/SSx pin voltage exceeds 3.5V, a soft start time
out signal (sstox) will be issued. This signal enables the
under-voltage protection. See the Under-Voltage Protection
section.
Operation Descriptions
General
The LM2633 is a combination of three voltage regulator
controllers. Among them, two are switching regulator controllers and one is a linear regulator controller. The two switching controllers, Channel 1 and Channel 2, operate 180˚ out
of phase. They can be independently enabled and disabled.
The linear controller, or Channel 3, is disabled only when
both switching channels are disabled. Channel 1 output
voltage is set by an internal DAC, which accepts a 5-bit VID
code from pins 6 through 10. Channels 2 and 3 output
voltages are adjusted with a voltage divider. Both switching
channels are synchronous and employ peak current mode
control scheme. Protection features include over-voltage
protection (Ch1 and 2), under-voltage protection (all channels), and positive and negative peak current limit (Ch1 and
2). UVP function can be delayed by an arbitrary amount of
time. Input voltage to the switching regulators can range
from 4.5V to 30V. The linear controller can generate a maximum 3.8V gate/base drive voltage. With an external NPN
transistor, output voltage can go up to 3.0V. The power good
function always monitors all three output voltages.
Shutdown Mode
If both ON/SSx pins are pulled low, the IC will be in shut
down mode. Both top gate-drives of the two switching channels are turned off while both bottom gate-drives remain on.
The linear channel is also disabled.
The same thing happens to the gate drives when the input
voltage is brought below the UVLO threshold.
Turning Off a Switching Channel
A switching channel can be turned off by pulling its ON/SSx
pin below about 1.1V. Upon detecting a low level on ON/SSx
pin, the corresponding top gate-drive will be turned off and
the bottom gate-drive will be turned on.
In a high current application, it may be necessary to take
special measures to make sure that the output voltage does
not go too negative during shutdown. One of those measures is to add a Schottky diode in parallel with output
capacitors. Another measure is to fine tune the power stage
parameters such as inductance and capacitance values.
Soft Start
If the ON/SSx pin is connected to ground instead of to a
capacitor, the corresponding channel is turned off and will
not start up.
Assume the ON/SSx pin is connected to a capacitor and the
rest of the circuit is set up correctly. When the input voltage
rises above the 4.2V threshold, the internal circuitry is powered on, the ON/SSx pin should be already held at 1.1V, and
a 2µA current starts to charge the capacitor connected between the ON/SSx pin and ground. When the ON/SSx pin
voltage exceeds 1.2V, the corresponding channel is turned
on. A MIN_ON_TIME comparator generates the soft start
PWM pulses. As the ON/SSx pin voltage ramps up, the duty
cycle grows, causing the output voltage to ramp up. During
this time, the error amplifier output voltage is clamped at
0.8V, and the duty cycle generated by the PWM comparator
is ignored. When the corresponding output voltage exceeds
99% of the set target voltage, the mode of the channel
transitions from soft start to operating. As a result, the high
clamp at the output of the error amplifier is switched to 2V.
Beyond this point, once the PWM pulses generated by the
PWM comparator are wider than that generated by the MIN_ON_TIME comparator, the PWM comparator takes over
and starts to regulate the output voltage. That is, peak
current mode control now takes place.
The speed at which the duty cycle grows depends on the
capacitance of the soft start capacitor. The higher the capacitance, the slower the speed. However, that speed is
independent of how fast the input voltage rises. That is
because the ramp signal used to generate the soft start duty
cycle has a slope proportional to input voltage, making the
product of duty cycle and input voltage a value that is independent of input voltage. This feature makes the soft start
process more predictable and reliable because whether the
input power supply goes through a soft start process or is
applied abruptly does not affect the LM2633 soft start.
During soft start, under-voltage protection is disabled. But
over-voltage protection and current limit are in place.
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Fault State
Whenever the input voltage becomes too low (less than
about 3.9V), or the IC is too hot and enters thermal shut
down mode, a ’fault’ signal will be generated internally. This
signal will discharge the capacitor connected between the
ON/SSx pin and ground with 3 µA of current until the pin
reaches 1.1V. The switching channels will be turned off upon
seeing this signal.
In the fault state, OVP and UVP are disabled and shut down
latch is released.
Force-PWM Mode
This mode applies to both switching channels simultaneously. The force-PWM mode is activated by pulling
the FPWM pin to logic low. In this mode, the top FET and the
bottom FET gate signals are always complementary to each
other. The 0-CROSSING / NEGATIVE CURRENT LIMIT
comparator will be set to detect the negative current limit. In
force-PWM mode, the regulator always operates in Continuous Conduction Mode (CCM) and its steady-state duty cycle
(approximately VOUT / VIN) is almost independent of load.
The force-PWM mode is good for applications where fixed
switching frequency is required. It also offers the fastest load
transient response.
In force-PWM mode, the top FET has to be turned on for a
minimum of 220ns each cycle. However, when the required
duty cycle is less than the minimum value, the skip comparator will be activated and pulses will be skipped to maintain
regulation.
Skip Comparator
Whenever the COMPx pin voltage goes below the 0.5V
threshold, the PWM cycles will be ’skipped’ until that voltage
again exceeds the threshold.
Pulse-Skip Mode
This mode is activated by pulling the FPWM pin to a
TTL-compatible logic high and applies to both switching
channels simultaneously. In this mode, the 0-CROSSING /
NEGATIVE CURRENT LIMIT comparator detects the bottom
22
LM2633
Operation Descriptions
(Continued)
FET current. Once the bottom FET current flows from drain
to source, the bottom FET will be turned off. This prevents
negative inductor current. In force-PWM operation, the inductor current is allowed to go negative, so the regulator is
always in Continuous Conduction Mode (CCM), no matter
what the load is. In CCM, the steady-state duty cycle is
almost independent of the load, and is roughly VOUT divided
by VIN. In pulse-skip mode, the regulator enters Discontinuous Conduction Mode (DCM) under light load. Once the
regulator enters DCM, its steady-state duty cycle droops as
the load current decreases. The regulator operates in DCM
PWM mode until its duty cycle falls below 85% of the CCM
duty cycle, when the MIN_ON_TIME comparator takes over.
It forces 85% CCM duty cycle which causes the output
voltage to continuously rise and COMPx pin voltage (error
amplifier output voltage) to continuously droop. When the
COMPx pin voltage dips below 0.5V, the CYCLE_SKIP comparator toggles, causing the present switching cycle to be
’skipped’, i.e., both FETs remain off during the whole cycle.
As long as the COMPx pin voltage is below 0.5V, no switching of the FETs will happen. As a result, the output voltage
will droop, and the COMPx pin voltage will rise. When the
COMPx pin goes above 0.5V, the CYCLE_SKIP comparator
flips and allows a 85% CCM duty cycle pulse to happen. If
the load current is so small that this single pulse is enough to
bring output voltage up to such a level that the COMPx pin
drops below 0.5V again, the pulse skipping will happen
again. Otherwise it may take a number of consecutive pulses
to bring the COMPx pin voltage down to 0.5V again. As the
load current increases, it takes more and more consecutive
pulses to discharge the COMPx voltage to 0.5V. When the
load current is so high that the duty cycle exceeds the 85%
CCM duty cycle, then pulse-skipping disappears. In
pulse-skip mode, the frequency of the switching pulses decreases as the load current decreases.
The LM2633 needs to sense the output voltages directly in
the pulse-skip mode operation. For Channel 1 this is realized
through the FB1 pin. For Channel 2, it is realized by connecting SENSE2 pin to the output.
The LM2633 pulse-skip mode helps the light load efficiency
for two reasons. First, it does not turn on the bottom FET, this
eliminates circulating energy and reduces gate drive power
loss. Second, the top FET is only turned on when necessary,
rather than every cycle, which also reduces gate drive power
loss.
20000805
FIGURE 1. Current Limit Method
There is a 10 µA current sink on the ILIMx pin. When an
external resistor is connected between ILIMx pin and top
FET drain, a DC voltage is established between the two
nodes. When the top FET is turned on, the voltage across
the FET is proportional to the inductor current. If the inductor
current is too high, SWx pin voltage will be lower than the
ILIMx voltage, causing the comparator to toggle and thus the
top FET will be turned off immediately. The comparator is
disabled when the top FET is turned off and during the
leading edge blanking time.
Negative Current Limit
The negative current limit is put in place to ensure that the
inductor will not saturate during a negative current flow and
cause excessive current to flow through the bottom FET. The
negative current limit is realized through sensing the bottom
FET Vds. An internal reference voltage is used to compare
with the bottom FET Vds when it is on. Upon seeing too high
a Vds, the bottom FET will be turned off. The negative
current limit is activated in force PWM mode, or in the case
of Channel 1, also whenever there is a dynamic VID change.
Active Frequency Control
As the input / output voltage differential increases, the on
time of the top FET as regulated by the feed-back control
circuitry may approach the minimum value, i.e. the blanking
time. That will cause unstable operations such as pulse
skipping and uneven duty cycles. To avoid such an issue, the
LM2633 is designed in such a way that when input voltage
rises above about 17V, the PWM frequency starts to droop.
The frequency droops fairly linearly with the input voltage.
See typical curves. The theoretical equation for PWM frequency is ƒ = min (1, 17V/VIN) x 250 kHz.
The main impact of this shift in PWM frequency is the
inductor ripple current and output ripple voltage. Regulator
design should take this into account.
Current Sensing and Current Limiting
Sensing of the inductor current for feedback control is accomplished through sensing the drain-source voltage of the
top FET when it is turned on. There is a leading edge
blanking circuitry that forces the top FET to be on for at least
160ns. Beyond this minimum on time, the output of the PWM
comparator is used to turn off the top FET. The blanking
circuitry is being used to blank out the noise associated with
the turning on of the top FET.
Current limit is implemented using the same Vds information.
See Figure 1.
Shutdown Latch State
This state is typically caused by an output under voltage or
over voltage event. In this state, both switching channels
have their top FETs turned off, and their bottom FETs turned
on. The linear channel is not affected.
There are two methods to release the system from the latch
state. One is to create a fault state (see the corresponding
section) by either bringing down the input voltage to below
3.9V UVLO threshold and then bringing it back to above
4.2V, or somehow by causing the system to enter thermal
shut down. Another method is to pull both ON/SSx pins
below 0.8V and then release them.
After the latch is released, the two switching channels will go
through the normal soft start process. The linear channel
23
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LM2633
Operation Descriptions
Power good upper limit is the same as that of the OVP
function.
(Continued)
output voltage will not be affected unless the UVLO method
is used to release the latch. If the linear channel causes a
UVP event, then the IC enters Shut Down Latch State. If
later the fault at the linear channel is removed, the linear
channel will recover, but the IC will still be in the latch state.
In cases 2 and 3 above, if the corresponding output voltage(s) recovers, PGOOD will be asserted again. But there is
a built-in hysteresis. See Vpwrgd in the Electrical Characteristics Table. The above information is also available in Power
Good Truth Table.
When the internal power good MOSFET is turned on, the
PGOOD pin will be pulled to ground. When it is turned off,
the PGOOD pin floats (open-drain). The on resistance of the
power good MOSFET is about 15kΩ.
Over-voltage Protection
This protection feature is implemented in the two switching
channels and not in the linear channel. Refer to Table 1. As
long as there is at least one switching channel enabled, and
the LM2633 is not in fault state, an over voltage event at
either of the two switching channels’ output will cause system to enter the Shut Down Latch State.
However, if the over voltage event happens only on Channel
1 after a dynamic VID change signal is issued and before the
change completes, the system will not enter the Shut Down
Latch State. See the Dynamic VID Change section.
Dynamic VID Change
During normal operation, if Channel 1 sees a change in the
VID pattern, a NEW VID signal will be issued. Upon seeing
the NEW VID signal, power good signal will be deasserted,
UVP and OVP of Channel 1 will be disabled temporarily, and
Channel 1 goes through a special step to quickly ramp the
output voltage to the new value.
If the new output voltage is higher than the old voltage,
Channel 1 will rely on the control loop to change the output
voltage. If the new value is lower than the old one, the top
FET is going to remain off while the bottom FET is going to
remain on. This will cause the output capacitor to discharge
through the inductor. The 0-CROSSING / NEGATIVE CURRENT LIMIT comparator will detect for negative over current,
even if the LM2633 is in pulse-skip mode. When the negative
current limit is reached, bottom FET will be turned off, forcing
the inductor current to flow through the body diode of the top
FET to the input supply. When next clock cycle comes, the
bottom FET will be turned on again, and it will not be turned
off until the negative current limit is reached again. During
this process, if the output voltage goes below the new voltage, the NEW VID signal will be deasserted. At this time,
power good function will be released, OVP and UVP will be
enabled and the bottom FET will be turned off. The normal
control loop takes over after the output voltage droops below
the new DAC voltage.
Under-voltage Protection
The UVP feature is implemented in all three channels.
If the UV_DELAY pin is pulled to ground, then the undervoltage protection feature is disabled. Otherwise, if a capacitor is connected between the UV_DELAY pin and ground,
the UVP is enabled. Assume UVP is enabled and the system
is not in fault state. If a switching channel is enabled, and its
soft start time out signal (sstox, see soft start section) is
asserted, then an under voltage event at the output of that
channel will cause the system to enter the Shut Down Latch
State.
However, if the under voltage event happens only on Channel 1 after a dynamic VID change signal is issued and before
the change completes, the system will not enter the Shut
Down Latch State. See the Dynamic VID Change section.
For the linear channel, if there is at least one switching
channel on, and at least one soft start time out signal has
been issued, and if the system is not in Fault State, then an
under voltage event at the linear regulator output will cause
the system to enter Shut Down Latch State.
When the LM2633 reacts on an under voltage event, a 5 µA
current will be charging the capacitor connected to the
UV_DELAY pin and when its voltage exceeds 2.1V, the
system immediately enters Shut Down Latch State.
For details, see the block diagram and Shut Down Latch
Truth Table.
Internal 5V Supply
The internal 5V supply is generated from the VIN voltage
through an internal linear regulator. This 5V supply is mainly
for internal circuitry use, but can also be used externally
(through the VLIN5 pin) for convenience. A typical use of this
5V is supplying the bootstrap circuitry for top drivers and
supplying the voltage needed by the bottom drivers (through
the VDDx pins). But since this 5V is generated by a linear
regulator, it may hurt the light load efficiency, especially
when VIN voltage is high. So if there is a separate 5V
available that is generated by a switching power supply, it
may be a good idea to use that 5V to power the bootstrap
circuitry and the VDDx pins for better efficiency and less
thermal stress on the LM2633.
In shut down mode, the VLIN5 pin will go to 5.5V. So it is
recommended not to use this voltage for purposes other
than the bootstrap circuitry and VDDx pins.
When the power stage input voltage can be guaranteed to
be within 4.5V to 5.5V, the VLIN5 pin can be tied to the VIN
pin directly. In this mode, all 5V currents are directly coming
from power stage input rail VIN and power loss due to the
internal linear regulation is no longer an issue.
Power Good Function
The power good function is a general indication of the health
of the regulators. There is an internal MOSFET tied from the
PGOOD pin to ground. Power good signal is asserted by
turning off that MOSFET.
The internal power good MOSFET will not be turned on
unless at least one of the following occurs:
1. There is an output over voltage event in at least one of
the switching channels.
2. The output voltage of any of the three channels is below
the power good lower limit, regardless of ON/SSx pin
voltage level.
3. Whenever Channel 1 is going through a dynamic VID
change.
4. System is in the shut down mode.
5. System is in the fault state.
6. System is in the shut down latch state.
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Design Procedures
CPU Core / GTL Bus Power Supply
Nomenclature
24
The design procedures that follow are generally appropriate
for both the CPU core and the GTL bus power supplies,
although emphasis is placed on the former. When there is a
difference between the two, it will be pointed out.
(Continued)
ESR - Equivalent Series Resistance.
Loading transient - a load transient when the load current
goes from minimum load to full load.
Output Capacitor Selection
Unloading transient - a load transient when the load current
goes from full load to minimum load.
C - regulator output capacitance.
D - duty cycle.
f - switching frequency.
Inlim - negative current limit level.
Type of output capacitors
Different type of capacitors often have different combinations
of capacitance and ESR. High-capacitance multi-layer ceramic capacitors (MLCs) have very low ESR, typically 12mΩ,
but also relatively low capacitance - up to 100µF. Tantalum
capacitors can have fairly low ESR, such as 18mΩ, and
pretty high capacitance - up to 1mF. Aluminum capacitors
can have very high capacitance and fairly low ESR. OSCON
capacitors can achieve ESR values that are even lower than
those of MLCs’ while having a higher capacitance.
Tutorial on load transient response
Skip to the next subsection when a quick design is desired.
The control loop of the LM2633 can be made fast enough so
that when a worst-case load transient happens, duty cycle
will saturate (meaning it jumps to either 0% or Dmax). If the
control loop is fast enough, the worst situation for a load
transient will be that the transient happens when the following three are also happening. One, present PWM pulse has
just finished. Two, input voltage is the highest. Three, the
load current goes from maximum down to minimum (referred
to as an unloading transient). Figure 2 shows how inductor
current changes during a worst-case load transient. The
reasons are as follows. In a mobile CPU application, the
input/output voltage differential, which is applied across the
inductor during a loading transient, is higher than the output
voltage, which is applied across the inductor during an unloading transient.
Iilim - ILIMx pin current.
Iirrm - maximum input current ripple RMS value.
Iload - load current.
Irip - output inductor peak-to-peak ripple current.
± δ% - CPU core voltage regulation window.
± λ% - LM2633 initial DAC tolerance.
∆Vc_s - maximum allowed CPU core voltage excursion during a load transient, as derived from CPU specifications.
∆Ic_s - maximum load current change during a load transient,
as specified by the CPU manufacturer.
L - inductance of the output inductor.
Re - total combined ESR of output capacitors.
Re_s - maximum allowed total combined ESR of the output
capacitors, as derived from CPU load transient specifications.
Rilim - current limit adjustment resistance. See Current Sensing and Current Limiting.
tmax - maximum allowed dynamic VID transition time.
tpeak - time for the CPU core voltage to reach its peak value
during an unloading transient.
Vin - input voltage to the switching regulators.
Vn - nominal output voltage.
Vold - nominal CPU core voltage before dynamic VID
change.
Vnew - nominal CPU core voltage after dynamic VID change.
Vrip - peak-to-peak output ripple voltage.
General
Designing a power supply involves many tradeoffs. A good
design is usually a design that makes good tradeoffs. Today’s synchronous buck regulators typically run at a 200kHz
to 300kHz switching frequency. Beyond this range, switching
loss becomes excessive, and below this range, inductor size
becomes unnecessarily large. The LM2633 has a fixed operating frequency of 250kHz when VIN voltage is below
about 17V, and has decreased frequency when VIN voltage
exceeds 17V. See Active Frequency Control section.
In a mobile CPU application, both the CPU core and the GTL
bus exhibit large and fast load current swings. The load
current slew rate during such a transient is usually well
beyond the response speed of the regulator. To meet the
regulation specification, special considerations should be
given to the component selection. For example, the total
combined ESR of the output capacitors must be lower than a
certain value. Also because of the tight regulation specification, only a small budget can be assigned to ripple voltage,
typically less than 20mV. It is found that starting from a given
output voltage ripple will often result in fewer design iterations.
20000806
FIGURE 2. Worst-case Load Transient
That means the inductor current changes slower during an
unloading transient than during a loading transient. The
slower the inductor current changes during a load transient,
the higher output capacitance is needed. That is why an
unloading transient is the worst case. If the load transient
happens when the present PWM pulse has just finished, the
inductor current will be the highest, which means highest
initial charging current for the output capacitors. Finally, the
higher the input voltage, the higher the inductor ripple current and the higher the initial charging current for the output
capacitors.
25
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LM2633
Design Procedures
LM2633
Output Capacitor Selection
The total change in output voltage during such a load transient is:
(3)
∆Vc = ∆Vr + ∆Vq
(Continued)
From Figure 4 it can be told that ∆Vc will reach its peak value
at some point in time and then it is going to decrease. The
larger the output capacitance is, the earlier the peak will
happen. If the capacitance is large enough, the peak will
occur at the beginning of the transient, i.e., ∆Vc will decrease
monotonically after the transient happens. To find the peak
position, let the derivative of ∆Vc go to zero, and the result is:
(4)
The target is to find the capacitance value that will yield, at
tpeak, a ∆Vc that equals ∆Vc_s. By plugging tpeak expression
into the ∆VC expression and equating the latter to ∆Vc_s, the
following formula is obtained:
20000807
FIGURE 3. Load Transient Spec. Violation
Because the response speed of the regulator is slow compared to a typical CPU load transient, the regulator has to
rely heavily on the output capacitors to handle the load
transient. The initial overshoot or undershoot is caused by
the ESR of the output capacitors. How the output voltage
recovers after that initial excursion depends on how fast the
output inductor current ramps and how large the output
capacitance is. See Figure 3. If the total combined ESR of
the output capacitors is not low enough, the initial output
voltage excursion will violate the specification, see ∆Vc1. If
the ESR is low enough, but there is not enough output
capacitance, output voltage will have too much an extra
excursion and travel outside the specification window, before
it returns to its nominal value, see ∆Vc2.
(5)
Notice it is already assumed the total ESR is no greater than
Re_s otherwise the term under the square root will be a
negative value.
20000813
FIGURE 5. Re = Re_s vs Re < Re_s
There are two scenarios when calculating the Cmin. See
Figure 5. One is that Re is equal to Re_s so there is absolutely no room for ∆Vq, which means tpeak = 0s. The other is
that Re is smaller than Re_s so there is some room for ∆Vq,
which means tpeak is greater than zero. However, it is not
necessary to differentiate between the two scenarios when
figuring out the Cmin by the above formula.
Allowed transient voltage excursion
The allowed output voltage excursion during a load transient
is:
20000808
FIGURE 4. Delta Output Voltage Components
During a load transient, the delta output voltage ∆Vc has two
changing components. One is the delta voltage across the
ESR (∆Vr), the other is the delta voltage caused by the
gained charge (∆Vq). Both delta voltages change with time.
For ∆Vr, the equation is:
(1)
(6)
Example: Vn = 1.35V, δ% = 7.5%, λ% = 1.4%, Vrip = 20mV
and for ∆Vq, the equation is:
(2)
Since the ripple voltage is included in the calculation of
∆Vc_s, the inductor ripple current should not be included in
the worst-case load current excursion. That is, the
worst-case load current excursion should be simply ∆Ic_s.
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26
LM2633
Output Capacitor Selection
(Continued)
Maximum ESR calculation
No matter how much capacitance there is, if the total combined ESR is not less than a certain value, the load transient
requirement will not be met.
The maximum allowed total combined ESR is:
Generally speaking, Cmax decreases with decreasing tmax,
Inlim and Iload, but with increasing voltage step.
Power loss in output capacitors
In a typical buck regulator, the ripple current in the inductor
(and thus the output capacitors) is so small that it causes
very little power loss. The equation for calculating that loss
is:
(7)
Example: ∆Vc_s = 72mV, ∆Ic_s = 10A. Then Re_s = 7.2mΩ.
Maximum ESR criterion can be used when the capacitance
is high enough, otherwise more capacitors than the number
determined by this criterion should be used.
Minimum capacitance calculation
In a CPU core or a GTL bus power supply, the minimum
output capacitance is typically dictated by the load transient
requirement. If there is not enough capacitance, the output
voltage excursion will exceed the maximum allowed value
even if the maximum ESR requirement is met. The
worst-case load transient is an unloading transient that happens when the input voltage is the highest and when the top
FET has just been turned off. The corresponding minimum
capacitance is calculated as follows:
(10)
Example: Irip = 4.3A, Re = 7 mΩ.
(11)
Output Inductor Selection
The size of the output inductor can be determined from the
assigned output ripple voltage budget and the impedance of
the output capacitors at switching frequency. The equation to
determine the minimum inductance value is as follows:
(12)
where min(Vin_max, 17V) means the smaller of Vin_max and
17V. The reason this term is not simply Vin_max is that the
switching frequency droops with increasing Vin when Vin is
higher than 17V. See Active Frequency Control.
In the above equation, Re is used in place of the impedance
of the output capacitors. This is because in most cases, the
impedance of the output capacitors at the switching frequency is very close to Re. In the case of ceramic capacitors,
replace Re with the true impedance.
Example 1: Vin_max = 21V, Vn = 1.6V, Vrip = 26mV, Re =
6mΩ, f = 250kHz.
(8)
Notice it is already assumed the total ESR is no greater than
Re_s, otherwise the term under the square root will be a
negative value.
Example: Re = 6mΩ, Vn = 1.35V, ∆Vc_s = 72mV, ∆Ic_s =
10A, L = 2µH
Generally speaking, Cmin decreases with decreasing Re,
∆Ic_s, and L, but with increasing Vn and ∆Vc_s.
Maximum capacitance calculation
This subsection applies to Channel 1 / CPU core power
supply only.
If there is a need to change the CPU core voltage dynamically (see Dynamic VID Change), there will be a maximum
output capacitance restriction. If the output capacitance is
too large, it will take too much time for the CPU core voltage
to ramp to the new value, violating the maximum transition
time specification. The worst-case dynamic VID change is
one that takes the largest step down at no load. The maximum capacitance as determined by the way LM2633 implements the VID change can be calculated as follows:
Example 2: Vin_max = 18V, Vn = 1.35V, Vrip = 20mV, Re =
6mΩ, f = 250kHz.
The actual selection process usually involves several iterations of all of the above steps, from ripple voltage selection,
to capacitor selection, to inductance calculations. Both the
highest and the lowest CPU core voltages and their load
transient requirements should be considered. If an inductance value larger than Lmin is selected, make sure the Cmin
requirement is not violated. Priority should be given to parameters that are not flexible or more costly. For example, if
there are very few types of capacitors to choose from, it may
(9)
Example: tmax = 100µs, Inlim = 20A, Vold = 1.6V, Vnew =
1.35V, Iload = 0.
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LM2633
Output Inductor Selection
current. In the case of two FETs in parallel, multiply the
calculated on resistance by 4 to obtain the on resistance for
each FET. In the case of three FETs, that number is 9. Since
efficiency is very important in a mobile PC, having the lowest
on resistance is usually more important than fully utilizing the
thermal capacity of the package. So it is probably better to
find the lowest-Rds FET first, and then determine how many
are needed.
Example: Tj_max = 100˚C, Ta_max = 60˚C, Rθja = 60˚C/W,
Vin_max = 21V, Vn = 1.6V, and Iload_max = 10A.
(Continued)
be a good idea to adjust the inductance value so that a
requirement of 3.2 capacitors can be reduced to 3 capacitors.
Inductor ripple current is often the criterion for selecting an
output inductor. However, in the CPU core or GTL bus
application, it is usually of lower priority. That is partly because the stringent output ripple voltage requirement automatically limits the inductor ripple current level. It is nevertheless a good idea to double check the ripple current. The
equation is:
(13)
where min(Vin_max, 17V) means the smaller of Vin_max and
17V.
What is more important is the ripple content, which is defined
by Irip_max / Iload_max. Generally speaking, a ripple content of
less than 50% is ok. Too high a ripple content will cause too
much loss in the inductor.
Example: Vin_max = 21V, Vn = 1.6V, f = 250kHz, L = 1.7µH.
If the lowest-on-resistance FET has a Rds_max of 10mΩ, then
two can be used in parallel. The temperature rise on each
FET will not go to Tj_max because each FET is now dissipating only half of the total power.
Alternatively, two 22mΩ FETs can be used in parallel, with
each FET reaching Tj_max. This may lower the FET cost, but
will double the bottom switch power loss.
Top FET Selection
The top FET has two types of power losses - the switching
loss and the conduction loss. The switching loss mainly
consists of the cross-over loss and the bottom diode reverse
recovery loss. It is rather difficult to estimate the switching
loss. A general starting point is to allot 60% of the top FET
thermal capacity to switching loss. The best way to find out is
still to test it on bench. The equation for calculating the on
resistance of the top FET is thus:
If the maximum load current is 14A, then the ripple content is
4.3A / 14A = 30%.
When choosing the inductor, the saturation current should
be higher than the maximum peak inductor current. The
RMS current rating should be higher than the maximum load
current.
MOSFET Selection
Bottom FET Selection
During normal operations, the bottom FET is turned on and
off at almost zero voltage. So only conduction loss is present
in the bottom FET. The bottom FET power loss peaks at the
maximum input voltage and load current. The most important
parameter when choosing the bottom FET is the on resistance. The less the on resistance, the less the power loss.
The equation for the maximum allowed on resistance at
room temperature for a given FET package, is:
(15)
where Tj_max is the maximum allowed junction temperature
in the FET, Ta_max is the maximum ambient temperature,
Rθja is the junction-to-ambient thermal resistance of the FET,
and TC is the temperature coefficient of the on resistance
which is typically 4000ppm/˚C.
Example: Tj_max = 100˚C, Ta_max = 60˚, Rθja = 60˚C/W,
Vin_min = 14V, Vn = 1.6V, and Iload_max = 10A.
(14)
where Tj_max is the maximum allowed junction temperature
in the FET, Ta_max is the maximum ambient temperature,
Rθja is the junction-to-ambient thermal resistance of the FET,
and TC is the temperature coefficient of the on resistance
which is typically 4000ppm/˚C.
If the calculated on resistance is smaller than the lowest
value available, multiple FETs can be used in parallel. If the
design criterion is to use the highest-Rds FET, then the
Rds_max of each FET can be increased due to reduced
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Since the switching loss usually increases with bigger FETs,
choosing a top FET with a much smaller on resistance
sometimes may not yield noticeable lower temperature rise
and better efficiency.
It is recommended that the peak value of the Vds of the top
FET does not exceed 200 mV when the top FET conducts,
otherwise the COMPx pin voltage may reach its high clamp
value (2V) and cause loss of regulation.
28
What is actually monitored and limited is the peak drainsource voltage of the top FET when it is conducting. The
equation for current limit resistor is as follows:
(17)
where I1 is maximum load current of Channel 1, I2 is the
maximum load current of Channel 2, D1 is the duty cycle of
Channel 1, and D2 is the duty cycle of Channel 2.
Example: Iload_max_1 = 6.8A, Iload_max_2 = 2A, D1 = 0.09,
and D2 = 0.1.
(16)
where Iload_lim is the desired load current limit level and
Iilim_min is the minimum sink current at the ILIM1 pin. This
calculated Rilim value guarantees that the minimum current
limit will not be less than Iload_lim.
Example: Iload_lim = 16A, Irip_max = 4.3A, Rds_max = 18mΩ,
Tj_max = 100˚C, Iilim_min = 8µA.
Choose input capacitors that can handle 1.97A ripple RMS
current at highest ambient temperature. The input capacitors
should also meet the voltage rating requirement. In this
case, a SANYO OSCON capacitor 25SP33M, or a Taiyo
Yuden ceramic capacitor TMK325BJ475, will meet both requirements.
Comparison: If the two channels are operating in phase, the
ripple RMS value would be 2.52A. The equation for calculating ripple RMS current takes the same form as the one
above but the meanings of the variables change. I1 is the
sum of the maximum load currents, D1 is the smaller duty
cycle of the two, D2 is the difference between the two duty
cycles, and I2 is the maximum load current of the channel
that has larger duty cycle.
It is recommended that a 1% tolerant resistor be used and its
resistance should not be lower than the calculated value.
Input Capacitor Selection
In a typical buck regulator the power loss in the input capacitors is much larger than that in the output capacitors. That is
because the current flowing through the input capacitors is of
square-wave shape and the peak-to-peak magnitude is
equal to load current. The result is a large ripple RMS current
in the input capacitors.
The fact that the two switching channels of the LM2633 are
180˚ out of phase helps reduce the RMS value of the ripple
current seen by the input capacitors. That will help extend
input capacitor life span and result in a more efficient system. In a mobile CPU application, both the CPU core and
GTL bus voltages are rather low compared to the input
voltage. The corresponding duty cycles are therefore less
than 50%, which means there will be no over-lapping be-
Figure 6 shows how the reduction of input ripple RMS current brought by the 2-phase operation varies with load current ratio and duty cycles. From the plots, it can be seen that
the benefit of the 2-phase operation tends to maximize when
the two load currents tend to be equal. Another conclusion is
that the ratio increases rapidly when one channel’s duty
cycle is catching up with the other channel’s and then becomes almost flat when the former exceeds the latter. So the
absolute optimal operating point in terms of input ripple is at
D1 = D2 = 0.5 and Iload_max_1 = Iload_max_2, when the input
ripple current is zero for 2-phase operation.
29
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LM2633
tween the two channels’ input current pulses. The equation
for calculating the maximum total input ripple RMS current is
therefore:
Current Limit Setting
LM2633
Input Capacitor Selection
(Continued)
20000884
FIGURE 6. Input Ripple RMS Current Ratio: 2-phase vs. In-phase
Control Loop Design
Samll Signal Model
The buck regulator small signal model is shown in Figure 7.
The model is obtained by applying the current-controlled
PWM switch derived by Vorperian and by omitting portions
that are irrelevant in a buck topology.
20000838
FIGURE 7. Small Signal Model of Buck Regulators
In the model, the DC output conductance of the PWM switch
is:
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30
γ = C(R + Re) + go(CRRe + L) + CsR
δ = 1 + goR
(Continued)
(31)
For a reasonable design, the output filter has large attenuation at large complex frequencies (i.e. large s values). At s
values where 1/sC is smaller than Re, the power stage can
be reduced to the one shown in Figure 8.
(18)
Where
D’ = 1−D
(30)
(19)
(20)
200008D5
Se = Vm • f
(21)
FIGURE 8. Simplified Power Stage at High Frequencies
The transfer function can be re-written as:
(22)
Ri = Rds • ρ
(23)
Se is the correction ramp slope, Sn is the on-time slope of the
current sense waveform, Vm is the peak-peak value of the
correction ramp, f is the PWM frequency, Vin is input voltage,
Ri is the transfer resistance from inductor current to ramp
voltage, Rds is the top FET on-resistance and ρ is the gain of
the current sense amplifier.
The coefficient of the first current source is:
(32)
Where
(33)
(34)
All the Re terms are omitted in the denominator because
their values are negligible compared to other terms.
Since the denominator of the control-output transfer function
is a third-order polynomial, and its coefficients are positive
real numbers, the transfer function either has one real pole
and two complex poles that are complex conjugates or has
three real poles. Thus it can be approximately written in the
following format:
(24)
and the coefficient of the second current source is:
(25)
The output capacitance of the PWM switch is:
(26)
The DC resistance of the FET switches and of the inductor is
not included here because its value is usually much smaller
than the load resistance.
(35)
Where
Control-Output Transfer Function
The control (COMPx pin) voltage in a peak-current mode
scheme such as that of the LM2633 is the current command.
At any instant that voltage determines the level of the inductor current (from an average-model point of view). The
control-output transfer function is a description of the
small-signal behavior of the power stage and is obtained by
letting the small signal component of the input voltage be
zero. The expression for the control-output transfer function
is:
(36)
and
(37)
where
(27)
Where
α = LCsC(R + Re)
β = goLC(R + Re) + Cs(CRRe + L)
(28)
(38)
(29)
and
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LM2633
Control Loop Design
LM2633
Control Loop Design
(Continued)
(39)
The value of fp can be determined by comparing the denominators of Equation (35) and Equation (27). The result is:
(40)
From the above expressions, it can be seen that the
control-output transfer function has three poles and one
zero. Of the three poles, one is a real pole (fp) that is located
at low frequency, the other two are either complex conjugates that are located at half the switching frequency (fn), or
are separated real poles, depending on the Q value. When Q
value is less than 0.5, the two high frequency poles will
become two real poles.
From Equation (34) it can be told that Q will become negative when mc < 1/(2D’). A negative Q value means an
unstable system because the control-output transfer function
will have a right-half-plane pole.
Example: L = 1.5 µH, C = 2 mF, Re = 9 mΩ, Rds = 10 mΩ,
Vin = 10V, Vout = 1.6V, R = 0.4Ω. For LM2633, f = 250 kHz,
Se = 0.25V, ρ = 5.
20000863
FIGURE 9. Example Control-Output Transfer Function
Bode Plot
It should be noted that load resistance only changes the low
frequency gain. This causes the location of the low frequency pole to change with load.
Frequency Compensation Design
The general purpose to compensate the loop is to meet
static and dynamic performance requirements while maintaining stability. Loop gain is what is usually checked for
small-signal performance. Loop gain is equal to the product
of control-output transfer function (or so-called ’plant’) and
the output-control transfer function (i.e. the compensation
network transfer function). Different compensation schemes
result in different trade-offs among static accuracy, transient
response speed and degree of stability, etc.
Generally speaking it is a good idea to have a loop gain
slope that is −20dB/decade from a very low frequency to well
beyond cross-over frequency. The cross-over frequency
should not exceed one-fifth of the switching frequency, i.e.
50kHz in the case of LM2633. The higher the bandwidth, the
potentially faster the load transient response speed. However, if the duty cycle saturates during the load transient,
then further increasing the small signal bandwidth will not
help. In the context of CPU core or GTL bus power supply, a
small-signal bandwidth of 20kHz to 30kHz should be sufficient if output capacitors are not just MLCs.
Since the control-output transfer function usually has very
limited low frequency gain (see Figure 9), it is a good idea to
place a pole in the compensation at zero frequency, so that
the low frequency gain especially the DC gain will be very
large. A large DC gain means high DC regulation accuracy
(i.e. DC voltage changes little with load or line variations).
The rest of the compensation scheme depends highly on the
plant shape. If a typical shape such as shown in Figure 9 is
assumed, then the following can be done to create a
−20dB/decade roll-off of the loop gain.
Place the first zero at fp, the second pole at fz, and the
second zero at fn, then the resulting loop gain plot will be of
−20dB/dec slope from zero frequency up to fn (half the
switching frequency).
Rj = 10mΩ x 5 = 50mΩ
Se = 0.25V x 250kHz = 62.5mV/µs
fn = 250kHz ÷ 2 = 125kHz
Figure 10 shows the gain plot of such a two-pole two-zero
(more accurately, a lag-lag) compensation network, where
fz1, fz2 and fp2 are the first zero, second zero and second
pole frequencies. The first pole fp1 is located at zero frequency.
The resulting gain plot is shown in Figure 9 as the asymptotic
plot. The plots of the actual gain and phase as computed by
Equation (27) are also shown.
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32
LM2633
Control Loop Design
(Continued)
TABLE 5. R1 and R2 Values vs. VID
VID4:0
VDAC (V)
R1
R2
r=
R2/(R1+R2)
00000
2.00
25k
17.1k
0.41
00001
1.95
25k
18.4k
0.42
00010
1.90
25k
17.4k
0.41
00011
1.85
25k
21.4k
0.46
00100
1.80
25k
19.3k
0.43
00101
1.75
25k
22.0k
0.47
00110
1.70
25k
22.1k
0.47
20000864
00111
1.65
25k
30.0k
0.55
01000
1.60
25k
24.5k
0.49
01001
1.55
25k
27.3k
0.52
01010
1.50
25k
26.0k
0.51
01011
1.45
25k
34.6k
0.58
01100
1.40
25k
29.3k
0.54
01101
1.35
25k
36.0k
0.59
01110
1.30
25k
36.4k
0.59
01111
NO CPU
25k
64.3k
0.72
10000
1.275
12.5k
23.2k
0.65
10001
1.250
12.5k
25.7k
0.67
10010
1.225
12.5k
24.5k
0.66
10011
1.200
12.5k
32.1k
0.72
10100
1.175
12.5k
27.5k
0.69
10101
1.150
12.5k
33.3k
0.73
10110
1.125
12.5k
33.6k
0.73
10111
1.100
12.5k
56.2k
0.82
11000
1. 075
12.5k
39.6k
0.76
11001
1.050
12.5k
47.4k
0.79
11010
1.025
12.5k
43.4k
0.78
11011
1.000
12.5k
75.0k
0.86
11100
0.975
12.5k
53.7k
0.81
11101
0.95
12.5k
81.8k
0.87
11110
0.925
12.5k
83.7k
0.87
11111
0.900
12.5k
∞
1
FIGURE 10. 2-Pole 2-Zero (lag-lag) Network Asymptotic
Gain Plot
To achieve the gain shape in Figure 10, Zc in Figure 7 should
take the form of two RC branches in parallel, as shown in
Figure 11. In the scheme, C1 and R3 form the first zero fz1,
C2 and R3 form the second pole fp2, and C2 and R4 form the
second zero fz2.
20000865
FIGURE 11. Compensation Network
The gain of the compensation network can be calculated as
the following. If the ESR zero frequency fz is higher than the
low frequency pole fp, then there should be a −20dB/decade
section from fp (310 Hz) to fz (8.8 kHz) in the plant gain plot,
such as shown in Figure 9. Find the frequency where this
section (or the extension of this section) crosses 0dB by
using the following equation:
fc_o = M • fp
(41)
If the desired loop transfer function cross-over frequency is
fc_c, then the gain of the compensation network at fp should
be:
The signal path from output voltage to control voltage is the
feedback path. It typically contains a voltage divider, an error
amplifier and a compensation network. Those are shown In
Figure 7 as R1, R2, the gm amplifier, and Zc. For Channel 1
of the LM2633, since an R-2R ladder network is used, R1
and R2 values change with the VID setting. For information
regarding their values and ratios, refer to Table 5. For Channel 2, R1 and R2 are simply the external voltage divider
resistors.
(42)
To determine the component values in Figure 11, the following equations can be used:
(43)
where B is the desired gain at fz1, and gm is the transconductance of the error amplifier.
(44)
33
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LM2633
Control Loop Design
(Continued)
(45)
(46)
Back to the previous example. Let B = K, fz1 = fp, fp2 = fz, fz2
= fn, then:
fc_o = 5.1 x 310Hz = 1581Hz
20000877
FIGURE 13. Example Loop Transfer Function
If a shorter recovery time is desired during a load transient,
fz1 can be increased so that the gain of the loop transfer
function becomes higher. However, try not to let fz1 be higher
than the desired cross-over frequency, otherwise phase margin can be too low. Figure 14 shows a situation where fz1 is
placed at a higher frequency than the fp, which results in a
−40 dB/dec section before the cross-over frequency. Notice
the phase margin is lower.
The corresponding Bode plots of the compensation network
and the loop transfer function are shown in Figure 12 and
Figure 13 respectively.
200008D6
FIGURE 14. Higher Low Frequency Gain
Sometimes the slow transient response is caused by the
current source and sink capability of the error amplifier.
Reducing the value of the compensation capacitor helps, but
make sure the small-signal loop is stable.
The power stage component selection can be significantly
different from the example values. Figure 15 shows how the
two high frequency poles of a current-mode-control buck
regulator change with the Q value.
20000876
FIGURE 12. Example Compensation Transfer Function
It can be seen from Figure 13 that the crossover frequency is
20kHz, and the phase margin is about 84 degrees.
One thing that should be pointed out is this Bode plot is only
for the 0.4Ω load. That is, when load current is 4A. If load
current is lower than 4A, the portion of the gain plot from the
corresponding fp to 310Hz will be −40dB/dec. If load current
is higher than 4A, then the portion of the gain plot from
310Hz to fp will be flat. However, this usually does not have
much effect on the cross-over frequency and phase margin
because it happens at low frequencies.
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34
LM2633
Control Loop Design
(Continued)
(48)
where H(s) is the compensation transfer function defined by:
(49)
It can be seen from Equation (47) that if mc is equal to
1/(2D’)+0.5, then the open-loop audio susceptibility is zero.
Unfortunately, the transfer function is rather sensitive to the
value of mc around the critical value and thus this phenomenon is of little value.
20000878
FIGURE 15. How Control-Output Transfer Function
Changes with Q Values
When Q is higher than 0.5, there will be a double-pole at half
the switching frequency fn. When Q is lower than 0.5, the
double-pole is damped and becomes two separate poles.
The lower the Q value is, the farther apart the two poles are.
When Q is too low (such as Q = 0.05 or lower), one of the
two high frequency poles may move well into the low frequency region. When Q is too high (such as Q = 5 or higher),
there will be significant peaking at half the switching frequency and the phase will rapidly go to −180˚ near it. This
typically results in a lower cross-over frequency so that the
peaking in the loop gain is well below the 0dB line.
Q is a function of duty cycle and the deepness of the ramp
compensation (mc). See Equation (34). The larger the duty
cycle, the higher the Q value. The deeper the ramp compensation, the lower the Q value. When the inductor current
ramp is too much smaller than the compensation ramp, one
of the two high frequency poles will move far into the low
frequency region and form a double-pole with the existing
low frequency pole fp. That makes it a voltage-mode control.
The ramp compensation becomes deeper when inductance
is increased, or input voltage is decreased, or sense resistance is decreased.
In the case of Channel 1 of LM2633, if L = 1 to 3µH, Vin = 5
to 24V, Vo = 0.925 to 2V, Rds = 5 to 20mΩ, the Q value will
be between 0.65 and 0.2.
20000882
FIGURE 16. Example Audio Susceptibility Gain
The open-loop and closed-loop audio susceptibility of the
previous example is shown in Figure 16. It can be told, both
from the model and from Equation (47), that open-loop gain
of audio susceptibility is just a level shift of the loop gain.
Closed-loop audio susceptibility starts to depart from its
open-loop counterpart when frequency drops below the
cross-over frequency.
Adjusting the Output Voltages of the Switching
Channels
Channel 1 output voltage is normally adjusted through the
VID pins. Channel 2 output voltage is adjusted through an
external voltage divider, as shown in Figure 17.
Audio Susceptibility
Audio susceptibility is the transfer function from input to
output. In a typical power supply design, it is desirable to
have as much attenuation in that transfer function as possible so that noise appearing at the input has little effect on
the output. The open-loop audio susceptibility given by the
model in Figure 7 is:
200008B7
FIGURE 17. Setting the Ch2 Output Voltage
The equation to find the value of R2 when R1 has been
selected is:
(47)
The closed-loop audio susceptibility is simply:
(50)
where Vfb2 is equal to the internal reference voltage connected to the non-inverting input of the Channel 2 error
35
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LM2633
Control Loop Design
Since an op-amp is an active device, pay close attention to
its start up and shut down behavior. Make sure that it does
not create a problem during those times.
(Continued)
amplifier, and Ifb2 is the current drawn by the FB2 pin. The
Vfb2 and Ifb2 have a typical value of 1.24V and 18 nA
respectively.
Designing a Power Supply without a Load Transient
Specification
Example: Vout2 = 1.5V, R1 = 10 kΩ.
Many times the load transient response of a buck regulator is
not a critical issue. In that case, the selection of the power
stage components can start from the inductor ripple current.
Choosing the peak-to-peak ripple current to be 30% of the
maximum load current is often a good starting point. Then
the inductance value can be determined by ripple, switching
frequency and input and output voltages. By rearranging
Equation (13), the inductance value can be calculated as
follows:
(51)
To calculate the total system tolerance, use the following
equation:
(52)
where φ is the tolerance of the Channel 2 reference voltage,
and σ is the tolerance of the resistors.
Example: Vout2 = 3.3V, feedback resistors have a ± 1%
tolerance.
(54)
Example: Vin_max = 21V, Vn = 1.6V, Iload_max = 10A.
The output capacitors can be chosen based on the output
voltage ripple requirement. If there is no specific requirement, then a ± 1% ripple level may be a good starting point.
The equation for determining the impedance of the output
capacitors is:
(53)
That means the 3.3V output voltage will have a ± 2.96%
tolerance over the (LM2633 die) temperature range of 0˚C to
125˚C.
Channel 2 output voltage should not go above 6V in
pulse-skip mode. That is because the SENSE2 pin cannot
take a voltage higher than 6V. However, if force-PWM operation is the chosen operating mode, then the SENSE2 pin
can be grounded and there will be no limitation to Channel 2
output voltage.
If the desired Channel 1 voltage is higher than 2V, an
op-amp and a voltage divider can be used to expand the
voltage range, as shown in Figure 18.
(55)
If the ESR zero frequency of the capacitor is lower than the
switching frequency, such as the case of aluminum, tantalum
and OSCON capacitors, then the output capacitors are chosen by the ESR value. Otherwise, such as in the case of
ceramic capacitors, the output capacitors are chosen by the
capacitance. The equation is:
(56)
Basically make sure that the product of the impedance of the
capacitors and the ripple current does not exceed the ripple
voltage requirement.
Example: Vn = 1.6V, Irip = 3A.
200008B6
(57)
If ceramic capacitors are preferred, then the minimum capacitance is:
FIGURE 18. How to Make VOUT1 Higher Than 2V
It is recommended that the VIDx pins be all tied to ground so
that the DAC is set at 2.00V. That will reduce the total
tolerance. The equations used to calculate Channel 2’s feedback resistors and total tolerance still hold, except that the
reference voltage Vfb1 is 2.00V instead of 1.24V. Channel 1
can operate only in force-PWM mode when it is configured
as Figure 18.
(58)
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36
In pulse-skip mode, the apparent switching frequency is
lower than the frequency the regulator would run at if it were
in force-PWM mode. The actual frequency depends on the
load, the lighter the load the lower the frequency.
(Continued)
If aluminum, tantalum or OSCON capacitors are going to be
used, make sure the combined ESR is not greater than
10.6 mΩ.
The load at which pulse-skipping starts to happen can be
determined from the following formula:
Depending on the application, a different priority may be
assigned to the selection of components. For example, to
achieve a 10.6 mΩ combined ESR, it would require 6
low-ESR tantalum capacitors, which can be quite expensive.
If the inductor size is allowed to expand, then a higher
inductance value can be used so that ripple current is reduced and impedance of the capacitor at the switching frequency can be higher. It is often necessary to go through
several iterations before a reasonable combination of the
inductor and capacitors is achieved.
Notice the above procedure is given without any consideration of a load transient, whether expected or unexpected.
The power supply designer may be tempted to use a 100 µF
ceramic capacitor as the only output capacitor in the above
example. That may be fine in a design that has a very static
load. However, should there be a large fault load current
(which is not enough to trigger UVP) and if later that condition is suddenly lifted, the output may see a severe over
voltage. Although the LM2633 will shut down immediately
upon seeing the over-voltage event, the load could have
been damaged already. Another concern with pure ceramic
output capacitors is soft start. It may be necessary to increase the soft start time so that there will be minimum
overshoot at the end of soft start. So when a large inductance and a small capacitance are chosen, care should be
given to the above situations.
If the load current goes from one level to another during
normal operations, a design with less capacitance tends to
have more output voltage excursion and recover more
slowly than one with more capacitance. From the
time-domain viewpoint, that is because less capacitance is
less effective an energy buffer when the load current is
temporarily different from the inductor current. From the
frequency-domain viewpoint, that is because the output impedance of the regulator is higher.
For power supplies that don’t have a stringent load transient
requirement, polymer aluminum capacitors can be used as
well as low-ESR tantalum capacitors. These polymer aluminum capacitors are surface mount, long-life, ignition free and
typically have very low ESR values. For example, Cornell
Dubilier’s ESRE and ESRD polymer aluminum chip capacitors have ESR value as low as 6 mΩ and capacitance up to
270 µF (http://www.cornell-dubilier.com).
Panasonic also offers specialty polymer aluminum capacitors. Panasonic’s UE series offers capacitance up to 270 µF,
and voltage rating up to 8 VDC.
For the Typical Application circuit, if there is no stringent load
transient requirement on Channel 1, C2 can be replaced by
a single polymer aluminum capacitor, such as
ESRE271M02R from Cornell Dubilier. The frequency compensation should be: C14 = 4.7 nF, R9 = 7.5 kΩ. C15 and
R10 are not necessary. Notice that the voltage rating of that
capacitor is only 2 VDC.
(59)
Example: Irip = 3A.
Since the critical load current completely depends on the
inductor ripple current, the inductance value cannot be arbitrary if accurate control of the value of the critical load is
desired.
When the FPWM pin is pulled high, the regulator enters the
discontinuous conduction mode (DCM) when the load is light
enough so that the inductor current goes to zero before the
end of each switching cycle. The critical load current value
for the regulator to enter DCM is:
(60)
Notice in DCM mode the FETs still switch every clock cycle
but the duty cycle shrinks as load current decreases. When
the load current goes below Iload_skip, the regulator enters
the pulse-skip mode. So the DCM region is a very narrow
one.
So, when the peak-peak ripple current is 3A, the DCM
happens only when load current falls in the 1.1A to 1.5A
range. Above that range, the regulator is in continuous conduction mode (CCM), and below that range, the regulator
runs in pulse-skip mode.
Designing a Linear Regulator with Channel 3
Channel 3 of the LM2633 can be used to drive an external
NPN transistor and provide linear regulation. See Figure 19.
200008A7
Designing Around the Pulse-Skip Mode
If the FPWM pin is pulled to logic high, the LM2633 operates
in pulse-skip mode. In this mode, when the load is light
enough, the LM2633 starts to skip pulses. See Pulse-Skip
Mode in Operation Descriptions.
FIGURE 19. Channel 3 Controlling an LDO
The output voltage is adjusted through the voltage divider,
and the equation is:
37
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LM2633
Control Loop Design
LM2633
Control Loop Design
The error amplifier of Channel 3 has a DC gain of 83 dB, and
a unity-gain bandwidth of 200 kHz. See the plots in Figure
21.
(Continued)
(61)
where Vfb3 is equal to the reference voltage connected to the
non-inverting input of the error amplifier and has a typical
value of 1.24V, and Ifb3 is the bias current drawn by the FB3
pin and has a typical value of 70 nA.
Example: The intended output voltage is 2.5V. Find the
appropriate R2 value if R1 is chosen to be 10.0 kΩ.
(62)
The G3 voltage cannot exceed 4V, and the G3 current
sourcing capability decreases with increasing G3 pin voltage. See the typical curves. It is suggested that the maximum output voltage does not exceed 3V when an NPN pass
transistor is used. If an N-channel FET is to be used, make
sure the FET can be fully turned on before G3 goes to 4V.
There are two factors to consider when selecting Q1. First is
the DC current gain β, second is power dissipation.
For a certain load current, the lower the β value, the more
base current is necessary to maintain regulation. Since the
base current comes from VIN pin through internal linear
regulation, a large base current significantly increases power
consumption in the LM2633 and hurts light-load efficiency,
particularly when VIN is relatively high. Therefore a transistor
with a large β value is preferred.
The maximum power consumption in Q1 is:
20000895
FIGURE 21. VFB3-to-VG3 Transfer Function (theoretical)
It is not easy to model the loop frequency response of an
NPN linear regulator. The best way is still to measure the
loop gain under different load conditions on bench. As a
reference point, for an LDO set at 2.5V that uses an
MMBT2222 as the pass transistor, a 1 µF ceramic as the
output capacitor and at a 170 mA load, the bandwidth is
about 107 kHz, with a phase margin of 71˚ and a gain margin
of about 10 dB.
The higher the bandwidth, the less the output capacitance is
needed to handle the load transient. However, for most
applications, stability is the only concern.
PCB Layout Guidelines
Ploss = Iload_max • (Vin2_max − Vout3_min)
(63)
Example: The input voltage of the linear regulator is 3.3V
± 5%, the maximum load current is 150 mA, and the output
voltage is 2.5V. Since Channel 3 of the LM2633 has a ± 2%
tolerance over temperature, and the voltage divider contributes another ± 1%, so the total output voltage tolerance is
± 3%. See Equation (52) for the calculation of total tolerance
when a voltage divider is used.
Ploss = 150 mA x (3.3V x 1.05 − 2.5V x 0.97) = 156 mW
It is extremely important to follow the guidelines below to
ensure a clean and stable operation.
1. Use a four-layer PCB.
2. Keep the FETs as close to the IC as possible.
3. Keep the power components on the right side (pins 25
through 48) of the IC and low-power components on the
left side.
4. Analog ground and power ground should be separate
planes and should be connected at a single point, preferably at the PGNDx and GND pins and directly underneath the IC.
5. The VDDx pin decoupling capacitor should be connected to the power ground plane.
6. Input ceramic capacitors should be placed very close to
the FETs and their connections to the drain of the top
FET and to the source of the bottom FET should be as
short as possible and should not go through power plane
or ground plane.
7. HDRVx, SWx traces should be as close to each other as
possible to minimize noise emission. If these two traces
are longer than 2 centimeters, they should be fairly wide,
such as 50mil.
8. Keep KSx trace as short as possible. Otherwise, use a
trace of 50mil or wider.
9. ILIMx trace should be kept away from noisy nodes such
as the switch node.
10. It is preferable to have a shorter and wider FBx trace
than a longer and narrower one.
If the ambient temperature is 65˚C or less, a SOT-23 package should be able to handle this much power.
Since Channel 3 affects UVP, if it is not to be used, proper
termination of the pins should be made. One good way is to
tie FB3 to VLIN5, and tie OUT3 and G3 together and leave
them floating. See Figure 20.
200008A8
FIGURE 20. When Ch.3 is Not in Use
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38
13. Channel 3 should use the analog ground, not the power
ground, to avoid potential noise coupling from the
switching channels.
(Continued)
11. VLIN5 pin decoupling capacitor should be connected to
the local analog ground.
An example of the power stage layout is shown in Figure 22.
12. Compensation components should be placed close to
the IC, within 1 to 2 centimeters.
20000883
FIGURE 22. PCB Layout Example
39
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LM2633
PCB Layout Guidelines
LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs
Physical Dimensions
inches (millimeters)
unless otherwise noted
48-Lead TSSOP Package
Order Number LM2633MTD
NS Package Number MTD48
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