74AHC257-Q100; 74AHCT257-Q100 Quad 2-input multiplexer; 3-state Rev. 1 — 22 July 2013 Product data sheet 1. General description The 74AHC257-Q100; 74AHCT257-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC257-Q100; 74AHCT257-Q100 has four identical 2-input multiplexers with 3-state outputs. They select 4 bits of data from two sources and a common data select input (S) controls them. The data inputs from source 0 (1I0 to 4I0), are selected when input S is LOW. The data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74AHC257-Q100; 74AHCT257-Q100 is the logic implementation of a 4-pole 2-position switch. The logic levels applied to input S determine the position of the switch. The outputs are forced to a high-impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE (1I1 S + 1I0 S) 2Y = OE (2I1 S + 2I0 S) 3Y = OE (3I1 S + 3I0 S) 4Y = OE (4I1 S + 4I0 S) This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Balanced propagation delays All inputs have Schmitt-trigger actions Non-inverting data path Inputs accept voltages higher than VCC Input levels: For 74AHC257-Q100: CMOS level For 74AHCT257-Q100: TTL level 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC257D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74AHC257PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74AHC257-Q100 74AHCT257-Q100 74AHCT257D-Q100 74AHCT257PW-Q100 40 C to +125 C SOT109-1 4. Functional diagram 2 3 5 1I0 1I1 1 S 15 OE Fig 1. 6 2I0 2I1 11 10 3I0 3I1 14 13 4I0 4I1 SELECTOR 3-STATE MULTIPLEXER OUTPUTS 1Y 2Y 3Y 4Y 4 7 9 12 mgr280 Functional diagram 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 2 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 1 G1 15 EN 1 2 1I0 3 1I1 5 2I0 6 2I1 11 3I0 10 3I1 14 4I0 13 4I1 15 OE S 2 4 1Y MUX 4 1 5 7 2Y 1 3 7 6 9 3Y 11 9 10 12 4Y 14 12 13 001aad467 mga835 Fig 2. Logic symbol Fig 3. IEC logic symbol 1I0 1Y 1I1 2I0 2Y 2I1 3I0 3Y 3I1 4I0 4Y 4I1 OE S Fig 4. 001aad468 Logic diagram 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 3 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 5. Pinning information 5.1 Pinning $+&4 $+&74 6 9&& , 2( , , < , , < , , < , *1' < DDD Fig 5. Pin configuration SO16 and TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description S 1 common data select input 1I0 2 data input from source 0 1I1 3 data input from source 1 1Y 4 multiplexer output 2I0 5 data input from source 0 2I1 6 data input from source 1 2Y 7 multiplexer output GND 8 ground (0 V) 3Y 9 multiplexer output 3I1 10 data input from source 1 3I0 11 data input from source 0 4Y 12 multiplexer output 4I1 13 data input from source 1 4I0 14 data input from source 0 OE 15 output enable input (active LOW) VCC 16 supply voltage 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 4 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 6. Functional description Table 3. Function table[1] Control Input Output OE S nI0 nI1 nY H X X X Z L H X L L X H H L X L H X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions Min Max Unit 0.5 +7.0 V 0.5 +7.0 V 20 - mA 20 +20 mA 25 +25 mA input clamping current VI < 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current VO = 0.5 V to (VCC + 0.5 V) ICC supply current - +75 mA IGND ground current 75 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW IIK Tamb = 40 C to +125 C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K. For TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K. 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 5 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 2.0 5.0 5.5 V 74AHC257-Q100 VCC supply voltage VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C t/V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT257-Q100 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C t/V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = 8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V 74AHC257-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 6 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 A IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V - - 0.25 - 2.5 - 10.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 A CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF VI = VCC or GND 74AHCT257-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA 4.5 - 4.4 - 4.4 - V - - 3.80 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 A II input leakage current IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - 0.25 - 2.5 - 10.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 A ICC additional per input pin; supply current VI = VCC 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF 74AHC_AHCT257_Q100 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 VI = VCC or GND All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 7 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 8. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 4.2 9.3 1.0 11.0 1.0 12.0 ns CL = 50 pF - 6.0 12.8 1.0 14.5 1.0 16.0 ns - 2.9 5.9 1.0 7.0 1.0 7.5 ns - 4.2 7.9 1.0 9.0 1.0 11.5 ns CL = 15 pF - 5.2 11.0 1.0 13.0 1.0 14.0 ns CL = 50 pF - 7.4 14.5 1.0 16.5 1.0 18.5 ns - 3.5 6.8 1.0 8.0 1.0 8.5 ns - 5.0 8.8 1.0 10.0 1.0 12.5 ns CL = 15 pF - 4.5 10.5 1.0 12.5 1.0 13.5 ns CL = 50 pF - 6.4 14.0 1.0 16.0 1.0 17.5 ns 74AHC257-Q100 tpd propagation delay nI0, nI1 to nY; see Figure 6 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF [2] S to nY; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time [3] OE to nY; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tdis CL = 15 pF - 3.2 6.8 1.0 8.0 1.0 8.5 ns CL = 50 pF - 4.5 8.8 1.0 10.0 1.0 12.5 ns CL = 15 pF - 5.1 9.5 1.0 11.0 1.0 11.5 ns CL = 50 pF - 7.2 12.0 1.0 13.5 1.0 14.5 ns - 3.4 6.5 1.0 7.0 1.0 8.5 ns - 4.9 7.9 1.0 9.0 1.0 9.5 ns - 45 - - - - - pF - 15 - - - - - pF [4] disable time OE to nY; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power fi = 1 MHz; VI = GND to VCC dissipation 4 outputs switching via capacitance input S 1 output switching via input I 74AHC_AHCT257_Q100 Product data sheet [5] All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 8 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 8. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max - 3.7 6.5 1.0 8.0 1.0 9.0 ns - 4.9 8.5 1.0 10.0 1.0 11.0 ns CL = 15 pF - 5.1 9.0 1.0 10.5 1.0 11.5 ns CL = 50 pF - 6.4 10.5 1.0 12.5 1.0 13.5 ns - 3.9 8.0 1.0 9.0 1.0 10.0 ns - 5.1 10.0 1.0 11.0 1.0 12.0 ns - 4.5 7.5 1.0 8.0 1.0 8.5 ns - 6.5 9.5 1.0 10.5 1.0 11.5 ns - 51 - - - - - pF - 15 - - - - - pF 74AHCT257-Q100; VCC = 4.5 V to 5.5 V tpd propagation delay nI0, nI1 to nY; see Figure 6 [2] CL = 15 pF CL = 50 pF [2] S to nY; see Figure 6 ten enable time [3] OE to nY; see Figure 7 CL = 15 pF CL = 50 pF tdis [4] disable time OE to nY; see Figure 7 CL = 15 pF CL = 50 pF CPD power fi = 1 MHz; VI = GND to VCC dissipation 4 outputs switching via capacitance input S 1 output switching via input I [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZL and tPZH. [4] tdis is the same as tPLZ and tPHZ. [5] [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 9 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 11. Waveforms VI nI0, nI1, S VM input GND t PHL t PLH VOH VM nY output mna486 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Data inputs and common data select input to output propagation delays VI OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna813 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Enable and disable times Measurement points Type Input Output VM VM VX VY 74AHC257-Q100 0.5 VCC 0.5 VCC VOL + 0.3 V VOH 0.3 V 74AHCT257-Q100 1.5 V 0.5 VCC VOL + 0.3 V VOH 0.3 V 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 10 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = test selection switch. Fig 8. Table 9. Test circuitry for measuring switching times Test data Type 74AHC257-Q100 Input Product data sheet S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ VCC 3.0 ns 15 pF, 50 pF 1 k open GND VCC 3.0 ns 15 pF, 50 pF 1 k open GND VCC 74AHCT257-Q100 3.0 V 74AHC_AHCT257_Q100 Load All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 11 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 12 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 10. Package outline SOT403-1 (TSSOP16) 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 13 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT257_Q100 v.1 20130722 Product data sheet - - 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 14 of 17 74AHC257-Q100; 74AHCT257-Q100 NXP Semiconductors Quad 2-input multiplexer; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 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Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 15 of 17 NXP Semiconductors 74AHC257-Q100; 74AHCT257-Q100 Quad 2-input multiplexer; 3-state No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AHC_AHCT257_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2013 © NXP B.V. 2013. All rights reserved. 16 of 17 NXP Semiconductors 74AHC257-Q100; 74AHCT257-Q100 Quad 2-input multiplexer; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 July 2013 Document identifier: 74AHC_AHCT257_Q100