X9525
®
Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Data Sheet
PRELIMINARY
March 10, 2005
Dual DCP, EEPROM Memory
FN8210.0
DESCRIPTION
The X9525 combines two Digitally Controlled Potentiometers (DCP’s), and integrated EEPROM with Block
Lock™ protection. All functions of the X9525 are
accessed by an industry standard 2-Wire serial interface.
FEATURES
• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10kΩ
—256 Tap - 50kΩ
—Non-Volatile
—Write Protect Function
• 2kbit EEPROM Memory with Write Protect & Block
LockTM
• Device ID Addressability
• 2-Wire industry standard Serial Interface
—Complies to the Gigabit Interface Converter
(GBIC) specification
—Adressable
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• Packages
—CSP (Chip Scale Package)
—20 Pin TSSOP
The DCP’s of the X9525 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The 2kbit integrated EEPROM may be
used to store module definition data.
The features of the X9525 are ideally suited to simplifying
the design of fiber optic modules which comply to the Gigabit Interface Converter (GBIC) specification. The integration of these functions into one package significantly
reduces board area, cost and increases reliability of laser
diode modules.
BLOCK DIAGRAM
WIPER
COUNTER
REGISTER
WP
SDA
SCL
Ao
COMMAND
DECODE &
CONTROL
LOGIC
RW1
RL1
8
DATA
REGISTER
RH1
PROTECT
LOGIC
8 - BIT
NONVOLATILE
MEMORY
CONSTAT
REGISTER
WIPER
COUNTER
REGISTER
4
RH2
RW2
RL2
2kbit
EEPROM
ARRAY
8 - BIT
NONVOLATILE
MEMORY
THRESHOLD
RESET LOGIC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2001 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9525
PIN CONFIGURATION
NOT TO SCALE
20 Pin TSSOP
CSP
1
RH2
RW2
RL2
1
2
3
4
5
6
NC
NC
A0
WP
SCL
7
8
SDA
VSS
9
10
20
19
18
17
16
15
14
13
12
11
2
3
4
VCC
NC
NC
NC
A
B
NC
NC
NC
RH1
C
RW1
RL1
E
NC
VCC
RW2
RL2
NC
NC
RH2
NC
NC
NC
NC
WP
RH1
NC
A0
SCL
VSS
RW1
RL1
SDA
D
Top View – Bumps Down
PIN ASSIGNMENT
Pin
CSP
Name
Function
1
B3
RH2
Connection to end of resistor array for (the 256 Tap) DCP 2.
2
A3
Rw2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3
A4
RL2
Connection to other end of resistor array for (the 256 Tap) DCP 2.
6
D3
A0
Physical Device Address input. A match in the slave address serial data stream, and the
Physical Device Address input pin must be in order to initiate communication with the X9525.
A maximum of two (2) devices may occupy the same 2-wire serial bus.
7
C4
WP
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the
Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled
Potentiometers (DCPs). The WP pin uses an internal “pull-up” resistor, thus if left floating the
write protection feature is enabled.
8
D4
SCL
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for
data input and output.
9
E4
SDA
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires an
external pull up resistor.
10
E1
Vss
Ground.
11
E3
RL1
Connection to other end of resistor for (the 100 Tap) DCP 1.
12
E2
RW1
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
13
D1
RH1
Connection to end of resistor array for (the 100 Tap) DCP 1.
20
A2
VCC
Supply Voltage.
4, 5, 14,
15, 16, 17,
18, 19
A1, B1,
B2, B4,
C1, C2,
C3, D2
NC
No Connect
2
FN8210.0
March 10, 2005
X9525
SCL
SDA
Data Stable
Figure 1.
Data Change
Data Stable
Valid Data Changes on the SDA Bus
Serial Stop Condition
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive operations. Therefore, the X9525 operates as a slave in all
applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1. On power-up of the X9525, the SDA pin is
in the input mode.
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3.
Serial Start Condition
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subsequent eight bit word.
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will ter-
SCL
SDA
Start
Figure 2.
3
Stop
Valid Start and Stop Conditions
FN8210.0
March 10, 2005
X9525
SCL
from
Master
Data Output
from
Transmitter
1
Data Output
from
Receiver
8
9
Start
Figure 3.
Acknowledge
Acknowledge Response From Receiver
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9525
can be split up into three main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—The next two bits (SA2 - SA1) are the Internal Device
Address bits. Setting these bits to 00 internally selects
the EEPROM array, while setting these bits to 11
selects the DCP structures in the X9525. The CONSTAT Register may be selected using the Internal
Device Address 10.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA2 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9525 to
be addressed, and specifies if a Read or Write operation is to be performed.
It should be noted that in order to perform a write operation to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte consists of four parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9525.
SA7
SA6 SA5
1 0 1
SA4
SA3
SA2
SA1
0 A0
DEVICE TYPE
IDENTIFIER
SA0
R/W
PHYSICAL INTERNAL READ /
DEVICE
DEVICE WRITE
ADDRESS ADDRESS
(SA2 - SA1)
Internally Addressed
Device
00
EEPROM Array
10
CONSTAT Register
11
DCP
Bit SA0
Operation
0
WRITE
1
READ
Internal Address
Figure 4.
Slave Address Format
—SA3 is the Physical Device Address bit, whose logic
level must match that of the corresponding A0 pin in
order to enable communication to the X9525.
4
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March 10, 2005
X9525
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9525
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further Read
or Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWLEDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write operation. (Refer to Figure 5.).
Issue Slave Address
Byte (Read or Write)
Issue STOP
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
2
NON
VOLATILE
MEMORY
(NVM)
1
0
RLx
RWx
Figure 6.
DCP Internal Structure
The X9525 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RHx and RLx
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(Rwx) output. Within each individual array, only one
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
NO
YES
NO
Issue STOP
complete. Continue
DECODER
DCP Functionality
Issue START
High Voltage Cycle
WIPER
COUNTER
REGISTER
(WCR)
DIGITALLY CONTROLLED POTENTIOMETERS
Byte load completed
by issuing STOP.
Enter ACK Polling
ACK
returned?
RHx
N
command sequence?
YES
Continue normal
Read or Write
command sequence
On power-up of the X9525, wiper position data is automatically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The intial values of the
DCP WCR’s (before the contents of the NVM is loaded
into the WCR) are 0 and 255 for DCP1 (100 tap) and
DCP2 (256 tap) respectively. The data in the WCR is
then decoded to select and enable one of the respective
FET switches. A “make before break” sequence is used
internally for the FET switches when the wiper is moved
from one tap position to another.
PROCEED
Figure 5.
Acknowledge Polling Sequence
5
FN8210.0
March 10, 2005
X9525
Vcc
Vcc (Max.)
VTRIP
ttrans
tpu
t
0
Maximum Wiper Recall time
Figure 7.
DCP Power-up
Hot Pluggability
Figure 7 shows a typical waveform that the X9525 might
experience in a Hot Pluggable situation. On power-up,
Vcc applied to the X9525 may exhibit some amount of
ringing, before it settles to the required value.
The device is designed such that the wiper terminal
(RWx) is recalled to the correct position (as per the last
stored in the DCP NVM), when the voltage applied to
Vcc exceeds VTRIP for a time exceeding tpu.
Therefore, if ttrans is defined as the time taken for Vcc to
settle above VTRIP (Figure 7): then the desired wiper terminal position is recalled by (a maximum) time: ttrans +
tpu. It should be noted that ttrans is determined by system hot plug conditions.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after Vcc of the
X9525 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when Vcc to the device
is powered down then back up, the “wiper position”
reverts to that last position written to the DCP using a
nonvolatile write operation.
6
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9).
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
Instruction Byte
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010A011. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP
(0 - 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit
of the Instruction Byte (I7), determines the Write Type
(WT) performed.
If WT is “1”, then a Nonvolatile Write to the DCP occurs.
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated
WCR and NVM. Therefore, the new “wiper position” setting is recalled into the WCR after Vcc of the X9525 has
been powered down then powered back up
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
FN8210.0
March 10, 2005
X9525
I7
WT
I6
I5
I4
I3
I2
0
0
0
0
0
I1
P1
WRITE TYPE
be volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9525.
I0
P0
Following the Instruction Byte, a Data Byte is issued to
the X9525 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 27).
DCP SELECT
WT†
Description
0
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
1
Select a Nonvolatile Write operation to be performed on the DCP pointed to by bits P1 and P0
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
†This bit has no effect when a Read operation is being performed.
Figure 8.
P1-P0
Instruction Byte Format
the associated NVM register remains unchanged. Therefore, when Vcc to the device is powered down then back
up, the “wiper position” reverts to that last written to the
DCP using a nonvolatile write operation.
A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.
The Slave Address Byte 1010A0110 specifies that a
Write to a DCP is to be conducted. An ACKNOWLEDGE
is returned by the X9525 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to
be written, while the WT bit determines if the Write is to
1
0
1
A0
1
0
A WT
C
K
0
0
0
0
0
1
x=1
100
Reserved
Refer to APPENDIX 1
1
0
x=2
256
FFh
1
1
Reserved
0
0
P1 P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
INSTRUCTION BYTE
SLAVE ADDRESS BYTE
Figure 9.
7
0
Max. Data Byte
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. Therefore, the Data Byte 00001111 (1510) corresponds to setting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (2810) corresponds to setting the
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1” . An example of a simple C language function which “translates” between the tap position (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2” .
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 12.)
0
# Taps
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
DCP Write Operation
S 1
T
A
R
T
DCPx
DATA BYTE
A
C
K
S
T
O
P
DCP Write Command Sequence
FN8210.0
March 10, 2005
X9525
WRITE Operation
Signals from
the Master
SDA Bus
S
t
a
r
t
Slave
Address
Instruction
Byte
1 0 1 0 A0 1 1 0
W 00000 P P
1 0
T
A
C
K
Signals from
the Slave
READ Operation
S
t
a
r
t
Slave
Address
Data Byte
S
t
o
p
1 0 1 0 A0 1 1 1
A
C
K
A
C
K
DCPx
-
x=1
“Dummy” write
x=2
MSB
LSB
“-” = DON’T CARE
Figure 10.
DCP Read Sequence
It should be noted that all writes to any DCP of the X9525
are random in nature. Therefore, the Data Byte of consecutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits (P1 = 0,
P0 = 0) or (P1 = 1, P0 = 1) are reserved sequences, and
will result in no ACKNOWLEDGE after sending an
Instruction Byte on SDA.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corresponds to having the “wiper teminal” RWX (x = 1,2) at the
“lowest” tap position, therefore, the resistance between
RWX and RLX is a minimum (essentially only the Wiper
Resistance, RW).
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
The master issues the START condition and the Slave
Address Byte 1010A0110 which specifies that a
“dummy” write” is to be conducted. This “dummy” write
operation sets which DCP is to be read (in the preceding
Read operation). An ACKNOWLEDGE is returned by the
X9525 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1 - P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9525.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9525
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
WRITE Operation
Address
Byte
Slave
Address
S
t
o
p
Data
Byte
1 0 1 0 A0 0 0 0
Internal
Device
Address
A
C
K
A
C
K
A
C
K
Figure 11. EEPROM Byte Write Sequence
8
FN8210.0
March 10, 2005
X9525
Signals from
the Master
SDA Bus
S
t
a
r
t
S
t
o
p
(2 < n < 16)
Address
Byte
Slave
Address
Data
(n)
Data
(1)
1 0 1 0 A0 0 0 0
Signals from
the Slave
A
C
K
A
C
K
A
C
K
A
C
K
Figure 12. EEPROM Page Write Operation
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
Block-Lock feature (See “BL1, BL0: Block Lock
protection bits - (Nonvolatile)” on page 12.), suppresses
the ACKNOWLEDGE bit after the Address Byte.
EEPROM Page Write
2kbit EEPROM ARRAY
Operations on the 2kbit EEPROM Array, consist of either
1, 2 or 3 byte command sequences. All operations on the
EEPROM must begin with the Device Type Identifier of
the Slave Address set to 1010A000. A Read or Write to
the EEPROM is selected by setting the LSB of the Slave
Address to the appropriate value R/W (Read = “1”,
Write = “0”).
In some cases when performing a Read or Write to
the EEPROM, an Address Byte may also need to be
specified. This Address Byte can contain the values
00h to FFh.
EEPROM Byte Write
In order to perform an EEPROM Byte Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
For a write operation, the X9525 requires the Slave
Address Byte and an Address Byte. This gives the
master access to any one of the words in the array. After
receipt of the Address Byte, the X9525 responds with an
ACKNOWLEDGE, and awaits the next eight bits of data.
After receiving the 8 bits of the Data Byte, it again
responds with an ACKNOWLEDGE. The master then
terminates the transfer by generating a STOP condition,
at which time the X9525 begins the internal write cycle to
the nonvolatile memory (See Figure 11). During this
internal write cycle, the X9525 inputs are disabled, so it
does not respond to any requests from the master. The
SDA output is at high impedance. A write to a region of
EEPROM memory which has been protected with the
9
In order to perform an EEPROM Page Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
The X9525 is capable of a page write operation. It is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
number of 8-bit bytes. After the receipt of each byte, the
X9525 responds with an ACKNOWLEDGE, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to ‘0’ on
the same page.
For example, if the master writes 12 bytes to the page
starting at location 11 (decimal), the first 5 bytes are written to locations 11 through 15, while the last 7 bytes are
written to locations 0 through 6. Afterwards, the address
counter would point to location 7. If the master supplies
more than 16 bytes of data, then new data overwrites the
previous data, one byte at a time (See Figure 13).
The master terminates the Data Byte loading by issuing
a STOP condition, which causes the X9525 to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 12 for the address, ACKNOWLEDGE, and data transfer sequence.
FN8210.0
March 10, 2005
X9525
5 bytes
5 bytes
7 bytes
address
1110
address
= 6 10
address
1510
address pointer
ends here
Addr = 710
Figure 13. Example: Writing 2 bytes to a 16-byte page starting at location 11.
Stops and EEPROM Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and receiving the subsequent ACKNOWLEDGE signal.
If the master issues a STOP within a Data Byte, or before
the X9525 issues a corresponding ACKNOWLEDGE,
the X9525 cancels the write operation. Therefore, the
contents of the EEPROM array does not change.
EEPROM Array Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
Slave Address Byte is set to one. There are three basic
read operations: Current EEPROM Address Read, Random EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n + 1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation, the master must either issue a STOP condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to
a DCP or the CONSTAT Register (i.e.: an operation
using the Device Type Identifier 1010A011 or
1010A010). Immediately after an operation to a DCP or
CONSTAT Register is performed, only a “Random
EEPROM Read” is available. Immediately following a
“Random EEPROM Read” , a “Current EEPROM
Address Read” or “Sequential EEPROM Read” is once
again available (assuming that no access to a DCP or
CONSTAT Register occur in the interim).
S
t
o
p
Slave
Address
1 0 1 0 A0 0 0 1
A
C
K
Data
Figure 14. Current EEPROM Address Read Sequence
10
FN8210.0
March 10, 2005
X9525
Signals from
the Master
S
t
a
r
t
SDA Bus
WRITE Operation
Slave
Address
Address
Byte
1 0 1 0 0A0 0 0 0
S
t
o
p
1 0 1 0 0A0 0 0 1
A
C
K
Signals from
the Slave
READ Operation
S
t
Slave
a
r Address
t
A
C
K
A
C
K
Data
“Dummy” Write
Figure 15. Random EEPROM Address Read Sequence
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the START condition and the Slave Address Byte,
receives an ACKNOWLEDGE, then issues an Address
Byte. This “dummy” Write operation sets the address
pointer to the address from which to begin the random
EEPROM read operation.
After the X9525 acknowledges the receipt of the Address
Byte, the master immediately issues another START
condition and the Slave Address Byte with the R/W bit
set to one. This is followed by an ACKNOWLEDGE from
the X9525 and then by the eight bit word. The master terminates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In this
case, the device sets the address pointer to that of the
Signals from
the Master
SDA Bus
Slave
Address
Address Byte, and then goes into standby mode after the
STOP bit. All bus activity will be ignored until another
START is detected.
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an ACKNOWLEDGE,
indicating it requires additional data. The X9525 continues to output a Data Byte for each ACKNOWLEDGE
received. The master terminates the read operation by
not responding with an ACKNOWLEDGE and instead
issuing a STOP condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
the entire memory contents to be serially read during
one operation. At the end of the address space the
counter “rolls over” to address 00h and the device continues to output data for each ACKNOWLEDGE
received (Refer to Figure 16.).
A
C
K
A
C
K
A
C
K
S
t
o
p
A0 0 0 1
0
A
C
K
Signals from
the Slave
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
Figure 16. Sequential EEPROM Read Sequence
11
FN8210.0
March 10, 2005
X9525
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
0
0
0
BL1
BL0
RWEL
WEL
0
NV
NV
Bit(s)
CS7 - CS5
BL1 - BL0
RWEL
Description
Always “0”(RESERVED)
Sets the Block Lock partition
The WEL bit is a volatile latch that powers up in the disabled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT register) or until the X9525 powers down, and then up again.
Writes to the WEL bit do not cause an internal high voltage write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 18).
Register Write Enable Latch bit
WEL
Write Enable Latch bit
CS0
Always “0” (RESERVED)
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 17. CONSTAT Register Format
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides
the user with a mechanism for changing and reading
the status of various parameters of the X9525 (See Figure 17).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT register retain their stored values even when Vcc
is powered down, then powered back up. The volatile
bits however, will always power-up to a known logic state
“0” (irrespective of their value at power-down).
A detailed description of the function of each of the CONSTAT register bits follows:
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9525. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See
Figure 18).
—When the X9525 is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X9525 device. This bit must first be enabled before
ANY write operation (to DCPs, EEPROM memory array,
or the CONSTAT register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as the
CONSTAT register, is aborted and no ACKNOWLEDGE
is issued after a Data Byte.
12
The Block Lock protection bits (BL1 and BL0) are
used to:
—Inhibit a write operation from being performed to certain addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper
position”).
FN8210.0
March 10, 2005
X9525
SCL
SDA
S
T
A
R
T
1
0
1
0
A0 1
0
R/W A
C
K
1
1
1
1
1
1
ADDRESS BYTE
SLAVE ADDRESS BYTE
1
1
A
C
K
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
CONSTAT REGISTER DATA IN
A
C
K
S
T
O
P
Figure 18. CONSTAT Register Write Command Sequence
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1 and
BL0 bits written to the CONSTAT register. It is possible
to lock the regions of EEPROM memory shown in the
table below:
BL1 BL0
Protected Addresses
(Size)
Partition of array
locked
0
0
None (Default)
None (Default)
0
1
C0h - FFh (64 bytes)
Upper 1/4
1
0
80h - FFh (128 bytes)
Upper 1/2
1
1
00h - FFh (256 bytes)
All
If the user attempts to perform a write operation on a protected region of EEPROM memory, the operation is
aborted without changing any data in the array.
When the Block Lock bits of the CONSTAT register are
set to something other than BL1 = 0 and BL0 = 0, then
the “wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
BL1
BL0
DCP Write Operation Permissible
0
0
YES (Default)
0
1
NO
1
0
NO
1
1
NO
The factory default setting for these bits are BL1 = 0,
BL0 = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9525 is active (HIGH), then all nonvolatile write operations to both the EEPROM memory and DCPs are inhibited, irrespective of the Block Lock bit settings (See "WP:
Write Protection Pin").
CONSTAT Register Write Operation
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the BP1and BP0 bits.
The X9525 will not ACKNOWLEDGE any data bytes
written after the first byte is entered (Refer to Figure 18.).
When writing to the CONSTAT register, the bits CS7CS5 and CS0 must all be set to “0”. Writing any other bit
sequence to bits CS7-CS5 and CS0 of the CONSTAT
register is reserved.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the Register Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as 000st010 in binary,
where st are the Block Lock Protection (BL1 and BL0)
bits. This operation is proceeded by a START and
ended with a STOP bit. Since this is a nonvolatile write
cycle, it will typically take 5ms to complete. The RWEL
bit is reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2 is
set to ‘1’ in this third step (000s t110) then the RWEL
bit is set, but the BL1 and BL0 bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and the
X9525 does not return an ACKNOWLEDGE.
The CONSTAT register is accessed using the Slave
Address set to 1010A010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT register requires an Address Byte which must be set to FFh.
13
FN8210.0
March 10, 2005
X9525
Signals from
the Master
WRITE Operation
S
t
a
r
t
SDA Bus
Slave Address
Address Byte
1 0 1 0 0A0 1 0 0
11111111
A
C
K
Signals from
the Slave
S
t
a
r
t
READ Operation
Slave Address
S
t
o
p
1 0 1 0 0A0 0 0 1
A
C
K
A
C
K
Data
“Dummy” Write
Figure 19. CONSTAT Register Read Command Sequence
For example, a sequence of writes to the device CONSTAT register consisting of [02H, 06H, 02H] will reset the
BL0 and BL0 bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin
of the X9525 is active (HIGH) (See "WP: Write Protection
Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 19).
Using the Slave Address Byte set to 1010A0101, and an
Address Byte of FFh. Only one byte is read by each register read operation. The X9525 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write operation.
When reading the contents of the CONSTAT register,
the bits CS7-CS5 and CS0 will always return “0”.
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9525. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires
the setting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain regions
of the EEPROM memory, as well as to all the DCPs. One
further level of data protection in the X9525, is incorporated in the form of the Write Protection pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9525.
The table below (X9525 Write Permission Status) summarizes the effect of the WP pin (and Block Lock), on the
write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X9525 also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvolatile write cycle.
X9525 Write Permission Status
Block Lock
Bits
Write to CONSTAT Register
Permitted
BL0
BL1
WP
DCP Volatile Write
Permitted
DCP Nonvolatile
Write Permitted
Write to EEPROM
Permitted
Volatile Bits
Nonvolatile Bits
x
1
1
NO
NO
NO
YES
NO
1
x
1
NO
NO
NO
YES
NO
0
0
1
YES
NO
NO
YES
NO
x
1
0
NO
NO
Not in locked region
YES
YES
1
x
0
NO
NO
Not in locked region
YES
YES
0
0
0
YES
YES
Yes (All Array)
YES
YES
14
FN8210.0
March 10, 2005
X9525
ABSOLUTE MAXIMUM RATINGS
Parameter
Temperature under Bias
Storage Temperature
Voltage on WP pin (With respect to Vss)
Voltage on other pins (With respect to Vss)
| Voltage on RHx - Voltage on RLx | (x = 1,2. Referenced to Vss)
D.C. Output Current (SDA)
Lead Temperature (Soldering, 10 seconds)
Supply Voltage Limits (Applied Vcc voltage, referenced to Vss)
Min.
Max.
Units
-65
-65
-1.0
-1.0
2.7
+135
+150
+15
+7
Vcc
5
300
5.5
°C
°C
V
V
V
mA
°C
V
Min.
Max.
Units
-40
+85
°C
0
RECOMMENDED OPERATING CONDITIONS
Temperature
Industrial
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Figure 20. Equivalent A.C. Circuit
Vcc = 5V
2300Ω
SDA
100pF
Figure 21. DCP SPICE Macromodel
RTOTAL
RHx
CH
CL
RW
RLx
10pF
CW
10pF
25pF
(x = 1,2)
RWx
15
FN8210.0
March 10, 2005
X9525
TIMING DIAGRAMS
Figure 22. Bus Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA IN
tSU:STO
tA
tDH
tBUF
SDA OUT
Figure 23. Physical Device Address (A0) Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
tSU:A0
tHD:A 0
A0
Figure 24. Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK
tWC
Stop
Condition
16
Start
Condition
FN8210.0
March 10, 2005
X9525
Figure 25. Write Protect (WP) Pin Timing During Slave Address
START
Slave Address
SCL
Clk 1
Clk 9
SDA IN
tSU:WP
tHD:WP
WP
Figure 26. Write Protect (WP) Pin Timing
S
t
a
r
t
Slave Address
Address Byte
S
t
o
p
Data
SDA
…
WP
Figure 27. DCP “Wiper Position” Timing
Rwx ( x =1,2)
Rwx(n + 1)
Rwx(n)
Rwx(n - 1)
twr
n = tap position
Time
SCL
SDA
S 1
T
A
R
T
0
1
0
A0 1
1
SLAVE ADDRESS BYTE
17
0
A WT
C
K
0
0
0
0
0
INSTRUCTION BYTE
P1 P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
A
C
K
S
T
O
P
FN8210.0
March 10, 2005
X9525
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions / Notes
0.4
1.5
mA
fSCL = 400kHz
µA
VSDA = VCC
WP = Vss or Open/Floating
VSCL= VCC (when no bus activity
else fSCL = 400kHz)
10
µA
VIN (1) = GND to VCC.
10
µA
1
10
µA
0.1
10
µA
Current into VCC Pin
(X9525: Active)
Read memory array (1)
Write nonvolatile memory
ICC1 (1)
Current into VCC Pin
ICC2
(X9525:Standby)
With 2-Wire bus activity (1)
No 2-Wire bus activity
(1)
ILI
50
50
Input Leakage Current (SCL, SDA)
0.1
Input Leakage Current (WP, A0)
Iai
Analog Input Leakage
ILO
Output Leakage Current (SDA)
VIL (1)
Input LOW Voltage (SCL, SDA, WP, A0)
-0.5
0.8
V
VIH (1)
Input HIGH Voltage (SCL,SDA, WP, A0)
2.0
VCC
+0.5
V
VOLx
SDA Output Low Voltage
0.4
V
VIN = VSS to VCC with all other
analog inputs floating
VOUT (1) = GND to VCC.
X9525 is in Standby (1)
ISINK = 2.0mA
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation.
Notes: 1. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that initiates
a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.
Notes: 1. Current through external pull up resistor not included.
Notes: 1. VIN = Voltage applied to input pin.
Notes: 1. VOUT = Voltage applied to output pin.
Notes: 1. VIL Min. and VIH Max. are for reference only and are not tested
18
FN8210.0
March 10, 2005
X9525
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
400kHz
Symbol
Parameter
Min
Max
Units
400
kHz
fSCL
SCL Clock Frequency
0
tIN (1)
Pulse width Suppression Time at inputs
50
tAA (5)
SCL LOW to SDA Data Out Valid
0.1
tBUF (5)
Time the bus free before start of new transmission
1.3
µs
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
Data Output Hold Time
50
ns
tDH
(5)
ns
µs
0.9
tR (1)
SDA and SCL Rise Time
20 +.1Cb (1)
300
ns
tF (1)
SDA and SCL Fall Time
20 +.1Cb (1)
300
ns
tSU:WPA
WP, A0 Setup Time
0.6
µs
tHD:WPA
WP, A0 Hold Time
0
µs
Cb (5)
Capacitive load for each bus line
400
pF
A.C. TEST CONDITIONS
Input Pulse Levels
0.1VCC to 0.9VCC
Input Rise and Fall Times
10ns
Input and Output Timing Levels
0.5VCC
Output Load
See Figure 20
NONVOLATILE WRITE CYCLE TIMING
Symbol
tWC
(1)
Parameter
Min.
Typ.(1)
Max.
Units
5
10
ms
Nonvolatile Write Cycle Time
CAPACITANCE (TA = 25°C, F = 1.0 MHZ, VCC = 5V)
Symbol
Parameter
Max
Units
Test Conditions
COUT (1)
Output Capacitance (SDA)
8
pF
VOUT = 0V
CIN (1)
Input Capacitance (SCL, WP, A0 )
6
pF
VIN = 0V
Notes: 1. Typical values are for TA = 25°C and VCC = 5.0V
Notes: 1. Cb = total capacitance of one bus line in pF.
Notes: 1. Over recommended operating conditions, unless otherwise specified
Notes: 1. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 1. This parameter is not 100% tested.
19
FN8210.0
March 10, 2005
X9525
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Max.
Units
-20
+20
%
RH Terminal Voltage (x = 1,2)
Vss
VCC
V
VRLx
RL Terminal Voltage (x = 1,2)
Vss
VCC
V
PR
Power Rating (1)(6)
10
mW
RTOTAL = 10kΩ (DCP1)
5
mW
RTOTAL = 50kΩ (DCP2)
200
400
Ω
IW = 1mA, VCC = 5 V,
VRHx = Vcc, VRLx = Vss
(x = 1,2).
400
1200
Ω
IW = 1mA, VCC = 2.7 V,
VRHx = Vcc, VRLx = Vss
(x = 1,2)
4.4
mA
RTOL
End to End Resistance Tolerance
VRHx
RW
IW
Min.
Typ.
DCP Wiper Resistance
Wiper Current(6)
Noise
Test Conditions/Notes
µV/
sqt(Hz)
RTOTAL = 10kΩ ( DCP1)
µV/
sqt(Hz)
RTOTAL = 50kΩ (DCP2)
Absolute Linearity (1)
-1
+1
MI(4)
Rw(n)(actual) - Rw(n)(expected)
Relative Linearity (1)
-1
+1
MI(4)
Rw(n+1) - [Rw(n) + MI]
RTOTAL Temperature Coefficient
CH/CL/CW
Potentiometer Capacitances
twcr
Wiper Response time
VTRIP
Vcc power-up DCP recall threshold
tPU
Vcc power-up DCP recall delay time (6)
±300
ppm/°C
RTOTAL = 10kΩ (DCP1)
±300
ppm/°C
RTOTAL = 50kΩ (DCP2)
pF
10/10/25
200
µs
See Figure 21.
See Figure 27.
V
0.7
1.0
1.3
ms
Notes:1. Power Rating between the wiper terminal RWX(n) and the end terminals RHX or RLX - for ANY tap position n, (x = 1,2).
Notes: 1. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (Rwx(n)(actual) - Rwx(n)(expected)) = ±1
Ml Maximum (x = 1,2).
Notes: 1. Relative Linearity is a measure of the error in step size between taps = RWx(n+1) - [Rwx(n) + Ml] = ±1 Ml (x = 0,1,2)
Notes: 1. 1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1).
Notes: 1. Typical values are for TA = 25°C and nominal supply voltage.
Notes: 1. This parameter is periodically sampled and not 100% tested.
20
FN8210.0
March 10, 2005
X9525
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0
0
0000 0000
1
1
0000 0001
.
.
.
.
.
.
23
23
0001 0111
24
24
0001 1000
25
56
0011 1000
26
55
0011 0111
.
.
.
.
.
.
48
33
0010 0001
49
32
0010 0000
50
64
0100 0000
51
65
0100 0001
.
.
.
.
.
.
73
87
0101 0111
74
88
0101 1000
75
120
0111 1000
76
119
0111 0111
.
.
.
.
.
.
98
97
0110 0001
99
96
0110 0000
21
FN8210.0
March 10, 2005
X9525
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned
{
int
int
int
int
DCP1_TAP_Position(int tap_pos)
block;
i;
offset;
wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{
case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
}
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
return((unsigned)01100000);
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X9525
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0);
else if (tap_pos >99) return ((unsigned) 96);
/* set to min val */
/* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
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X9525
20-Bump Chip Scale Package (CSP B20)
Packaging Outline Drawing
a
9525RR
XACT
YWW I
EYWW
LOT
#
f
d
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C
C1
D4
D3
D2
D1
E3
E2
E1
b
j
E4
m
l
k
e
Side View
Bottom View (Bumped Side)
Top View (Marking Side)
e
c
Side View
Package Dimensions
Ball Matrix:
Millimeters
Symbol
Min
Nominal
Package Width
a
2.542
2.572
2.602
Package Length
b
3.812
3.842
3.872
Package Height
c
0.644
0.677
0.710
Body Thickness
d
0.444
0.457
0.470
Ball Height
e
0.220
0.240
0.260
Ball Diameter
f
0.310
0.330
0.350
Ball Pitch – Width
j
Ball Pitch – Length
k
Ball to Edge Spacing – Width
l
0.511
0.536
0.561
Ball to Edge Spacing – Length
m
0.896
0.921
0.946
24
4
3
2
1
RL2
RW2
Vcc
NC
B
NC
RH2
NC
NC
C
WP
NC
NC
NC
Inches
Max
Min
Nominal
Max
A
D
SCL
A0
NC
RH1
E
SDA
RL1
RW1
Vss
0.5
0.5
FN8210.0
March 10, 2005
X9525
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.300 (6.6)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
(4.16)
.010 (.25)
(7.72)
Gage Plane
0° - 8 °
Seating Plane
.019 (.50)
.029 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X9525
ORDERING INFORMATION
X9525
P
T
Device
Temperature Range
I = Industrial = -40°C to +85°C
Package
V20 = 20-Lead TSSOP
B20 = 20-Lead CSP
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
26
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