APPLICATION NOTE A V A I L A B L E AN84 16K x 8 Bit X24F128 128K 2-Wire SerialFlash with Block LockTM Protection DESCRIPTION The X24F128 is a CMOS SerialFlash Memory, internally organized 16K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. FEATURES • • • • • • • • • • • • Save Critical Data With Programmable Block Lock Protection —Block Lock (0, 1/4, 1/2, or all of E2PROM Array) —Software Program Protection —Programmable Hardware Program Protect In Circuit Programmable ROM Mode Longer Battery Life With Lower Power —Active Read Current Less Than 1mA —Active Program Current Less Than 3mA —Standby Current Less Than 1µA 1.8V to 3.6V or 5V “Univolt” Read and Program Power Supply Versions 32 Word Sector Program Mode —Minimizes Total Program Time Per Word 100KHz 2-Wire Serial Interface Internally Organized 16K x 8 Bidirectional Data Transfer Protocol Self-Timed Program Cycle —Typical Program Cycle Time of 5ms High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years 8-Lead DIP 16-Lead SOIC Three device select inputs (S0–S2) allow up to eight devices to share a common two wire bus. A Program Protect Register at the address location FFFFh provides three program protection features: Software Program Protect, Block Lock Protect, and Hardware Program Protect. The Software Program Protect feature prevents any nonvolatile writes to the device until the PEL bit in the Program Protect Register is set. The Block Lock Protection feature allows the user to individually block protect four blocks of the array by programming two bits in the Program Protect Register. The Programmable Hardware Program Protect feature allows the user to install the device with PP tied to VCC, program the entire memory array in circuit, and then enable the hardware program protection by programming a PPEN bit in the Program Protect Register. After this, selected blocks of the array, including the Program Protect Register itself, are permanently protected from being erased. FUNCTIONAL DIAGRAM DATA REGISTER SERIALFLASH DATA AND ADDRESS (SDA) SCL Y DECODE LOGIC COMMAND DECODE AND CONTROL LOGIC SECTOR DECODE LOGIC SERIALFLASH ARRAY 16K x 8 4K x 8 BLOCK LOCK AND PROGRAM PROTECT CONTROL LOGIC 4K x 8 S2 S1 DEVICE SELECT LOGIC PROGRAM PROTECT REGISTER S0 8K x 8 PROGRAM VOLTAGE CONTROL PP 7012 ILL F01.4 Xicor, 1995, 1996 Patents Pending 7012-0.8 11/25/96 T1/C0/D0 SH 1 Characteristics subject to change without notice X24F128 Xicor SerialFlash Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN NAMES Symbol PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. Description S0, S1, S2 Device Select Inputs SDA Serial Data SCL Serial Clock PP Program Protect VSS Ground VCC Supply Voltage NC No Connect 7012 FRM T01 PIN CONFIGURATION An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet. 8-LEAD DIP Device Select (S0, S1, S2) The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels. S0 1 S1 S2 2 VSS 4 3 X24F128 8 VCC 7 PP 6 SCL 5 SDA 16-LEAD SOIC Program Protect (PP) The Program Protect input controls the Hardware Program Protect feature. When held LOW, hardware program protection is disabled and the device can be programmed normally. When this input is held HIGH, and the PPEN bit in the Program Protect Register is set HIGH, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the Program Protect Register itself. S0 1 16 VCC S1 2 15 PP NC 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC S2 7 10 SCL VSS 8 9 SDA X24F128 7012 ILL F02.1 2 X24F128 Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. DEVICE OPERATION The device supports a bidirectional, bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24F128 will be considered a slave in all applications. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Figure 1. Data Validity SCL SDA DATA STABLE DATA CHANGE 7012 ILL F03 Figure 2. Definition of Start and Stop SCL SDA START BIT STOP BIT 3 7012 ILL F04 X24F128 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a program operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent byte. In the read mode the device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the device to the standby power mode and place the device into a known state. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. Figure 3. Acknowledge Response From Receiver SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 7012 ILL F05 4 X24F128 of the device select input pins. If the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. DEVICE ADDRESSING Following a start condition, the master must output the address of the slave it is accessing. The first four bits of the Slave Address Byte are the device type identifier bits. These must equal “1010”. The next 3 bits are the device select bits S0, S1, and S2. This allows up to 8 devices to share a single bus. These bits are compared to the S0, S1, and S2 device select input pins. The last bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. When it is zero then a program operation is selected. Refer to figure 4. After loading the Slave Address Byte from the SDA bus, the device compares the device type bits with the value “1010” and the device select bits with the status The byte address is either supplied by the master or obtained from an internal counter, depending on the operation. When required, the master must supply the two Address Bytes as shown in figure 4. The internal organization of the E2 array is 512 sectors by 32 bytes per sector. The sector address is partially contained in the Address Byte 1 and partially in bits 7 through 5 of the Address Byte 0. The specific byte address is contained in bits 4 through 0 of the Address Byte 0. Refer to figure 4. Figure 4. Device Addressing DEVICE TYPE IDENTIFIER 1 0 1 DEVICE SELECT 0 S2 S1 S0 R/W SLAVE ADDRESS BYTE HIGH ORDER ADDRESS 0 0 A13 A12 A11 A10 A9 A8 A1 A0 D1 D0 ADDRESS BYTE 1 LOW ORDER ADDRESS A7 A6 A5 A4 A3 A2 ADDRESS BYTE 0 D7 D6 D5 D4 D3 D2 DATA BYTE 7012 ILL F06.1 5 X24F128 respond with an acknowledge after the receipt of each of 31 more bytes. Each time the byte address is internally incremented by one, while the sector address remains constant. When the counter reaches the end of the sector, the master terminates the data loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. All inputs are disabled until completion of the nonvolatile write cycle. The SDA pin is at high impedance. Refer to figure 5 for the address, acknowledge, and data transfer sequence. PROGRAMMING OPERATIONS Sector Program Operation The device executes a thirty-two byte sector program operation. For a sector program operation, the device requires the Slave Address Byte, Address Byte 1, and Address Byte 0. Address Byte 0 must contain the first byte of the sector to be programmed. Upon receipt of Address Byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. After receiving the 8 bits of the first data byte, the device again responds with an acknowledge. The device will Figure 5. Sector Program Sequence SIGNALS FROM THE MASTER S T A R T SDA BUS S 1 0 1 0 SIGNALS FROM THE SLAVE ADDRESS BYTE 1 SLAVE ADDRESS ADDRESS BYTE 0 DATA (32) DATA (1) S T O P 0 P A C K A C K A C K A C K A C K 7012 ILL F08.1 6 X24F128 READ OPERATIONS Acknowledge Polling The maximum program cycle time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a program or read operation. If the device is still busy with the nonvolatile write cycle, then no ACK will be returned. If the device has completed the nonvolatile write operation, an ACK will be returned and the host can then proceed with the read or program operation. Refer to figure 6. Read operations are initiated in the same manner as program operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. Current Address Read Internally, the device contains an address counter that maintains the address of the last byte read or programmed, incremented by one. After a read operation from the last address in the array, the counter will “roll over” to the first address in the array. After a program operation to the last address in a given sector, the counter will “roll over” to the first address of the same sector. Figure 6. Acknowledge Polling Sequence BYTE LOAD COMPLETED BY ISSUING STOP. ENTER ACK POLLING Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the byte at the current address. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to figure 7 for the address, acknowledge, and data transfer sequence. ISSUE START ISSUE SLAVE ADDRESS BYTE (READ OR PROGRAM) ACK RETURNED? ISSUE STOP It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. NO YES Figure 7. Current Address Read Sequence NONVOLATILE WRITE CYCLE COMPLETE. CONTINUE SEQUENCE? NO YES CONTINUE NORMAL READ OR PROGRAM COMMAND SEQUENCE SIGNALS FROM THE MASTER S T A R T SDA BUS S 1 0 1 0 SIGNALS FROM THE SLAVE ISSUE STOP S T O P SLAVE ADDRESS 1 P A C K DATA 7012 ILL F10 PROCEED 7012 ILL F09 7 X24F128 ation is that the new address is loaded into the address counter, but no data is output by the device. Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “Dummy” program operation. The master issues the start condition and the Slave Address Byte with the R/W bit low, receives an acknowledge, then issues Address Byte 1, receives another acknowledge, then issues Address Byte 0 containing the address of the byte to be read. After the device acknowledges receipt of Address Byte 0, the master issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge and then eight bits of data from the device. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to figure 8 for the address, acknowledge, and data transfer sequence. The next Current Address Read operation will read from the newly loaded address. Sequential Read Sequential reads can be initiated as either a current address read or random read. The first byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. At the end of the address space the counter “rolls over” to address 0000h and the device continues to output data for each acknowledge received. Refer to figure 9 for the acknowledge and data transfer sequence. The device will perform a similar operation called “Set Current Address” if a stop is issued instead of the second start shown in figure 9. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. The effect of this oper- Figure 8. Random Read Sequence SIGNALS FROM THE MASTER S T A R T SDA BUS S1 0 1 0 ADDRESS BYTE 1 SLAVE ADDRESS S T A R T ADDRESS BYTE 0 A C K SIGNALS FROM THE SLAVE 1 S 0 A C K S T O P SLAVE ADDRESS A C K P A C K DATA 7012 ILL F11.1 Figure 9. Sequential Read Sequence SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE A C K SLAVE ADDRESS S A C K A C K S T O P 1 P A C K DATA (1) DATA (2) DATA (n–1) DATA (n) 7012 ILL F12.1 8 X24F128 PPEN: Program Protect Enable Bit (Nonvolatile) The Program Protect (PP) pin and the Program Protect Enable (PPEN) bit in the Program Protect Register control the Programmable Hardware Program Protection feature. Hardware Program Protection is enabled when the PP pin is HIGH and the PPEN bit is HIGH, and disabled when either the PP pin is LOW or the PPEN bit is LOW. When the chip is Hardware Program Protected, nonvolatile writes are disabled to the Program Protect Register, including the Block Lock Protect bits and the PPEN bit itself, as well as to the Block Lock protected sections in the memory array. Only the sections of the memory array that are not Block Lock protected, and the volatile bits PEL and RPEL, can be programmed. PROGRAM PROTECT REGISTER (PPR) Register Program Operation The Program Protect Register can only be modified by programming one data byte directly to the address FFFFh as described below. The data byte must contain zeroes where indicated in the procedural descriptions below; otherwise the operation will not be performed. Only one data byte is allowed for each Register Program Operation. The part will not acknowledge any data bytes after the first byte is entered. The user then has to issue a stop to initiate the nonvolatile write cycle that programs BL0, BL1, and PPEN to the nonvolatile bits. A stop must also be issued after volatile register program operations to put the device into Standby. In Circuit Programmable ROM Mode Note that since the PPEN bit is program protected, it cannot be changed back to a LOW state; so program protection is enabled as long as the PP pin is held HIGH. Thus an In Circuit Programmable ROM function can be implemented by hardwiring the PP pin to Vcc, programming and Block Locking the desired portion of the array to be ROM, and then programming the PPEN bit HIGH. Figure 11 defines the program protect status for each combination of PPEN and PP. The state of the Program Protect Register can be read by performing a random read at FFFFh at any time. The part will reset itself after the first byte is read. The master should supply a stop condition to be consistent with the protocol. After the read, the address counter contains 0000h. Program Protect Register: PPR (ADDR = FFFFh) 7 6 5 4 3 2 1 0 PPEN 0 0 BL1 BL0 RPEL PEL 0 Programming the PEL and RPEL bits PEL and RPEL are volatile latches that power up in the LOW (disabled) state. While the PEL bit is LOW, program operations to any address other than FFFFh will be ignored (no acknowledge will be issued after the data byte). The PEL bit is set by programming 00000010 to address FFFFh. Once set, PEL remains HIGH until either it is reset to 0 (by programming 00000000 to FFFFh) or until power cycles. Programming PEL and RPEL does not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. PEL: Program Enable Latch (Volatile) 0 = PEL reset, programming disabled. 1 = PEL set, programming enabled. RPEL: Register Program Enable Latch (Volatile) 0 = RPEL reset, programs to the Program Protect Register disabled. 1 = RPEL set, programs to the Program Protect Register enabled. The RPEL bit controls programming to the Block Lock Protect bits, BL0 and BL1, and the PPEN bit. If RPEL is 0 then no programming operations can be performed on BL0, BL1, or PPEN. RPEL is reset when power cycles or after any nonvolatile write, including those to the Block Lock Protect bits, the PPEN bit, or any sector in the memory array. RPEL must be reset before PEL can be reset. RPEL and PEL cannot be reset in one program operation. RPEL can also be reset by programming u00xy010 to FFFFh ONLY when the PPR is NOT protected. This is the same operation as in step 3 described below, and will result in programming BL0, BL1, and PPEN. BL0, BL1: Block Lock Protect Bits (Nonvolatile) The Block Lock Protect Bits, BL0 and BL1, determine which blocks of the array are protected. A program to a protected block of memory is ignored, but will receive an acknowledge. The master must issue a stop to put the part into standby, just as it would for a valid program; but the stop will not initiate an internal nonvolatile write cycle. See figure 10. 9 X24F128 Programming to the BL and PPEN Bits A 3 step sequence is required to change the nonvolatile Block Lock Protect or Program Protect Enable bits: RPEL bit in the data byte for step 3 is a one, then no changes are made to the Program Protect Register and the device remains at step 2. 1) Set PEL=1, Program 00000010 to address FFFFh (Volatile Write Cycle.) The PP pin must be LOW or the PPEN bit must be LOW before a nonvolatile register program operation is initiated. Otherwise, the program operation will abort and the device will go into standby mode after the master issues the stop condition in step 3. 2) Set RPEL=1, Program 00000110 to address FFFFh (Volatile Write Cycle.) 3) Set BL1, BL0, and/or PPEN bits, Program u00xy010 to address FFFFh, where u=PPEN, x=BL1, and y=BL0. (Nonvolatile Write Cycle.) Step 3 is a nonvolatile write operation, requiring 10mS max to complete (acknowledge polling may be used to reduce this time requirement). It should be noted that step 3 MUST end with a stop condition. If a start condition is issued during or at the end of step 3 (instead of a stop condition) the device will abort the nonvolatile register program and remain at step 2. If the operation is aborted with a start condition, the master must issue a stop to put the device into standby mode. The three step sequence was created to make it difficult to change the contents of the Program Protect Register accidentally. If PEL was set to one by a previous register program operation, the user may start at step 2. RPEL is reset to zero in step 3 so that user is required to perform steps 2 and 3 to make another change. RPEL must be 0 in step 3. If the Figure 10. Block Lock Protect Bits and Protected Addresses Protected Addresses BL1 BL0 Array Location X24F128 0 0 None No Protect 0 1 3000h - 3FFFh Upper 1/4 1 0 2000h - 3FFFh Upper 1/2 1 1 0000h - 3FFFh Full Array 7012 FRM T02 Figure 11. PP Pin and PPEN Bit Functionality PP PPEN Memory Array Not Lock Block Protected Memory Array Block Lock Protected Block Lock Bits PPEN Bit 0 X Programmable Protected Programmable Programmable X 0 Programmable Protected Programmable Programmable 1 1 Programmable Protected Protected Protected 7012 FRM T03 10 X24F128 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X24F128.....................................–65°C to +135°C Storage Temperature ........................–65°C to +150°C Voltage on any Pin with Respect to VSS .................................... –1V to +7V D.C. Output Current ..............................................5mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits 1.8V to 3.6V 4.5V to 5.5V Commercial 0°C +70°C X24F128 Extended –20°C +85°C X24F128–5 7012 FRM T05 7012 FRM T04 D.C. OPERATING CHARACTERISTICS Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA ICC2 VCC Supply Current (Program) 3 mA ISB1(1) VCC Standby Current 10 µA SCL = SDA = VCC – 0.3V, All Other Inputs = VSS or VCC – 0.3V, VCC = 5V ± 10% ISB2(1) VCC Standby Current 1 µA SCL = SDA = VCC – 0.1V, All Other Inputs = VSS or VCC – 0.1V, VCC = 1.8V ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VlL(2) Input LOW Voltage –0.5 VCC x 0.3 V VIH(2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V Vhys(3) Hysteresis of Schmitt Trigger Inputs VCC x 0.05 SCL = VCC X 0.1/VCC X 0.9 Levels @ 100KHz, SDA = Open, All Other Inputs = VSS or VCC – 0.3V IOL = 3mA V 7012 FRM T06.1 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Parameter Max. Units Test Conditions CI/O(3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN(3) Input Capacitance (S0, S1, S2, SCL, PP) 6 pF VIN = 0V 7012 FRM T07 Notes: (1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. 11 X24F128 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 5V 1.53KΩ 10ns Input and Output Timing Levels OUTPUT VCC X 0.5 100pF 7012 FRM T08 7012 ILL F14.1 A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Program Cycle Limits Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs 50 100 ns tAA SCL LOW to SDA Data Out Valid 0.3 3.5 µs tBUF Time the Bus Must Be Free Before a New Transmission Can Start 4.7 µs tHD:STA Start Condition Hold Time 4 µs tLOW Clock LOW Period 4.7 µs tHIGH Clock HIGH Period 4 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 µs tHD:DAT Data In Hold Time 0 µs tSU:DAT Data In Setup Time 250 ns tR SDA and SCL Rise Time 1 µs tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 4.7 µs tDH Data Out Hold Time 300 ns 7012 FRM T09 POWER-UP TIMING(4) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms 7012 FRM T10 Notes: (4) tPUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 12 X24F128 Bus Timing tHIGH tF tLOW tR SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT 7012 ILL F15 Program Cycle Limits Symbol Parameter Min. TWR(6) Program Cycle Time Typ.(5) Max. Units 5 10 ms 7012 FRM T11 Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the nonvolatile write operation. The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal erase/program cycle. During the program cycle, the X24F128 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Bus Timing SCL SDA 8th BIT ACK WORD n tWR STOP CONDITION Guidelines for Calculating Typical Values of Bus Pull-Up Resistors START CONDITION SYMBOL TABLE WAVEFORM RESISTANCE (KΩ) 120 RMIN = 100 80 VCC MAX =1.8KΩ IOL MIN RMAX = tR CBUS MAX. RESISTANCE 60 40 20 MIN. RESISTANCE 0 0 20 40 60 80 100 120 BUS CAPACITANCE (pF) 7012 ILL F16 7012 ILL F17 13 INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X24F128 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.145 (3.68) 0.128 (3.25) SEATING PLANE 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) 0.015 (0.38) MAX. 0.060 (1.52) 0.020 (0.51) 0.325 (8.25) 0.300 (7.62) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F01 14 X24F128 PACKAGING INFORMATION 16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.51) 0.386 (9.80) 0.394 (10.01) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0° – 8° 0.250" 0.0075 (0.19) 0.012 (0.30) 0.016 (0.410) 0.037 (0.937) FOOTPRINT 0.030" Typical 16 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F26 15 X24F128 ORDERING INFORMATION X24F128 X X -X V CC Range Blank = 1.8V to 3.6V 5 = 4.5V to 5.5V Device Temperature Range Blank = 0°C to +70°C E = –20°C to +85°C Package X24F128 P = 8-Lead Plastic DIP S = 16-Lead SOIC Part Mark Convention X24F128 X P = 8-Lead Plastic DIP S = 16-Lead SOIC X Blank = 1.8V to 3.6V, 0°C to +70°C E = 1.8V to 3.6V, –20°C to +85°C 5 = 4.5V to 5.5V, 0°C to +70°C E5 = 4.5V to 5.5V, –20°C to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 16