www.fairchildsemi.com FAN5070 High Performance Programmable Synchronous DC-DC Controller Features Description • Output programmable in 25mV steps from 1.05V to 1.825V using a dynamically programmable integrated 5-bit DAC • Remote sense • Programmable Active Droop™ up to 200mV • Drives N-Channel MOSFETs • Overcurrent protection using MOSFET sensing • Overvoltage protection including startup • 85% efficiency typical at full load • Integrated Power Good and Enable/Soft Start functions • Meets Intel VRM8.5 specifications using minimum number of external components • 20 pin SOIC package The FAN5070 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable output voltage for platforms such as the Intel Pentium III, and provides a complete solution for all Intel VRM8.5 CPU applications, and for other high-performance processors. The FAN5070 features remote voltage sensing, independently adjustable current limit, and a proprietary wide-range Programmable Active Droop™ for optimal converter transient response and VRM8.5 compliance. The FAN5070 uses a 5-bit D/A converter to dynamically program the output voltage during operation from 1.05V to 1.825V in 25mV steps. The FAN5070 uses a high level of integration to deliver load currents in excess of 28A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves 0.8% voltage regulation without expensive external components. The FAN5070 also offers integrated functions including opencollector Power Good, Output Enable/Soft Start and current limiting, and is available in a 20 pin SOIC package. Applications • Power supply for Pentium® III Platforms • VRM for Pentium III processor • Programmable power supply Block Diagram +5V VCCA 17 15 + RD +12V OCL + OSC +5V 14 RS 16 20 VCCP 1 HIDRV + + Digital Control + 2 VCC 19 LODRV 18 GNDP 5-Bit DAC 8 7 65 4 VID0 VID2 VID4 VID1 VID3 1.24V Reference Power Good 3 GNDA 13 PWRGD 12 ENABLE/SS Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor. REV. 1.0.1 8/7/01 FAN5070 Pin Assignments HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VREF NC 1 2 3 4 5 6 7 8 9 10 FAN5070 20 19 18 17 16 15 14 13 12 11 VCCP LODRV GNDP VCCA VFB DROOP ILIM PWRGD SS/ENABLE NC Pin Definitions Pin Number Pin Name Pin Function Description 1 HIDRV High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". 2 SW High Side Driver Source and Low Side Driver Drain Switching Node. Together with DROOP and ILIM pins allows FET sensing for VCC current. 3 GNDA Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. 4-8 VID4-0 Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. 9 VREF DAC Output for Test Only. Do not load externally. 10, 11 NC 12 ENABLE/SS 13 PWRGD 14 ILIM 15 DROOP 16 VFB 17 VCCA Analog VCC. Connect to system 5V supply and decouple with a 0.1µF ceramic capacitor. 18 GNDP Power Ground. Return pin for high currents flowing in pin 17 (VCCP). 19 LODRV VCC Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5". 20 VCCP Power VCC. For all FET drivers. Connect to system 12V supply through a 33Ω, and decouple with a 1µF ceramic capacitor. 2 NC. No Connect. Output Enable. A logic LOW on this pin will disable all outputs. An internal current source allows for open collector control. This pin also doubles as soft start for all outputs. Power Good Flag. An open collector output that will be logic LOW if any output voltage is not within ±14% of the nominal output voltage setpoint. VCC Current Feedback. Pin 11 is used in conjunction with pin 2 as the input for the VCC current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. Droop Set. Use this pin to set magnitude of active droop. Vcc Voltage Feedback. Pin 13 is used as the input for the VCC voltage feedback control loop. See Application Information for details regarding correct layout. REV. 1.0.1 8/7/01 FAN5070 Absolute Maximum Ratings Supply Voltage VCCP to GND 15V Supply Voltage VCCA to GND 13.5V Voltage Identification Code Inputs, VID0-VID4 VCCA All Other Pins 13.5V 150°C Junction Temperature, TJ Storage Temperature -65 to 150°C Lead Soldering Temperature, 10 seconds Thermal Resistance Junction-to-case, 300°C Θ 1JA 75°C/W Note 1: Component mounted on demo board in free air. Recommended Operating Conditions Parameter Min. Typ. Max. Units Supply Voltage VCCA Conditions 4.50 5 5.25 V Input Logic HIGH 2.0 V Input Logic LOW Ambient Operating Temperature 0 10.8 Output Driver Supply, VCCP 12 0.8 V 70 °C 13.2 V Electrical Specifications (VCCA = 5V, VCCP = 12V, VOUT = 1.425V, and TA = +25°C using circuits in Figure 1, unless otherwise noted.) The • denotes specifications which apply over the full operating temperature range. Parameter Conditions Output Voltage See Table I Min. • 1.05 Output Current Initial Voltage Setpoint ILOAD = 0.8A, VVID = 1.425V Output Temperature Drift TA = 0 to 70°C, VVID = 1.425V • Line Regulation VIN = 4.75V to 5.25V • Internal Droop Impedance3 ILOAD = 0.8A to 30A Maximum Programmable Droop Output Ripple Total Output Variation, Transient2 ILOAD = 0.8A to Imax, VVID = 1.425V Short Circuit Detect Current Max. Units 1.825 V 28 A 1.453 1.465 1.477 V -6 mV +10 13.0 14.4 mV/V 15.8 KΩ • 200 • 1.360 1.490 V • 1.335 1.515 V • 45 60 µA 20MHz BW, ILOAD = 28A Total Output Variation, Steady State1 VVID = 1.425V3 Typ. mV 20 50 mVpk Efficiency ILOAD = 18A, VVID = 1.425V 83 % Output Driver Rise & Fall Time See Figure 3 50 nsec Output Driver Deadtime See Figure 3 50 Duty Cycle 0 nsec 100 % 4 4.24 V 5V UVLO • 3.76 12V UVLO • 7.65 8.5 9.35 V Oscillator Frequency • 255 300 345 kHz • • 88 80 112 120 % PWRGD Threshold4 Switcher Logic HIGH [VVID + 85mV] Logic LOW [VVID–155mV] PWRGD Delay Switcher HIGH → LOW PWRGD Hysteresis Switcher REV. 1.0.1 8/7/01 6 µsec 25 mV 3 FAN5070 Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter’s VFB sense point. 2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5mΩ trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter’s output at the load, and the appropriate droop, the converter will be in compliance with Intel’s VRM 8.5 specification. If Intel specifications on maximum plane resistance from the converter’s output capacitors to the CPU are met, the specifications at the capacitors will also be met. Table 1. Output Voltage Programming Codes for FAN5070 VID25mV VID3 VID2 VID1 VID0 Nominal VOUT 0 0 1 0 0 1.050V 1 0 1 0 0 1.075V 0 0 0 1 1 1.100V 1 0 0 1 1 1.125V 0 0 0 1 0 1.150V 1 0 0 1 0 1.175V 0 0 0 0 1 1.200V 1 0 0 0 1 1.225V 0 0 0 0 0 1.250V 1 0 0 0 0 1.275V 0 1 1 1 1 1.300V 1 1 1 1 1 1.325V 0 1 1 1 0 1.350V 1 1 1 1 0 1.375V 0 1 1 0 1 1.400V 1 1 1 0 1 1.425V 0 1 1 0 0 1.450V 1 1 1 0 0 1.475V 0 1 0 1 1 1.500V 1 1 0 1 1 1.525V 0 1 0 1 0 1.550V 1 1 0 1 0 1.575V 0 1 0 0 1 1.600V 1 1 0 0 1 1.625V 0 1 0 0 0 1.650V 1 1 0 0 0 1.675V 0 0 1 1 1 1.700V 1 0 1 1 1 1.725V 0 0 1 1 0 1.750V 1 0 1 1 0 1.775V 0 0 1 0 1 1.800V 1 0 1 0 1 1.825V Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is pulled up to 3.3V. 4 REV. 1.0.1 8/7/01 FAN5070 Typical Operating Characteristics (VCCA = 5V, VCCP = 12V, and TA = +25°C using circuit in Figure 1, unless otherwise noted.) Vcpu Efficiency vs.Output Current Droop,Circuit of Fig.1 90 1.48 1.46 85 1.42 Vout (V) Efficiency (%) 1.44 80 1.4 75 1.38 70 1.36 65 2 4 6 8 10 12 14 16 18 Output Current (A) 20 22 24 26 1.34 28 0 Output Ripple, 1.425 @ 28A 3 6 9 12 15 Output Current (A) 18 21 24 28 Transient Response, 28A to 0.1A VCPU (50mV/div) VCPU (20mV/div) 1.515V 1.425V 1.335V Time (2 s/division) Time (20 s/division) Transient Response, 0.1A to 28A VCPU (50mV/div) 1.515V HIDRV pin 1.425V Time (20 s/division) 5V/div LODRV pin 1.335V 5 5V/div Switching Waveforms, 28A Load Time (20 s/division) REV. 1.0.1 8/7/01 FAN5070 Typical Operating Characteristics (continued) Output Startup from Enable VIM (2V/div) VCPU (1V/div) ENABLE (2V/div) VCPU (1V/div) Output Startup, System Power-up Time (20ms/div) Time (10ms/division) Application Circuit L1 (Optional) +5V CIN* C1 R6 R1 R2 C2 R3 Q1 L2 VO COUT* VID4 VID3 VID2 VID1 VID0 D1 Q2 R4 R8–12 1 2 3 4 5 6 7 8 9 10 20 19 18 U1 FAN5070 17 16 15 14 13 12 11 R7 +12V C6 C5 ENABLE/SS C3 VCC 3.3V R5 PWRGD C4 Figure 1. Application Circuit for VRM8.5 Motherboards (Worst Case Analyzed! See Appendix for Details) REV. 1.0.1 8/7/01 6 FAN5070 Table 3. FAN5070 Application Bill of Materials for Intel VRM8.5 Motherboards (Components based on Worst Case Analysis—See Appendix for Details) Reference Manufacturer Part # Quantity Description Requirements/Comments C1 AVX TAJB475M010R5 1 4.7µF, 10V Capacitor C2, C5 Panasonic ECU-V1C105ZFX 2 1µF, 16V Capacitor C3-4,C6 Panasonic ECU-V1H104ZFX 3 100nF, 50V Capacitor CIN Rubycon 16ZL1000M 4 1000µF, 16V Electrolytic IRMS = 2.3A COUT Rubycon 6.3ZL1500M 8 1500µF, 6.3V Electrolytic ESR ≤ 23mΩ D1 Motorola MBRD835L 1 8A Schottky Diode L1 Any L2 Optional 1.3µH, 10A Inductor DCR ~ 6mΩ See Note 1. Coiltronics HC2-1R0 1 1.0µH, 34A Inductor DCR ~ 1mΩ Q1 Fairchild FDD6690A 2 N-Channel MOSFET RDS(ON) = 17mΩ @ VGS = 4.5V See Note 2. Q2 Fairchild FDD6680A 2 N-Channel MOSFET RDS(ON) = 9.5mΩ @ VGS = 4.5V See Note 2. R1 Any 1 8.66KΩ R2 Any 1 27.4KΩ R3-4 Any 2 4.7Ω R5, R8-12 Any 6 10KΩ R6-7 Any 2 10Ω Fairchild FAN5070M 1 DC/DC Controller U1 Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For 30A designs using the TO-220 MOSFETs, heatsinks with thermal resistance ΘSA < 20°C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletins AB-8 and AB-15. Test Parameters tR tF 90% 10% 2V t DT 2V 90% HIDRV 10% 2V tDT 2V LODRV Figure 2. Output Drive Timing Diagram 7 REV. 1.0.1 8/7/01 FAN5070 Application Information The FAN5070 Controller The FAN5070 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the FAN5070 can be configured to deliver more than 28A of output current, as appropriate for Intel’s VRM8.5, and other processors. The FAN5070 functions as a fixed frequency PWM step down regulator. Internal Voltage Reference The reference included in the FAN5070 is a precision bandgap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. In the FAN5070, the DAC monitors the 5 voltage identification pins, VID0-4, and scales the voltage from 1.050V to 1.825V in 25mV steps according to Table I. Main Control Loop Refer to the FAN5070 Block Diagram on page 1. The FAN5070 implements “summing mode control,” which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the DROOP (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the DROOP and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the FAN5070 current limit comparator disables the output drive signals to the external power MOSFETs. Power Good (PWRGD) The FAN5070 Power Good function is designed in accordance with VRM8.5 and DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should be more than +14% from (VVID + 80mV), or less than –14% from (VVID – 120mV). The Power Good flag provides no other control function to the FAN5070. Output Enable/Soft Start (ENABLE/SS) The FAN5070 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching. Over-Voltage Protection The FAN5070 continuously monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds approximately 2.5V, an OVP circuit forces the low-side MOSFET on, over-riding all other conditions. The OVP circuit remains active, and the low-side MOSFET remains on, until the VFB voltage drops below approximately 2.1V. The OVP circuit is functional even during startup; thus, protection is provided even during startup with a shorted high-side MOSFET. Oscillator The FAN5070 oscillator section uses a fixed frequency of operation of 300KHz. High Current Output Drivers The FAN5070 contains two identical high current output drivers that utilize high speed bipolar transistors in a pushpull configuration. The drivers’ power and ground are separated from the chip’s power and ground for switching noise immunity. The power supply pin, VCCP, is supplied from an external 12V source through a series resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON. 8 REV. 1.0.1 8/7/01 FAN5070 Design Considerations and Component Selection Additional information on design and component selection may be found in Fairchild’s Application Note 57. MOSFET Selection This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: • Low Static Drain-Source On-Resistance, RDS,ON < 20mΩ (lower is better) • Low gate drive voltage, VGS = 4.5V rated • Power package with low Thermal Resistance • Drain-Source voltage rating > 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8. Inductor Selection Choosing the value of the inductor is a trade-off between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is: (Vin – Vout) f x Vout Vin ESR x The FAN5070 protects against output short circuit on the core supply by latching off both the high-side and low-side MOSFETs. The FAN5070 short circuit current characteristic includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. The short circuit limit is set with the RS resistor, as given by the formula RS = ISC *RDS, on IDetect with IDetect ≈ 50µA, ISC the desired current limit, and RDS,on the high-side MOSFET’s on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET’s RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET, as shown in Figure 6, eliminates this source of inaccuracy in the current limit. As an example, Figure 3 shows the typical characteristic of the DC-DC converter circuit with two FDD6690A high-side MOSFETs (RDS = 17mΩ maximum at 25°C * 1.25 at 75°C = 21.25mΩ each for a total of 10.6mΩ) and a 6.19KΩ RS. Vripple where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is: Lmax = 2CO FAN5070 Short Circuit Current Characteristics (Vin – Vout) Dm Vtb VOUT (V) Lmin = Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The FAN5070 provides significant cost savings for the newer CPU systems that typically run at high supply current. 0 10 20 30 40 50 Output Current (A) Ipp2 Figure 3. FAN5070 Short Circuit Characteristic where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%). REV. 1.0.1 8/7/01 The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50µA * 6.2KΩ = 310mV, which occurs at 310mV/10.6mΩ = 29A. [Note that this current limit level can be as high as 310mV/6.5mΩ = 48A, if the MOSFET has typical RDS,on rather than maximum, and is at 25°C. This is the reason for using the external sense resistor.] At this point, the internal comparator trips and signals the 9 FAN5070 controller to reduce the converter’s duty cycle to approximately 20%. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 4mΩ output short, the voltage is reduced to 29A * 4mΩ = 116mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating range for the DC-DC converter. deliver current when the high side MOSFET switches on. Figure 4 shows 3 x 1000µF, but the exact number required will vary with the speed and type of the processor. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15. Schottky Diode Selection The application circuits of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET’s body diode. Output Filter Capacitors The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1µF and 0.01µF are recommended values. 2.5µH Vin 5V 1000µF, 10V Electrolytic 0.1µF Figure 4. Input Filter Programmable Active Droop™ The FAN5070 includes Programmable Active Droop™: as the output current increases, the output voltage drops, and the amount of this drop is user adjustable. This is done in order to allow maximum headroom for transient response of the converter. The current is typically sensed by measuring the voltage across the RDS,on of the high-side MOSFET during its on time, as shown in Figures 1 and 2. To program the amount of droop, use the formula RD 14.4KΩ *Imax *Rsense VDroop *9 where Imax is the current at which the droop occurs, and Rsense is the resistance of the current sensor, either the source resistor or the high-side MOSFET’s on-resistance. For example, to get 120mV of droop with a maximum output current of 30A and a 10mΩ sense resistor, use RD = 14.4KΩ * 30A * 10mΩ/(120mV * 9) = 4KΩ. The value of the product Imax*Rsense must be < 600mV for proper functioning of the droop circuit. If this product is exceeded, a lower resistance MOSFET must be used. Further details on use of the Programmable Active Droop™ may be found in Applications Bulletin AB-24. Remote Sense Input Filter The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 5. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5µH is recommended. The FAN5070 offers remote sense of the output voltage to minimize the output capacitor requirements of the converter. It is highly recommended that the remote sense pin, Pin 20, be tied directly to the processor power pins, so that the effects of power plane impedance are eliminated. Further details on use of the remote sense feature of the FAN5070 may be found in Applications Bulletin AB-24. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors 10 REV. 1.0.1 8/7/01 FAN5070 PCB Layout Guidelines • Placement of the MOSFETs relative to the FAN5070 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5070 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. • In general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5070. That is, traces that connect to pins 1, 2, 16, and 17 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 13 and 14. • Place the 0.1µF decoupling capacitors as close to the FAN5070 pins as possible. Extra lead length on these reduces their ability to suppress noise. • Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. • Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. • Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. • A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. Additional Information For additional information contact your local Fairchild Semiconductor representative, or visit us at our web site www.fairchildsemi.com. REV. 1.0.1 8/7/01 11 FAN5070 Appendix Number of capacitors needed for COUT = the greater of: Worst-Case Formulae for the Calculation of Cin, Cout, R5, R7 and Roffset (Circuits similar to Figure 1 only) The following formulae design the FAN5070 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, internal droop impedance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: VS+, the value of the positive static voltage limit; |VS-|, the absolute value of the negative static voltage limit; VT+, the value of the positive transient voltage limit; ESR * IO X = VT- or ESR * IO Y= 14400 * IO * RD VT+ – VS+ + 18 * R5 * 1.1 Example: Suppose that the static limits are +89mV/-79mV, transient limits are ±134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing. We have VS+ = 0.089, |VS-| = 0.079, VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and ∆RD = 1.67. We calculate: |VT-|, the absolute value of the negative transient voltage limit; 2.000 14.2 * 5 IO, the maximum output current; + VS+ – .024 * Vnom – 2.000 2 5 Cin = = 3.47 ⇒ 4 caps 2 Vnom, the nominal output voltage; Roffset = Vin, the input voltage (typically 5V); Irms, the ripple current rating of the input capacitors, per cap (2A for the Sanyo parts shown in this data sheet); R7 = 0.089 – .014 * 2.000 – .029 *1000 = 15.8Ω 0.29 + 2.000 14.2 * 0.020 * (1 + 0.67) = 10.5KΩ 45 * 10-6 RD, the resistance of the current sensor (usually the MOSFET); ∆RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature); and R5 = 2 IO * – Vin Cin = Vnom X= 0.044 * 14.2 = 3.57 0.134 + 0.089 – .024 * 2.00 0.044 * 14.2 = 6.14 Y = 0.134 – 0.089 + Vin = 3.48KΩ 18 * (0.089 + 0.079 – .024 * 2.000) ESR, the ESR of the output capacitors, per cap (44mΩ for the Sanyo parts shown in this data sheet). Vnom 14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1 14400 * 14.2 * 0.020 18 * 3640 * 1.1 Irms Roffset = VS+ – .014 * Vnom – .029 Since Y > X, we choose Y, and round up to find we need 7 capacitors for COUT. * 1KΩ .029 * Vnom R7 = A detailed explanation of this calculation may be found in Applications Bulletin AB-24. IO* RD * (1 + ∆RD) 45 * 10-6 14400 * IO* RD * (1 + ∆RD) *1.1 R5 = 18 * (VS+ + VS- – .024 * Vnom) 12 REV. 1.0.1 8/7/01 FAN5070 Mechanical Dimensions 20 Lead SOIC Inches Symbol Min. A A1 B C D E e H h L N α ccc Notes: Millimeters Max. Min. Notes .093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC .394 .010 .016 10.00 0.25 0.40 .419 .029 .050 20 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. Max. 10.65 0.75 1.27 20 0° 8° 0° 8° — .004 — 0.10 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. 3 6 11 20 E H 10 1 h x 45° D C A1 A e B SEATING PLANE –C– LEAD COPLANARITY α L ccc C 13 REV. 1.0.1 8/7/01 FAN5070 Ordering Information Product Number Description Package FAN5070M VRM8.5 20 pin SOIC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/7/01 0.0m 006 Stock#DS30005070 2001 Fairchild Semiconductor Corporation