Data Sheet

HEF4017B-Q100
5-stage Johnson decade counter
Rev. 1 — 4 June 2014
Product data sheet
1. General description
The HEF4017B-Q100 is a 5-stage Johnson decade counter with ten spike-free decoded
active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant
flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding
asynchronous master reset input (MR).
The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or
a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3).
When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,
6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR
resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock
inputs (CP0, CP1).
Automatic counter code correction is provided by an internal circuit: following any illegal
code the counter returns to a proper counting mode within 11 clock pulses.
Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Automatic counter correction
 Tolerant of slow clock rise and fall times
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 ESD protection:
 MIL-STD-833, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Complies with JEDEC standard JESD 13-B
HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C
Type number
Package
Name
HEF4017BT-Q100 SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
4. Functional diagram
13
14
15
CP1
CP0
5-STAGE JOHNSON COUNTER
MR
Q5-9
DECODING AND OUTPUT CIRCUITRY
12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
3
Fig 1.
2
4
7
10
1
5
6
9
11
001aah242
Q
FF
4
CP Q
RD
D
Functional diagram
Q
FF
1
CP Q
RD
Q
FF
2
CP Q
RD
D
CP1
CP0
Q
FF
3
CP Q
RD
D
D
Q
FF
5
CP Q
RD
D
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q5-9
001aah243
Fig 2.
Logic diagram
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 18
HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
CTRDIV10/DEC
14
13
14
15
3
Q1
2
Q2
4
Q3
7
3
Q4
10
4
Q5
1
5
Q6
5
6
Q7
6
7
Q8
9
8
Q9
11
9
Q5-9
12
CT≥5
MR
13
15
&
1
CT = 0
2
3
2
4
7
10
1
5
6
9
11
12
001aah240
001aah239
Fig 3.
0
Q0
CP1
CP0
Logic symbol
Fig 4.
IEE logic symbol
5. Pinning information
5.1 Pinning
+()%4
4
9''
4
05
4
&3
4
&3
4
4
4
4
4
4
966
4
DDD
Fig 5.
Pin configuration
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
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3 of 18
HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Q0 to Q9
3, 2, 4, 7, 10, 1, 5, 6, 9, 11
decoded output
VSS
8
ground supply voltage
Q5-9
12
carry output (active LOW)
CP1
13
clock input (HIGH-to-LOW edge-triggered)
CP0
14
clock input (LOW-to-HIGH edge-triggered)
MR
15
master reset input
VDD
16
supply voltage
6. Functional description
Table 3.
Function table [1]
MR
CP0
CP1
Operation
H
X
X
Q0 = Q5-9 = H; Q1 to Q9 = L
L
H

counter advances
L

L
counter advances
L
L
X
no change
L
X
H
no change
L
H

no change
L

L
no change
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
 = positive-going transition;  = negative-going transition.
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 18
HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
Fig 6.
001aah244
Timing diagram
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 18
HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
IDD
supply current
-
50
mA
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+125
C
-
500
mW
-
100
mW
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Ptot
total power dissipation
Tamb = 40 C to +125 C
P
power dissipation
per output
[1]
[1]
Min
Max
Unit
0.5
+18
V
-
10
mA
0.5
VDD + 0.5
V
-
10
mA
-
10
mA
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
supply voltage
3
-
15
V
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
40
-
+125
C
t/V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
HEF4017B_Q100
Product data sheet
Conditions
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Rev. 1 — 4 June 2014
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HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
9. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level
input voltage
Conditions
IO < 1 A
Tamb = 40 C
Tamb = 25 C
Tamb = 85 C
Min
Min
Max
Min
Max
Max
Tamb = 125 C Unit
Min
Max
5V
3.5
-
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
-
0.05
V
HIGH-level
VO = 2.5 V
output current V = 4.6 V
O
5V
-
1.7
-
1.4
-
1.1
-
1.1
mA
5V
-
0.64
-
0.5
-
0.36
-
0.36 mA
VO = 9.5 V
10 V
-
1.6
-
1.3
-
0.9
-
0.9
mA
VO = 13.5 V
15 V
-
4.2
-
3.4
-
2.4
-
2.4
mA
LOW-level
input voltage
IO < 1 A
HIGH-level
IO < 1 A;
output voltage VI = VSS or VDD
LOW-level
IO < 1 A;
output voltage VI = VSS or VDD
LOW-level
VO = 0.4 V
output current V = 0.5 V
O
5V
0.64
-
0.5
-
0.36
-
0.36
-
mA
10 V
1.6
-
1.3
-
0.9
-
0.9
-
mA
VO = 1.5 V
15 V
4.2
-
3.4
-
2.4
-
2.4
-
mA
15 V
-
0.1
-
0.1
-
1.0
-
1.0
A
5V
-
5
-
5
-
150
-
150
A
10 V
-
10
-
10
-
300
-
300
A
15 V
-
20
-
20
-
600
-
600
A
-
-
-
-
7.5
-
-
-
-
pF
II
input leakage
current
IDD
supply current IO = 0 A;
VI = VSS or VDD
CI
VDD
input
capacitance
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V; for test circuit see Figure 10
Symbol Parameter
tPHL
HIGH to LOW
propagation delay
Extrapolation formula[1]
Min
Typ
Max Unit
CP0, CP1  Q0 to Q9; 5 V
see Figure 7
10 V
113 ns + (0.55 ns/pF)CL
-
140
280
44 ns + (0.23 ns/pF)CL
-
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
118 ns + (0.55 ns/pF)CL
-
145
290
ns
10 V
44 ns + (0.23 ns/pF)CL
-
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
88 ns + (0.55 ns/pF)CL
-
115
230
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
27 ns + (0.16 ns/pF)CL
-
35
70
ns
CP0, CP1  Q0 to Q9; 5 V
see Figure 7
10 V
98 ns + (0.55 ns/pF)CL
-
125
250
ns
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
98 ns + (0.55 ns/pF)CL
-
125
250
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
83 ns + (0.55 ns/pF)CL
-
110
220
ns
10 V
34 ns + (0.23 ns/pF)CL
-
45
90
ns
15 V
27 ns + (0.16 ns/pF)CL
-
35
70
ns
5V
103 ns + (0.55 ns/pF)CL
-
130
260
ns
10 V
44 ns + (0.23 ns/pF)CL
-
55
105
ns
32 ns + (0.16 ns/pF)CL
-
40
75
ns
Conditions
CP0, CP1  Q5-9;
see Figure 7
MR  Q1 to Q9;
see Figure 8
tPLH
LOW to HIGH
propagation delay
CP0, CP1  Q5-9;
see Figure 7
MR  Q5-9;
see Figure 8
MR  Q0;
see Figure 8
VDD
15 V
tt
th
transition time
hold time
see Figure 7
CP0  CP1;
see Figure 9
CP1  CP0;
see Figure 9
HEF4017B_Q100
Product data sheet
5V
[2]
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
5V
90
45
-
ns
10 V
40
20
-
ns
15 V
20
10
-
ns
5V
80
40
-
ns
10 V
40
20
-
ns
15 V
30
10
-
ns
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Rev. 1 — 4 June 2014
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HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
Table 7.
Dynamic characteristics …continued
Tamb = 25 C; VSS = 0 V; for test circuit see Figure 10
Symbol Parameter
Conditions
tW
CP0 input LOW;
minimum width;
see Figure 8
pulse width
recovery time
trec
maximum
frequency
fmax
VDD
Extrapolation formula[1]
Min
Typ
Max Unit
5V
80
40
-
ns
10 V
40
20
-
ns
15 V
30
15
-
ns
CP1 input HIGH;
minimum width;
see Figure 8
5V
80
40
-
ns
10 V
40
20
-
ns
15 V
30
15
-
ns
MR input HIGH;
minimum width;
see Figure 8
5V
50
25
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
60
30
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
6
12
-
MHz
10 V
12
30
-
MHz
15 V
15
30
-
MHz
MR input;
see Figure 8
see Figure 8
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
tt is the same as tTHL and tTLH.
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
5V
Typical formula for PD (W)
PD = 500  fi + (fo  CL)  VDD
where:
2
fi = input frequency in MHz;
10 V
PD = 2200  fi + (fo  CL)  VDD2
fo = output frequency in MHz;
15 V
PD = 6000  fi + (fo  CL)  VDD
CL = output load capacitance in pF;
2
VDD = supply voltage in V;
(CL  fo) = sum of the outputs.
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
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HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
11. Waveforms
VI
CP0 input
VM
VSS
VI
CP1 input
VM
VSS
tPHL
tPLH
VOH
Q1 - Q9
output
VM
VOL
tPLH
tPHL
VOH
Q0, Q5 - Q9
output
VOL
VM
tTLH
tTHL
001aaj305
Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. CP1 triggers on a HIGH-to-LOW transition;
The shaded areas indicate where the output state is set by the input count.
Measurement points given in Table 9.
Fig 7.
Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition
times
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
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10 of 18
HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
1/f max
tW
VI
CP0 input
VM
VSS
1/f max
VI
CP1 input
VM
VSS
tW
trec
VI
MR input
VM
VSS
tW
VOH
Q1 - Q9
output
VM
VOL
tPHL
VOH
Q0, Q5 - Q9
output
VOL
VM
001aaj306
tPLH
Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, tW and trec are measured when CP0 = HIGH and
CP1 triggers on a HIGH-to-LOW transition.
The shaded areas indicate where the output state is set by the input count.
Measurement points given in Table 9.
Fig 8.
Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for
CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
VI
CP0 input
VM
VSS
VM
th
th
VI
CP1 input
VM
VM
VSS
001aae578
Hold times are shown as positive values, but may be specified as negative values;
Measurement points given in Table 9.
Fig 9.
Waveforms showing hold times for CP0 to CP1 and CP1 to CP0
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
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HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
tW
VI
90 %
90 %
negative
pulse
VM
VM
10 %
0V
VI
10 %
tf
tr
tr
tf
90 %
positive
pulse
90 %
VM
VM
10 %
0V
10 %
tW
001aaj781
a. Input waveforms
VDD
VI
VO
G
DUT
CL
RT
001aag182
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test;
CL = load capacitance including jig and probe capacitance;
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 10. Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
 20 ns
50 pF
HEF4017B_Q100
Product data sheet
Load
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Rev. 1 — 4 June 2014
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HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
12. Application information
Some examples of applications for the HEF4017B-Q100 are:
•
•
•
•
Decade counter with decimal decoding
1 out of n decoding counter (when cascaded)
Sequential controller
Timer
Figure 11 shows a technique for extending the number of decoded output states for the
HEF4017B-Q100. Decoded outputs are sequential within each stage and from stage to
stage, with no dead time (except propagation delay).
CP0
MR
CP0
HEF4017B
CP1
Q0 Q1- - - - Q8 Q9
clock
MR
HEF4017B
CP1
Q0 Q1- - - - Q8 Q9
CP0
MR
HEF4017B
CP1
Q1 - - - - - - Q8 Q9
9 decoded
outputs
8 decoded
outputs
8 decoded
outputs
first stage
intermediate stages
last stage
001aae577
Enabling the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, causes an extra count.
Fig 11. Counter expansion
HEF4017B_Q100
Product data sheet
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Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 18
HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 12. Package outline SOT109-1 (SO16)
HEF4017B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4017B_Q100 v.1
20140604
Product data sheet
-
-
HEF4017B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4017B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4017B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application information. . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 June 2014
Document identifier: HEF4017B_Q100