ISL55141, ISL55142, ISL55143 Evaluation Board User’s Manual ® Application Note September 27, 2006 AN1270.0 Before Getting Started VEE PD QA QB VOL VOH CVB VINP CVA VCC VEE 14 12 11 10 9 8 ISL55141_TSSOP FIGURE 1. THERE ARE NO GROUND PINS ON THESE COMPARATORS. VEE ALWAYS PROVIDES THE MOST NEGATIVE POWER CONNECTION. JP01 VOL = VEE VEE 2 VOL GND 2 TP04_VCC_VEE VCC C4 C3 +4.7µF 0.1µF DIF-- JP02 JP03 VOL = GND VEE = GND DIF+ 1 VOL 1 No voltage should be greater than VCC or less than VEE. Also, VOH must be greater than VOL. Since there are so many variations of use, each evaluation board provides three jumpers relating to basic power strapping. 4 5 6 7 2 Take time to review the ISL55141, ISL55142, ISL55143 Data Sheet (FN6230) and become familiar with the part’s basic functions and power options. Note also that FN6230 super cedes this document with respect to updates and modifications. Always refer to that document if discrepancies occur. 1 1 This document supplements the ISL55141, ISL55142, ISL55143 specification FN6230. Evaluation board users should review that document to obtain information on the part’s basic functionality and power requirements. A most important note is before powering up the board, review the Power-up Sequence in that specification. There are many DC sources utilized, therefore a user may inadvertently mis-apply the power sources causing damage to the part. VEE GND All ISL55141, ISL55142, ISL55143 boards are designed essentially in the same fashion. This document provides the user with the information regarding the evaluation board design, circuitry layout and jumper options. GND - Banana Jack VCC - Banana Jack VEE - Banana Jack VOH TP03-VOH_VOL Jumper Options - VEE, VOL and GND First, VEE can be negative with respect to ground for receiving negative input ranges on the VINPs (comparator Inputs). The comparator outputs QA, QB toggle between VOH and VOL. VOL could also be a negative voltage, although this is usually not the case. VOL should never be more negative than VEE. For single supply operations, the user may wish to connect VEE to ground and VOL as well. Therefore, on each evaluation board there are positions for three jumpers (JP01, JP02, JP03). The user should make note that the ISL55141, ISL55142, ISL55143 all operate with VEE as the negative reference. There are no actual ground connection to the comparators unless VEE itself is connected to ground. VOL - Banana Jack VOH - Banana Jack DIF+ C1 C2 +4.7µF 0.1µF DIF-VOL FIGURE 2. THREE JUMPERS ARE AVAILABLE TO SET USER POWER STRAPPING OPTIONS. Before beginning the evaluation, the user should determine the desired relationship between GND, VEE and VOL. JP01 Connects VOL to VEE Both VEE and VOL voltage busses are negative with respect to ground. Comparator receives negative inputs and translates the QA/QB outputs with a negative low voltage. JP02 Connects VOL to GND VOL low is connected to ground, VEE is negative with respect to ground. Comparator inputs operate below ground but QA/QB level translation in reference to ground. JP03 Connects VEE to GND Both VOL and VEE are referenced to ground. There are no negative voltage requirements with respect to Comparator Inputs or level translation on the QA/QB Outputs 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1270 Scope Probe Connections QA_J3 Another topic to cover before getting started is the evaluation board physical connections for waveform observations. On each schematic version you will see a component with pins designated as DIF+ and DIF-. This is not an active component but a dual pin header physically design to accommodate connection of active differential probes. This will minimize ground lead inductance and capacitive loading while make waveform observations. However, the user must also be mindful of max voltage limitations when using these types of probes. The ISL5514x comparators cover a large voltage range, so double check the probe’s specifications. SCOPE PROBE CONNECTIONS QA0 TP01-QA_VOL DIF+ R1 50Ω VOL QB_J4 QB0 1 DIF-- TP02-QB_VOL QA0 QB0 VOL VOH DIF+ R2 50Ω CVB VINP CVA VCC VEE 12 11 10 9 8 ISL55141_TSSOP TP07-VINP QA0 R20 NOT POPULATED GND TP01-QA_VOL R1 50Ω VOL DIF+ PD DIF-- CVB VINP CVA VCC VEE R14 0Ω R18 0Ω VINP_J8 R20 NOT POPULATED GND GND FIGURE 3. DUAL1” SPACED PINS ARE PLACED ON THE EVALUATION BOARDS FOR DIFFERENTIAL PROBE CONNECTIONS Scope probe test points (TP) are positioned across all inputs, outputs and VCC and VEE. BNC Connections This series of evaluation boards also provides BNC connections for input and output signals. A key point to remember is the ISL55141, ISL55142, ISL55143 comparator outputs (QA/QB) operate with the VOH voltage as a High and VOL voltage as a Low. QA/QB BNC’s, which are connected to the outputs, have the shield connected to the VOL voltage bus. Keep this in mind when making BNC connections to avoid connecting the GND shield of the BNC inputs to the VOL shield of the BNC outputs. Also note that the comparator outputs have 50Ω terminations that you may need to remove for your application. GND 14 12 11 10 9 8 VINP_J8 R14 0Ω R18 0Ω DIF-- DIF-- QA QB VOL VOH VINP DIF+ DIF+ 14 FIGURE 4. BNC CONNECTIONS ON THE QA/QB COMPARATOR OUTPUTS HAVE THE SHIELD CONNECTED TO THE VOL BUS. NOTE: YOU MAY WISH TO REMOVE THE 50Ω TERMINATIONS. DIF-- TP07-VINP PD DIF-- VOL DIF+ QA_J3 4 5 6 7 VEE CVB_BUS CVA_BUS VCC VEE VINP _TSSOP FIGURE 5. BNC CONNECTIONS ON THE HIGH SPEED VINP PINS HAVE THE SHIELD CONNECTED TO GND. NOTE: TWO SMD SERIES POSITIONS PLUS ONE POSITION TO GROUND ARE AVAILABLE FOR USER SPECIFIC CIRCUITRY. Power-Down Feature All boards provide the same capability for testing the power-down feature. A SPDT- center OFF switch is provided for manual testing of the feature. In one position the PD input is connected to VCC (Power-down enabled). In the other position the PD Input is connected to VEE (power-down disabled). S1 - POWER-DOWN CONTROL SPDT - CENTER OFF VDD VEE PD - BN_J5 PD GND 1 4 5 6 7 VEE PD 14 QA QB VOL VOH CVB VINP CVA VCC VEE 12 11 10 9 8 ISL55141_TSSOP FIGURE 6. ALL ISL5514X EVALUATION BOARDS HAVE THE SAME POWER-DOWN CIRCUITRY. 2 AN1270.0 September 27, 2006 Application Note 1270 Finally the center off position provides a means of connecting a repetitive signal source to the PD input. This is so the user can observe power-down enable/disable timing. An important note to remember when using the PD - BNC: 1. Place the switch in center-off position. 2. The PD input is referenced to VCC/VEE. The low amplitude of the PD input must match the VEE voltage. The high amplitude must be close to VCC. Comparator Threshold Rails 28 CVB0 VINP0 CVA0 CVB1 VINP1 CVA1 CVB2 VINP2 CVA2 QA0 QB0 QA1 QB1 QA2 QB2 QA3 QB3 CVB_BUS 27 26 25 24 23 22 21 20 Once static observations check out, you can then increase power current limits for VCC/VEE and VOH/VOL and apply higher frequency inputs to the VINP pins. Layout Information All evaluation boards have complete silk-screen information regarding test points, jumpers and component placements. The silk-screen on the board you receive will provide up-to-date layout information. Included in the following pages are three schematics. ISL55141 single comparator device, ISL55142 dual comparator and ISL55143 quad comparator device. The Evaluation boards are laid out for the TSSOP packages for the ISL55141 and ISL55142, while the ISL55143 is the QFN package. Please refer to the device specification for part numbers/options for these and other package ordering. 19 CVA_BUS FIGURE 7. ISL55142 AND ISL55143 COMPARATOR THRESHOLD CVA/CVB INPUTS ARE TIED TOGETHER TO EITHER THE CVA_BUS OR CVB_BUS. 3 When first powering up the device, set all power bus inputs to minimum current levels needed for quiescent operation. Check the device out statically with DC inputs on the VINP pins and observe that the QA/QB outputs toggle when the VINP voltage crosses the CVA and CVB thresholds. Schematics are drawn with physical location in mind. Any changes in electrical circuitry will be updated in this document as needed. 10 11 12 13 14 15 16 17 18 ISL55143_QFN Please refer to the device specification for power-up sequencing and current requirements. Also note that the frequency of operation and number of comparators will determine the current needed. There are graphs in the specification regarding current characteristics. Schematic Information VOH VOL VOH VOL VEE VCC CVA3 VINP3 CVB3 2 3 4 5 6 7 8 9 PD VCC VEE VCC VEE 34 33 32 31 Each comparator has two thresholds. CVA/CVB. The data sheet explains the operation of these analog inputs. However, it should be mentioned that while the ISL55142 (Dual) and ISL55143 (QUAD) comparators have separate threshold inputs for each comparator, the evaluation boards have all CVA inputs tied to single CVA_BUS. Accordingly, all CVB inputs are tied to a single CVB_BUS. Initial Power-Up Bill of Material A bill of material of the ISL55142 evaluation board is included on page 6. It provides sources for special components such as the BNC connectors and banana jacks. All other parts are QPL standard passive components. Refer to device specification (FN6230) when ordering replacements for actual ISL55141, ISL55142 or ISL55143 devices. AN1270.0 September 27, 2006 Application Note 1270 ISL55142IVZ Evaluation Board Schematic S1 - POWER-DOWN CONTROL SPDT - CENTER OFF VDD VEE VINP PD - BN_J5 TP07-VINP DIF+ PD R20 NOT POPULATED GND DIF-- R1 50Ω VOL QB_J4 QB0 R2 50Ω VOL TP01-QA_VOL GND DIF+ 1 DIF-- 4 5 6 7 TP02-QB_VOL DIF+ VEE QA QB VOL VOH CVB_BUS TP06_CVB 14 PD 12 CVB_BUS 11 10 CVA_BUS VCC 9 8 VEE CVB VINP CVA VCC VEE VINP DIF-- C7 +4.7µF J9-CVB - Banana Jack GND J10-GND - Banana Jack C8 +4.7µF J11-CVA - Banana Jack GND CVA_BUS VOL GND GND TP04_VCC_VEE VCC C4 +4.7µF C3 0.1µF GND 2 1 VOL 1 JP02 JP03 VOL = GND VEE = GND DIF-- C6 0.1µF 2 1 DIF+ 2 C1 C2 +4.7µF 0.1µF DIF-- VEE VOL TP03-VOH_VOL CVA_BUS DIF+ JP01 VOL = VEE VOH VOH - Banana Jack C5 0.1µF ISL55141_TSSOP DIF-- TP05_CVA VOL - Banana Jack CVB_BUS DIF+ DIF-- QA0 DIF+ QA_J3 VINP_J8 R14 0Ω R18 0Ω VEE GND GND - Banana Jack VCC - Banana Jack VEE - Banana Jack FIGURE 8. ISL55141IVZ TSSOP SINGLE COMPARATOR EVALUATION BOARD SCHEMATIC 4 AN1270.0 September 27, 2006 ISL55142IVZ Evaluation Board Schematic S1 - POWER-DOWN CONTROL SPDT - CENTER OFF VINP0_J8 VINP0 R14 0Ω R18 0Ω VEE VDD VINP1 PD - BN_J5 TP10-VINP0 R20 NOT POPULATED GND TP07-VINP1 DIF+ R9 NOT POPULATED DIF+ PD DIF-GND GND DIF-- GND VINP1_J14 R10 0Ω R8 0Ω GND 5 CVA_BUS TP01-QA0_VOL DIF-- VOL QB0 R2 50Ω CVB1 VINP1 CVA1 20 19 18 CVB_BUS VCC VEE 16 15 VCC VEE QB1 QA1 12 11 VOL JP02 VOL = GND DIF+ R7 50Ω VINP1 DIF-QB1 QA1 TP09-QA1_VOL ISL55142IVZ_TSSOP JP01 VOL = VEE VEE DIF+ DIF-- . CVB0 VINP0 CVA0 PD VEE VCC VOH VOL QA0 QB0 1 VOL QA0 QB0 TP02-QB0_VOL VEE VCC VOH VOL 1 2 3 4 5 6 7 8 9 10 QB1 DIF+ DIF-- JP03 VEE = GND TP04_VCC_VEE VCC C4 C3 C9 +4.7µF 0.1µF 0.1µF TP03-VOH_VOL C2 C1 +4.7µF 0.1µF DIF+ GND 2 1 2 1 VOL VEE QA1 QA1_J12 R6 50Ω VOL CVB_BUS TP06_CVB CVB_BUS C5 0.1µF DIF-- C7 + 4.7µF J9-CVB - Banana Jack GND GND DIF-VOH - Banana Jack VOL DIF+ VOH VOL - Banana Jack QB1_J13 GND J10-GND - Banana Jack C8 +4.7µF J11-CVA - Banana Jack CVA_BUS VOL TP05_CVA DIF+ GND - Banana Jack VCC - Banana Jack VEE - Banana Jack CVA_BUS C6 0.1µF DIF-GND GND FIGURE 9. ISL55142IVZ TSSOP DUAL COMPARATOR EVALUATION BOARD Application Note 1270 QB0_J4 VINP0 TP10-QB1_VOL DIF-- DIF+ R1 50Ω DIF+ QA0 2 QA0_J3 AN1270.0 September 27, 2006 Application Note 1270 ISL5514x Bill of Materials QTY REF DES 7 J3-J5, J8, J12-J14 2 J7, J10 1 DESCRIPTION 50Ω PCB mount receptacle PART NUMBER 31-5329-52RFX MANUFACTURER AMPHENOL Right angle PCB mount insulated socket - single (black) 571-0100 DELTRON J1 Right angle PCB mount insulated socket - single (blue) 571-0200 DELTRON 1 J20 Right angle PCB mount insulated socket - single (brown) 571-0300 DELTRON 1 J2 Right angle PCB mount insulated socket - single (green) 571-0400 DELTRON 1 J6 Right angle PCB mount insulated socket - single (red) 571-0500 DELTRON 1 J9 Right angle PCB mount insulated socket - single (white) 571-0600 DELTRON 1 J11 Right angle PCB mount insulated socket - single (yellow) 571-0700 DELTRON 2 C5, C6 Multilayer cap C1608X7R1H104K TDK 1 S1 Sealed subminiature toggle switch ET03SD1CBE ITT CANNON-C&K 3 C2, C3, C9 Multilayer cap H1045-00104-25V10 GENERIC 4 C1, C4, C7, C8 Multilayer cap H1065-004R7-50VR25 GENERIC 4 R3, R5, R8, R10 Thick film chip resistor H2511-00R00-1/16W1 GENERIC 4 R1, R2, R6, R7 Thick film chip resistor H2513-049R9-1/8W1 GENERIC 2 R4, R9 Thick film chip resistor (do not populate) H2513-DNP-DNP-1 GENERIC 1 U1 High-speed CMOS window comparators (Pb-free) ISL55142ARZ INTERSIL JUMPER2_100 GENERIC 13 JP01-JP03, TP01-TP010 Two-pin jumper 6 AN1270.0 September 27, 2006 Application Note 1270 ISL55143IRZ Evaluation Board Schematic VINP0 QA0_J3 QA0 TP01-QA0_VOL TP10-VINP0 DIF+ DIF+ DIF-- DIF-- R1 50Ω R18 0Ω VINP0_J16 R14 0Ω R20 NOT POPULATED GND VINP1 QB0_J4 QB0 TP02-QB0_VOL TP10-VINP1 S1 - POWER-DOWN CONTROL SPDT - CENTER OFF DIF+ R2 50Ω DIF-- VEE VDD GND DIF+ PD - BN_J5 VINP1_J15 R10 0Ω R8 0Ω R9 NOT POPULATED DIF-- GND VINP2 TP03-QA1_VOL R12 50Ω DIF+ TP10-VINP2 GND DIF-- QB0 DIF-- QA1 2 3 4 5 6 7 8 9 QB1 QA2 TP05-QA3_VOL QB2 DIF+ R11 50Ω QB2_J21 QA2 QB2 QB3 TP06-QB2_VOL ISL55143_QFN VOH CVB_BUS 27 26 25 24 23 22 21 20 19 VINP1 QB3_J13 TP16_CVB CVB_BUS C5 0.1µF C7 +4.7µF J9-CVB - Banana Jack GND TP15_CVA DIF+ DIF-- GND J10-GND - Banana Jack 2 GND CVA_BUS C6 0.1µF C8 +4.7µF J11-CVA - Banana Jack GND 2 JP03 VEE = GND 1 1 VOL JP02 VOL = GND 2 DIF-- R7 50Ω GND CVA_BUS VINP3 DIF+ QB3 R4 NOT POPULATED GND DIF-- DIF-- DIF-- TP07-QA3_VOL R6 50Ω VINP3_J8 R5 0Ω CVA_BUS 1 QA3 DIF+ DIF+ JP01 VOL = VEE QA3_J12 GND R3 0Ω CVB_BUS VINP2 VCC DIF+ R15 50Ω 28 QA0 QB0 QA1 QB1 QA2 QB2 QA3 QB3 QA3 DIF-- CVB0 VINP0 CVA0 CVB1 VINP1 CVA1 CVB2 VINP2 CVA2 VINP3 TP10-VINP3 VOH VOL VOH VOL VEE VCC CVA3 VINP3 CVB3 QA2_J17 VINP0 PD VCC VEE VCC VEE QA0 DIF+ R16 50Ω 34 33 32 31 TP05-QB1_VOL 10 11 12 13 14 15 16 17 18 QB1 C9 NOT POPULATED GND DIF-- VEE QB1_J21 DIF+ VCC VINP2_J14 R6 0Ω R4 0Ω TP01_VCC_VEE VCC C3 C4 C9 +4.7µF 0.1µF 0.1µF GND DIF-- QA1 DIF+ QA1_J18 GND VEE TP08-QB3_VOL GND VOH DIF+ DIF-- TP03-VOH_VOL VOL - Banana Jack C1 C2 +4.7µF 0.1µF DIF+ DIF-- VOH - Banana Jack GND - Banana Jack VCC - Banana Jack VEE - Banana Jack VOL FIGURE 10. ISL55143IRZ QFN QUAD COMPARATOR EVALUATION BOARD Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 7 AN1270.0 September 27, 2006