SEMTECH E818AHF

Edge818
Octal 18V Pin Electronics
Driver/window Comparator
TEST AND MEASUREMENT PRODUCTS
Description
Features
•
•
•
•
•
•
•
The Edge818 is an octal pin electronics driver and window
comparator fabricated in a wide voltage CMOS process.
It is designed specifically for Test During Burn In (TDBI)
applications, where cost, functional density, and power
are all at a premium.
The Edge818 incorporates eight channels of programmable
drivers and window comparators into one 14 mm X 20
mm 100 pin MQFP package. Each channel has per pin
driver levels, data, and high impedance control. In addition,
each comparator has per pin high and low threshold levels.
18V I/O Range
50 MHz Operation
Per Pin Flexibility
Programmable Input Thresholds
Flex In Digital Inputs
Flex Out Digital Outputs
Small footprint (100 pin MQFP)
Applications
The Edge818 uses "Flex In" and "Flex Out" digital inputs,
and can therefore mate directly with any digital technology
providing a minimum 2V swing. The digital outputs can
mate directly with any digital technology.
• Burn In ATE
• Low Cost ATE
• Instrumentation
The 18V driver output and receiver input range allow the
Edge818 to interface directly with TTL, ECL, CMOS (3V,
5V, and 7V), LVCMOS, and custom level circuitry, as well
as the high voltage (Super Voltage) level required for many
special test modes for Flash Devices.
Functional Block Diagram
VH VL
DATA
EN*
QA
8
8
8
–
+
8
COMP HIGH
8
8
DOUT
CVA
VINP
COMP LOW
QB
Revision 5 / August 18, 2004
8
+
–
1
8
CVB
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
PIN Description
Pin Name
Pin Number
DATA (0:7)
100, 4, 8, 12, 19, 23, 27, 31
Digital inputs which determine the high/low state of the
driver, when it is enabled.
EN* (0:7)
3, 7, 11, 15, 16, 20, 24, 28
Digital inputs wihch enable/disable the driver.
QA (0:7)
QB (0:7)
1, 5, 9, 13, 18, 22, 26, 30
2, 6, 10, 14, 17, 21, 25, 29
Comparator digital outputs.
DOUT (0:7)
79, 75, 71, 67, 64, 60, 56, 52
Driver Outputs.
VINP (0:7)
81, 77, 73, 69, 62, 58, 54, 50
Comparator Inputs.
VH (0:7)
80, 76, 72, 68, 63, 59, 55, 51
Unbuffered analog inputs that set the driver "high" voltage
level.
VL (0:7)
78, 74, 70, 66, 65, 61, 57, 53
Unbuffered analog inputs that set the driver "low" voltage
level.
CVA (0:7)
97, 95, 89, 87, 44, 42, 36, 34
Analog inputs that set the threshold for the A comparators.
CVB (0:7)
96, 94, 88, 86, 45, 43, 37, 35
Analog inputs that set the threshold for the B comparators.
VBB
46, 85
Analog input voltage that sets the threshold for the digital
inputs.
COMP HIGH
33, 98
Unbuffered analog input that sets the high level of the
comparator outputs.
COMP LOW
32, 99
Unbuffered analog input that sets the low level of the
comparator outputs.
VCC
40, 41, 47, 49, 82, 84, 90, 91
Positive power supply.
VEE
38, 39, 48, 83, 92, 93
Negative power supply.
 2004 Semtech Corp. / Rev. 5, 8/18/04
Description
2
www .semtech.com
Edge818
VINP0
VCC
VEE
VCC
VBB
CVB3
CVA3
CVB2
CVA2
VCC
VCC
VEE
VEE
CVB1
CVA1
CVB0
CVA0
COMP HIGH
COMP LOW
DATA0
TEST AND MEASUREMENT PRODUCTS
PIN Description (continued)
81
QA0
1
VH0
DOUT0
QB0
VL0
EN*0
VINP1
DATA1
QA1
VH1
QB1
DOUT1
VL1
EN*1
VINP2
DATA2
QA2
VH2
QB2
DOUT2
VL2
EN*2
VINP3
DATA3
QA3
VH3
QB3
DOUT3
EN*3
VL3
100 Lead - 14 x 20 MQFP
EN*4
VL4
QB4
DOUT4
QA4
VH4
VINP4
DATA4
VL5
EN*5
QB5
DOUT5
QA5
VH5
VINP5
DATA5
VL6
EN*6
QB6
DOUT6
QA6
VH6
VINP6
DATA6
VL7
EN*7
DOUT7
QB7
51
QA7
VH7
 2004 Semtech Corp. / Rev. 5, 8/18/04
3
VCC
VINP7
VEE
VBB
VCC
CVA4
CVB4
CVB5
VCC
CVA5
VEE
VCC
VEE
CVA6
CVB6
CVA7
CVB7
COMP HIGH
DATA7
COMP LOW
31
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Circuit Description
VH
Driver Description
The Edge818 supports programmable high and low levels
and tristate per channel. There are no shared lines
between any drivers. The EN* and DATA signals are wide
voltage high impedance analog inputs capable of receiving
digital signals over a wide common mode range. VBB is
the high impedance analog input which sets the threshold
for EN* and DATA.
DUT
VL
EN*, DATA
> VBB
< VBB
Status
"1"
"0"
Figure 1. Simplified Model of the
Unbuffered Output Stage
With EN* high, the driver goes into a high impedance state.
With EN* low, DATA high forces the driver into a high state,
and DATA low forces the driver into a low state.
EN*
1
0
0
DATA
X
1
0
DOUT
HiZ
VH
VL
VH and VL define the logical "1" and "0" levels of the driver,
and can be adjusted anywhere over the range determined
by VCC and VEE. There are no restrictions between VH
and VL, other than they must remain within the power
supply levels.
VH ≤ VCC
VL ≤ VCC
The VH and VL inputs are unbuffered in that they also
provide the driver output current (see Figure 1), so the
source of VH and VL must have ample current drive
capability.
 2004 Semtech Corp. / Rev. 5, 8/18/04
In a functional testing environment, where a resistor is
added in series with the driver output to create a 50Ω
driver, the Edge818 can withstand a short to any legal
voltage for an indefinite amount of time.
In a low impedance application, with no additional output
resistance, the system should be designed to check for a
short circuit prior to connecting the driver, and tristate the
driver if a short is detected.
Drive High and Low
VEE ≤
VEE ≤
Driver Output Protection
4
Receiver Description
The Edge818 supports a window comparator with
independent threshold levels per channel. There are no
shared comparator lines between channels. CVA and CVB
are high impedance analog voltage inputs which define
the threshold voltages for comparators A and B.
If VINP is more positive than CVA or CVB, QA and QB will
be high. Otherwise, QA and QB will be low.
VINP
VINP > CVA
VINP < CVA
QA
COMP HIGH
COMP LOW
VINP
VINP > CVB
VINP < CVB
QB
COMP HIGH
COMP LOW
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
The comparator outputs are "Flex Out". They are technology
independent and may be adjusted over a wide voltage
common mode range. COMP HIGH and COMP LOW are
analog inputs which set the digital high and low levels
(respectively) of QA and QB. COMP HIGH and COMP LOW
are unbuffered inputs that provide the necessary drive
current, so the sources for these levels must have adequate
current capability.
COMP HIGH
QAX, QBX
COMP LOW
Figure 2. Simplified Model of the
Unbuffered Comparator Output Stage
Typically, COMP HIGH and COMP LOW will be connected
to the digital power supplies of the chip receiving QA and
QB.
Receiver Headroom
There is ~3V of headroom required between the
comparator thresholds and both power supply levels.
VEE + 3.0 ≤
CVA, CVB ≤
 2004 Semtech Corp. / Rev. 5, 8/18/04
VCC – 3.0
5
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Application Information
Power Supply Decoupling
VCC and VEE should be decoupled to GND with a .1 µF
chip capacitor in parallel with a .001 µF chip capacitor. A
VCC and VEE plane, or at least a solid power bus, is
recommended for optimal performance.
VH and VL Decoupling
As the VH and VL inputs are unbuffered and supply the
driver output current, which can be quite large during edge
transitions, decoupling capacitors for these inputs are
recommended in proportion to the amount of output
current requirements.
For applications where VH and VL are shared over multiple
channels, a solid power plane to distribute these levels is
preferred.
VBB
The two VBB pins are connected together on-chip.
Therefore, only one VBB needs to be connected to for
proper 818 operation.
The two pins may be used to daisy chain a VBB signal
across a PC Board without having to route the actual signal
underneath the 818.
Power-on Sequencing
1. VCC (substrate)
2. VEE
3. I/O Pins
Power-off Sequencing
1. I/O Pins
2. VEE
3. VCC
The three diode configuration shown in Figure 3 should
be used on a once-per-board basis.
VCC
External
Logic
Supply
VDD
1N5820 or
Equivalent
External
System
Ground
VEE
Figure 3.
Power Supply Protection Scheme
Power Supplies
The Edge818 has several power supply requirements to
protect the part in power supply fault situations, as well
as during power up and power down sequences.
The following power supply requirements must be satisfied
at all times:
VEE ≤ All I/O pins ≤ VCC at all times.
 2004 Semtech Corp. / Rev. 5, 8/18/04
The power sequence below can be used as a guideline
when operating the Edge818:
6
gure 5.
Warning: It is extremely important that the voltage
on any device pin does not exceed the range of VEE
–0.5V to VCC +0.5V at any time, either during power
up, normal operation, or during power down. Failure
to adhere to this requirement could result in latchup
of the device, which could be destructive if the system
power supplies are capable of supplying large
amounts of current. Even if the device is not
immediately destroyed, the cumulative damage
caused by the stress of repeated latchup may affect
device reliability.
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Application Information (continued)
Power Dissipation/Thermal Considerations
The Edge818 is specified to operate with a die junction
temperature, Tj, of up to 125˚C. The theoretical junction
temperature is calculated as follows:
Tj = Tc + θjc x Ptotal
Where Tj
= The Theoretical Junction Temperature
of the Edge818 [˚C]
= The Case Temperature of the
Tc
Edge818[˚C]
θjc
= The Thermal Impedance of the
Edge818 (junction to top center of
case)[˚C]
Ptotal = The Total Power Dissipation of the
Edge818 [W]
In order to maximize the reliability and operating lifetime
of the Edge818, the junction temperature of the device
should be minimized. It can be seen from the equation
above that the junction temperature of the Edge818 is
both a function of its case temperature and the total power
dissipation of the device. Therefore, one can minimize
the junction temperature of the Edge818 by minimizing
the case temperature and the overall power dissipation of
the device.
The case temperature of the Edge818 can be controlled
through the use of some source of external cooling to
regulate the case temperature (i.e. forced air). A heat
sink can also be attached to the Edge818 in order to
maximize the efficiency and increase the overall heat
capacity of the external cooling used in an application.
A heat sink can be attached to the top of the device, and/
or additional cooling can be attained through the bottom
of the device (i.e. into a copper plane on the PCB or a
heat sink attached to the device through a hole in the
PCB). This will significantly decrease the effective thermal
resistance between the case of the Edge818 and the
cooling mechanism being used.
relatively large power savings when using the device is to
minimize the power supply levels that are used for a
particular application. (Note that varying power supply
levels may have an effect on device propagation delays
and driver output impedance.) For illustrative purposes,
this approach to power savings is evaluated on the following
application:
Example:
The Edge818 is used to generate 3.3V output swings
on all 8-channels simultaneously under the following
conditions:
•
•
•
•
VL = 0V
VH = 3.3V
f = 25 MHz
Zload = 1kΩ||80pF
Under the conditions above, the power dissipation of
the Edge818 is as depicted in Table 1.
VCC[V]
VEE[V]
VCC–VEE[V]
Pdiss[W]
Tj[˚C]
12
–3.3
15.3
3.4
77
7.5
–4.6
12.1
2.2
59
Table 1. Comparison of Edge818 Power Dissipation
and Junction Temperature at f = 25 MHz,
Ta = 25 ˚C, Airflow = 300 LFPM
Note that by reducing the power supply levels in the
application depicted above, a power savings of 1.2W
was realized (and Tj was reduced by 18˚C).
The power dissipation (and hence Tj) of the Edge818 is
directly proportional to its operating frequency. This is
illustrated in Figures 4 and 5.
The total power dissipation of the Edge818 can also be
minimized, but is ultimately dependent upon the
requirements of the application. One way to attain a
 2004 Semtech Corp. / Rev. 5, 8/18/04
7
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Application Information (continued)
Edge 818AHF Power Dissipation vs. Frequency
4.00
3.50
3.00
2.50
A/L B057
A/L B076
2.00
A/L 2131
1.50
1.00
0.50
0.00
0
5
10
15
20
25
30
Frequency [Mhz]
Figure 4. Edge818 Power Dissipation vs. Operating Frequency
(VCC = 12V, VEE = –3.3V, VH = 3.3V, VL = 0V, Zload = 1KΩ\\80pF, Ta = 25˚C,
Airflow = 300 LFPM, All 8 Driver Channels Toggled)
Edge 818 AHF Junction Temperature vs. Operating Frequency
90
Junction Temperature, Tj [Deg. C]
80
70
60
50
A/L B057
A/L B076
A/L 2131
40
30
20
10
0
0
5
10
15
20
25
30
Frequency [MHz]
Figure 5. Edge818 Junction Temperature vs. Operating Frequency
(VCC = 12V, VEE = –3.3V, VH = 3.3V, VL = 0V, Zload = 1KΩ||80pF, Ta = 25˚C,
Airflow = 300 LFPM, All 8 Driver Channels Toggled)
 2004 Semtech Corp. / Rev. 5, 8/18/04
8
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Application Information (continued)
Therefore, the per-channel power dissipation due to the
Edge818 driving and resistive load is:
Driving a Resistive Load
In addition to the VCC and VEE power supply levels, the
“driver high” (VH) and “driver low” (VL) levels used in an
application also have an effect on the total power
dissipation of the device illustrated using Figure 6.
External "Driver High" Buffer
VH
Rds(H)
Simplified
Edge818
Output
Stage
H
IL
DOUT
L
RT
Rds(L)
P = [IL(H) x Rds(H) x D + IL(L)] x [Rds(L) x (1–D)]
where
P
= The total power dissipated by the Edge818
as a result of the resistive load, RL [W]
IL(H) = The amount of current required by RL
during a logic “high” state [A]
Rds(H) = The output impedance of the Edge818
driver when driving a logic “high” state [Ω]
D
= The normalized amount of time that logic
“high” is driven (Duty Cycle)
IL(L) = The amount of current required by RL
during a logic “low” state [A]
Rds(L) = The output impedance of the Edge818
driver when driving a logic “low” state [Ω]
VT
VL
External "Driver Low" Buffer
Figure 6. Simplified Functional Schematic of Edge818
Output Stage and External Buffers
The CMOS switches of the Edge818’s output stage have
on-resistance values (depicted by Rds(H) and Rds(L) in
Figure 6) that vary as a function of VH and VL voltage
levels. The amount of current required by the load
impedance, RT, is also a function of the VH and VL voltage
levels as follows:
Switch in Figure 6 is in position “H”:
IL(H) =
VH – VT
Rds(H) + RT
Switch in Figure 6 is in position “L”:
IL(L) =
VL – VT
Rds(L) + RT
 2004 Semtech Corp. / Rev. 5, 8/18/04
9
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Package Information
100-Pin MQFP
14 mm x 20 mm
4
PIN Descriptions
0.25
4X
C
A–B
D
D
D2
Z
3
D
3
–D–
–A–
–B–
3
E2
–E–
4
e
Z
SEE DETAIL "A"
E
TOP VIEW
2
4X
5
7
0.20
C
A–B
D
5
7
D1
7
E1
O
O
C
5
BOTTOM VIEW
 2004 Semtech Corp. / Rev. 5, 8/18/04
10
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Package Information (continued)
0.40 MIN.
'
˚'
0 MIN.
e/2
A2
–' 0.10 S
0.13 / 0.30 R. TYP.
–A, B, D–
0.13'
R. MIN.
3
GAGE '
PLANE
C
C
A1
DETAIL "A"
BASE'
PLANE
0.25
L
˚'
0–7
1.60 REF.
SEATING'
PLANE
DETAIL "B"
˚
12 – 16
ccc
8
SEE DETAIL "B"
A
1.28 REF.
C A–B S D S
WITH LEAD FINISH
B
–H–
M
2
0.076
12
0.13 / 0.17
0.13 / 0.23
–C–
˚
12 – 16
B
1
BASE METAL
SECTION C–C
Variations
(all dimensions in millimeters)
Notes:
1. All dimensions and tolerances conform to ANSI Y14.5-1982.
2. Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
3. Datums A-B and -D- to be determined where centerline between
leads exits plastic body at datum plane -H-.
4. To be determined at seating plane -C-.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254 mm per side. Dimensions
D1 and E1 do include mold mismatch and are determined at
datum plane -H-.
6. “N” is the total # of terminals.
7. Package top dimensions are smaller than bottom dimensions
and top of package will not overhang bottom of package.
8. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm total in excess of the
dimension at maximum material condition. Dambar cannot
be located on the lowerradius or the foot.
9. All dimensions are in millimeters.
10. Maximum allowable die thickness to be assembled in this
package family is 0.635 millimeters.
11. This drawing conforms to JEDEC registered outlines MS-108
and MS-022.
12. These dimensions apply to the flat section of the lead between
0.10 mm and 0.25 mm from the lead tip.
 2004 Semtech Corp. / Rev. 5, 8/18/04
Symbol
Min
A
A1
0.25
A2
2.57
Max
3.40
Note
0.33
2.71
Comments
Height above PCB
Gap above PCB
2.87
Body Thickness
D
23.20 BSC
4
D1
20.00 BSC
5
D2
18.85 REF
ZD
0.58 REF
Body Dimension
E
17.20
4
E1
14.00 BSC
5
Body Dimension
E2
12.35 REF
6
Pin Count
ZE
L
0.83 REF
0.73
N
0.88
1.03
100
e
11
Nom
3.04
0.65 BSC
B
0.22
B1
0.22
Lead Pitch
0.38
0.30
0.33
8
Pad Dimension
Pad Dimension
ccc
0.13
ND
30
Side Pin Count
NE
20
Side Pin Count
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Recommended Operating Conditions
Parameter
Total Analog Supply
Symbol
Min
VCC - VEE
12.0
Typ
Max
Units
18.0
V
Ambient Operating Temperature
TA
+70
oC
Junction Temperature
TJ
+125
oC
Thermal Resistance of Package
(Junction to Still Air)
θJA
32.2
oC/W
Thermal Resistance of Package
(Junction to Case)
θJC
12.4
oC/W
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Total Power Supply
VCC - VEE
-0.5
19.0
V
Digital Input Voltages
DATA, EN*
VEE - .5
VCC + .5
V
Analog Input Voltages
VH, VL, CVA, CVB, VINP, VBB
VEE - .5
VCC + .5
V
DOUT, COMP HIGH, COMP LOW
VEE - .5
VCC + .5
V
Ambient Operating Temperature
TA
-50
+125
oC
Storage Temperature
TS
-65
+150
oC
Junction Temperature
TJ
+150
oC
TSOL
+260
Analog Output Voltages
Soldering Temperature
(5 seconds, .25" from the pin)
oC
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these, or any other conditions beyond
those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device
reliability.
 2004 Semtech Corp. / Rev. 5, 8/18/04
12
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
DC Characteristics
Parameter
Symbol
Min
VH
VL
VH – VL
Ileak
Rout
Iout DC
Iout AC
VEE
VEE
– 18
– 2.0
9.0
– 125
– 400
VINP
CVA, CVB
Vos
Ibias
VEE
VEE + 3.0
– 200
– 10
COMP HIGH
COMP LOW
– 2.0
– 2.0
Rout
30
-50
EN*, DATA - VBB
VBB - EN*, DATA
Iin
1.0
1.0
– 100
ICC
IEE
36
36
Typ
Max
Units
VCC
VCC
18
+2.0
15
+125
+400
V
V
V
nA
Ω
mA
mA
VCC
VCC – 3.0
+100
+10.0
V
V
mV
nA
+5.0
+5.0
V
V
50
50
Ω
mA
0
+100
V
V
nA
57
57
78
78
mA
mA
Driver
High Voltage
Low Voltage
Output Swing
HiZ Leakage Current
Output Impedance
DC Output Current (Note 1)
AC Output Current (Note 2)
0
12
Receiver
Input Voltage Range
Threshold Voltage Range
Offset Voltage (Note 3)
Input Bias Current
Output Voltage Range
QA, QB Output Impedance
DC Output Current Capability
0
40
Digital Inputs
Input High Voltage
Input Low Voltage
Input Current
Power Supplies
Positive Supply Current (Note 4)
Negative Supply Current (Note 4)
Test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note
Note
Note
Note
1:
2:
3:
4:
DC output current is specified per individual driver.
Surge current capability for durations of < 2 seconds.
Offset voltage is tested at CVA, CVB = 1.5V.
Power supply current tested with VCC = +15V, VEE = –3V.
 2004 Semtech Corp. / Rev. 5, 8/18/04
13
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
AC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Tpd
Tpd
Tpd
9.5
10
11
14.5
20
16
19.5
30
21
ns
ns
ns
Driver
DATA to DOUT
EN* to DOUT (Active to HiZ) (Note 1)
EN* to DOUT (HiZ to Active)
Rise/Fall Times (Note 2)
1V Swing (20% - 80%)
3V Swing (10% - 90%)
5V Swing (10% - 90%)
10V Swing (10% - 90%)
15V Swing (10% - 90%)
Tr/Tf
Tr/Tf
Tr/Tf
Tr/Tf
Tr/Tf
Maximum Operating Frequency (Note 3)
Fmax
50
Minimum Pulse Width
DOUT Capacitance
ns
ns
ns
ns
ns
1.5
1.9
2.0
2.5
3.2
MHz
8
11
19
CD O U T
ns
pF
Receiver
Comparator Propagation Delay (Note 4)
Tpd+ (Positive Edge)
VINP – CVA(B) = 0.2V
VINP – CVA(B) = 0.3V
VINP – CVA(B) = 0.4V
VINP – CVA(B) = 1.5V
VINP – CVA(B) ≥ 1.5V
Tpd
Tpd– (Negative Edge)
VINP – CVA(B) = 0.2V
VINP – CVA(B) = 0.3V
VINP – CVA(B) = 0.4V
VINP – CVA(B) = 1.5V
VINP – CVA(B) ≥ 1.5V
Maximum Operating Frequency (Note 3)
Fmax
Minimum Pulse Width
VINP Capacitance
23.3
19.0
17.0
9.7
8.0
49.7
41.0
36.0
20.7
20.7
ns
ns
ns
ns
ns
28.5
22.5
22.0
14.5
10.0
58.5
47.5
41.6
23.5
23.5
ns
ns
ns
ns
ns
50
MHz
10
CV I N P
6
15
ns
pF
Test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1:
Note 2:
Note 3:
Note 4:
Load = 10 mA and measured when a 1V change at the output is detected. (VH = 3V,
VL = 0V, VFLOAT = 1.5V, tested at 1V and 2V.)
Into 18 cm of 50 Ω transmission line terminate with 1 KΩ, with proper series termination
resistor. Guaranteed by characterization. This parameter is not tested in production.
This parameter is production tested at 40 MHz.
Tested under no-load conditions.
 2004 Semtech Corp. / Rev. 5, 8/18/04
14
www .semtech.com
Edge818
TEST AND MEASUREMENT PRODUCTS
Ordering Information
Model Number
Package
E818AHF
100 Lead MQFP
14 mm x 20 mm Body Size
w/Internal Heat Spreader
EVM818AHF
Edge818 Evaluation Board
Contact Information
Semtech Corporation
Test and Measurement Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
 2004 Semtech Corp. / Rev. 5, 8/18/04
15
www .semtech.com