ISL55141, ISL55142, ISL55143 ® Data Sheet July 17, 2006 High-Speed 18V CMOS Comparators Features ISL55141, ISL55142, ISL55143 integrated circuits are high-speed, wide input common-mode range comparators. They provide three-state window comparators in a high voltage CMOS process (18V). Each comparator has dual receive thresholds, CVA and CVB, for establishing minimum 1-VIH and maximum 0-VIL voltage levels. These devices can accept inputs from a number of logic families, such as TTL, ECL, CMOS, LVCMOS, LVDS and CML. Two bits of output per comparator provide the test controller with qualification of a comparator input into three states. The two output bits work with a separate user supply to establish VOH, VOL levels compatibility with the system’s controller logic levels. • 18V I/O range Fast propagation delay (9.5ns typical at ±50mV overdrive) makes this family compatible with high-speed digital test systems. The 18V range enables the comparator input to operate over a wide input range. Two references per input enable and three state digitization of input with voltage swings of up to 13V common mode. The operating frequency of these devices is typically 65MHz. FN6230.0 • 65MHz operation • 9.5ns typical propagation delay • Programmable input thresholds • User defined comparator output levels • Common-mode range includes negative rails • Small footprints in QFN packages • Power-down current <10µA • Pb-free plus anneal available (RoHS compliant) Applications • Burn in ATE • Low cost ATE • Fast supervisory power control • Instrumentation High voltage CMOS process makes these devices ideal for large voltage swing applications, such as special test voltages levels associated with Flash devices or power supervision applications and may avoid the need for test bus isolation relay(s). Ordering Information ISL55141IRZ* 55141IRZ (See Note) -40 to +85 16 Ld QFN (Pb-free) Functional Block Diagram ISL55141IVZ* 55141IVZ (See Note) -40 to +85 14 Ld TSSOP M14.173 (Pb-free) ISL55142IRZ* 55142IRZ (See Note) -40 to +85 20 Ld QFN (Pb-free) ISL55142IVZ* 55142IVZ (See Note) -40 to +85 20 Ld TSSOP M20.173 (Pb-free) ISL55143IRZ* 55143IRZ (See Note) -40 to +85 36 Ld TQFN (Pb-free) DUAL LEVEL COMPARATOR - RECEIVERS VOH VCC QAX CVAX VOL VEE VOH VCC VINPX PART NUMBER PART TEMP. MARKING RANGE (°C) PACKAGE PKG. DWG. # L16.4X4A L20.5x5 L36.6X6 * Add “-T” suffix for tape and reel. QBX CVBX VOL VEE x denotes 1, 2 or 4 channels for ISL55141, ISL55142 and ISL55143, respectively 1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL55141, ISL55142, ISL55143 Pinouts QA 3 10 VINP QB 4 9 6 7 8 CVB0 CVB1 18 17 16 PD 1 15 VINP1 VEE 2 14 CVA1 VCC 3 13 VCC VOH 4 12 VEE VOL 5 11 NC 6 QA0 5 CVA 19 7 8 9 10 NC 11 CVB 20 QB1 2 VCC NC VEE 12 NC VOH 1 VOL NC VINP0 13 QA1 14 CVA0 15 QB0 16 NC PD TOP VIEW NC TOP VIEW VEE ISL55142 SINGLE DEVICE (5X5 QFN) NC ISL55141 SINGLE DEVICE (4X4 QFN) ISL55141 (TSSOP) ISL55142 (TSSOP) TOP VIEW TOP VIEW VEE 1 14 PD CVB0 1 20 CVB1 NC 2 13 NC VINP0 2 19 VINP1 NC 3 12 CVB CVA0 3 18 CVA1 QA 4 11 VINP PD 4 17 NC QB 5 10 CVA VEE 5 16 VCC VOL 6 9 VCC VCC 6 15 VEE VOH 7 8 VEE VOH 7 14 NC VOL 8 13 NC QA0 9 12 QB1 QB0 10 11 QA1 ISL55143 QUAD DEVICE (6X6 TQFN) 2 NC NC VCC VEE VCC VEE NC NC PD TOP VIEW 36 35 34 33 32 31 30 29 28 QA1 4 24 CVB1 QB1 5 23 VINP1 QA2 6 22 CVA1 QB2 7 21 CVB2 QA3 8 20 VINP2 QB3 9 19 CVA2 10 11 12 13 14 15 16 17 18 CVB3 25 CVA0 VINP3 3 CVA3 QB0 VCC 26 VINP0 VEE 2 VOL QA0 VOH 27 CVB0 VOL 1 VOH NC FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Pin Descriptions PIN FUNCTION VEE Negative supply input QAX Channel A, CVAX reference driven. Comparator output. QBX Channel B, CVBX reference driven. Comparator output. VOL Comparator output logic low supply. Unbuffered analog input that sets all QAX, QBX “low” voltage level. VOH Comparator output logic high supply. Unbuffered analog input that sets all QAX, QBX “high” voltage level. VCC Positive supply input. CVAX Channel A comparator reference analog input. VINPX Window comparator input. Common to both channel Ax and channel Bx. CVBX Channel B comparator reference analog input. PD Power-down logic input (connect to VEE if not used for power-down). NC No internal connection. TABLE 1. CVA-QA AND CVB-QB BASIC COMPARATOR TRUTH TABLE INPUT OUTPUTS* VINPX QAX QBX <CVAX <CVBX 0 0 <CVAX >CVBX 0 1 >CVAX <CVBX 1 0 >CVAX >CVBX 1 1 * When QAX/QBX = 1, Output is connect to VOH * When QAX/QBX = 0, Output is connect to VOL 3 FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Absolute Maximum Ratings Thermal Information VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 19V Input Voltages PD, CVAX, CVBX, VINPX, VOH, VOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VEE -0.5V) to (VCC +0.5V) Output Voltage QAX, QBX . . . . . . . . . . . . . . . . . . . . . (VOL -0.5V) to (VOH +0.5V) Thermal Resistance (Typical, Note 1, 2) θJA (°C/W) 16 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 75 14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 90 20 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 65 20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 80 36 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 45 Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review Power Dissipation Considerations for more information. pO Recommended Operating Conditions PARAMETER SYMBOL MIN TYP MAX UNITS VCC-VEE 10 15 18 V Comparator Output High Rail VOH VEE+1 VCC-0.5 V Comparator Output Low Rail VOL VEE+0.5 VEE+6 V Common Mode Input Voltage Range VCM VEE VCC-5 V Ambient Temperature TA -40 +85 °C Junction Temperature TJ +125 °C Device Power Electrical Specifications 27 Test Conditions: VCC = 12V, VEE = -3V, VOH = 5V, VOL = 0V, PD = VEE, CLOAD = 15pF, TA = 25°C, unless otherwise specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS Input Offset Voltage VOS CVAX = CVBX = 1.5V 50 mV Input Bias Current IBIAS VINPX - CV(A/B)X = ±5V -50 10 25 nA Power-down Current IPD PD = VCC 8 25 µA Power-down Time (Note 5) tPD 10 µs Power-up Time (Note 5) tPU 15 µs TIMING CHARACTERISTICS 4.0 9.5 Propagation Delay tpd Rise Time (Note 5) tr 1.4 tf 1.5 Δtpd 0.5 Fall Time (Note 5) Propagation Delay Mismatch Maximum Operating Frequency FMAXR Min Pulse Width tWIDR Symmetry 50% 15 ns ns ns 2 ns 65 MHz 7.7 ns COMPARATOR INPUT Input Current IIN Input Capacitance (Note 5) CIN 4 VINPX = VCC or VEE -100 0 2.5 100 nA pF FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Electrical Specifications Test Conditions: VCC = 12V, VEE = -3V, VOH = 5V, VOL = 0V, PD = VEE, CLOAD = 15pF, TA = 25°C, unless otherwise specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS QAX, QBX 18 27 37 Ω Output Logic High Voltage VOH VOH = 5V, ISOURCE = 1mA 4.9 4.95 5.0 V Output Logic Low Voltage VOL VOL = 0V, ISINK = 1mA 0.00 0.05 0.1 V +8.25 12.5 mA Output Resistance RoutR POWER SUPPLIES, STATIC CONDITIONS Positive Supply DC Current/Comparator ICC No input data Negative Supply Current/Comparator IEE No input data Total Power Dissipation/Comparator P† Input data at 40MHz -12.5 -8.25 mA 670 mW †Total Power dissipation per comparator can be approximately calculated from the following: P = (VCC-VEE)*8.25mW + 90pF*(VCC-VEE)^2*f + CL*(VCC-VEE)^2*f where f is the operating frequency and CL is the load capacitance. Because the ISL55142 has two comparators, the power dissipation would be twice of P calculated from the above equation. The ISL55143 would be four times P. NOTES: 3. Lab characterization, room temperature, timing parameters matched stimulus/loads, channel-to-channel skew < 500ps, 1ns maximum by design 4. Note about ICC measurement input can approach 140mA (single comparator) at maximum pattern rates 5. Not 100% Tested Test Circuits and Waveforms DATA = 1 DATA = 0 400mV VINPX 0V tPDLH tPDHL VOH (≈VH) 50% QAX, QBX 50% VOL (≈VL) tR tF FIGURE 1. COMPARATOR PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS CVA 2.4V + - VCC QA VINP CVB 0.4V + - VEE Although there is no electrical difference between the CVA and CVB Inputs, if one defines CVA as being the high threshold and CVB being the low threshold, it becomes easier to understand the utilization of a dual threshold comparator. Essentially this enables the qualification of an incoming signal into three states. In the case pictured, the three states are Valid Low <0.4V, No-man’s-land (between 0.4 and 2.4V), Valid High >2.4V. Table 2 shows how the QA/QB truth table would be utilized in the real world. TABLE 2. QA/QB TRUTH TABLE QB VINP QA QB COMMENT <0.4V 0 0 Valid 0 >0.4 and <2.4V 0 1 Invalid >2.4V 1 1 Valid 1 FIGURE 2. THREE-STATE WINDOW COMPARATOR FUNDAMENTALS 5 FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Test Circuits and Waveforms (Continued) CVA = CVB = 1.5V +11 VCC CVA 1.5V 50mV + +5V-VOH VINP QA VINP -50mV tPDLH VOL CVB 1.5V 1.5V 1.5V tPDHL VOH (≈5V) + - QB QX 50% 50% VOL (≈0V) -3 VEE FIGURE 3. tpd RECEIVER SWITCHING TEST CIRCUIT Application Information The ISL55141, ISL55142, ISL55143 provide 1, 2 and 4 dual threshold, three-state window comparator(s) in TSSOP or QFN footprints. They offer a combination of speed (10ns Tpd and wide voltage range (18V). This product directly addresses the need for unique common-mode characterisitics while supplying a power-down feature. FIGURE 4. tpd RECEIVER PROPAGATION DELAY MEASUREMENT POINTS The truth table for the receivers is given in Table 1. Receiver outputs are not tri-statable, and do not incorporate any on-chip short circuit current protection. Momentary short circuits to GND, or any supply voltage, will not cause permanent damage, but care must be taken to avoid longer duration short circuits. If tolerable to the application, current limiting resistors can be inserted in series with the QAX and QBX outputs to protect the receiver outputs from damage due to overcurrent conditions. Figures 3 and 4 show the stimulus setup and measurement points for an example propagation delay measurement. Typical room temperature results are displayed in Figure 11. Power-down Features Figure 4 shows a VINP range of 50mV. In Figure 11 the offset is increased in the horizontal axis from 50mV above and below the reference (1.5V) up to 2.5V above and below the 1.5V reference. The ISL55141, ISL55142, ISL55143 PD pin provides a means of reducing current consumption when the device is not in use. Supply currents falls from ~7mA to less than 10µA in the power-down mode. The device requires approximately 10µs to power-down and 15µs to power-up. Two lines are displayed in Figure 11. One represents the rising-to-rising delay (tPDLH) and the other the falling-to-falling delay (tPDHL). Power Supply Bypassing and Printed Circuit Board Layout Comparator Features These three-state window comparators feature high output current capability, and user defined high and low output levels to interface with a wide variety of logic families. Each receiver comprises two comparators and each comparator has an independent threshold level input, making it easy to implement (Minimum1-VIH)/(Maximum 0-VIL) logic level comparator functions. The CVAX and CVBX pins set the threshold levels of the A and B comparators respectively. VOH and VOL set all the comparator output levels, and VOH must be more positive than VOL. These two inputs are unbuffered supply pins, so the sources driving these pins must provide adequate current for the expected load. VOH and VOL typically connect to the power supplies of the logic device driven by the comparator outputs. 6 As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VEE pin is connected to ground, one 0.1µF ceramic capacitor should be placed from the VCC pin to ground. A 4.7µF tantalum capacitor should then be connected from the VCC pin to ground. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Power Dissipation Considerations Specifying continuous data rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation/cooling necessities. Driver output patterns also impact these needs. The faster the pin activity, the greater the need to supply current and remove heat. Power Supply Information OPTIONAL PROTECTION DIODE VCC VOH CVA The maximum power dissipation allowed in a package is determined according to: QA VINP T JMAX - T AMAX P DMAX = -------------------------------------------Θ JA where: QB CVB • TJMAX = Maximum junction temperature VOL • TAMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package Approximate Power Dissipation VEE OPTIONAL PROTECTION DIODE (Typ) P = N*[(VCC-VEE)*8.25mW + 90pF*(VCC-VEE)^2*f + CL*(VOH-VOL)^2*f] where: N is the number of comparators in the chip (1 for ISL55141, 2 for ISL55142 and 4 for ISL55143). (f) is the operating frequency. CL is the load capacitor. The power dissipation calculated from the above formula may have an error of ±20-25%. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads. Power also depends on the number of channels changing state and frequency of operation. The extent of continuous active pattern generation/reception will greatly affect dissipation requirements. The user should evaluate various heat sink/cooling options in order to control the ambient temperature part of the equation. This is especially true if the user’s applications require continuous, high-speed operation. Circuit design must always take into account the internal EOS/ESD protection structure of the device. Important Note: The QFN package metal plane is used for heat sinking of the device. It is electrically connected to the negative supply potential (VEE). If VEE is tied to ground, the thermal pad can be connected to ground. Otherwise, the thermal pad (VEE) must be isolated from other power planes. Power Supply Sequencing The ISL55141, ISL55142, ISL55143 reference every supply with respect to VEE. Therefore, apply VEE, VOL then VCC followed by the CVA and CVB supplies. The comparator VINP pin should not exceed VEE or VCC during power-up. In cases where inputs may exceed voltage rails during power-up, series resistance should be employed to safeguard EOS to the ESD protection diodes. The reader is cautioned against assuming the same level of thermal performance in actual applications. A careful inspection of conditions in your application should be conducted. 7 FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Typical Performance Curves Device installed on Intersil ISL55141, ISL55142, ISL55143 Evaluation Boards. 60 30.0 54 27.0 48 ISL55143 21.0 42 18.0 36 ICC (mA) ICC (mA) 24.0 15.0 ISL55142 12.0 VCC = 18V VCC = 14V 30 24 18 09.0 06.0 12 ISL55141 03.0 6 00.0 0 10 12 14 16 18 VCC = 10V 3200 1600 FIGURE 5. ISL55141, ISL55142, ISL55143 QUIESCENT CURRENT 100 160 56 ICC (mA) 40 32 24 1 CHANNEL 4 CHANNELS 120 3 CHANNEL 100 2 CHANNEL 80 60 16 40 8 20 3200 1600 800 400 200 100 50 0 25 VINP SQUARE WAVE PERIOD IN ns 3200 1 CHANNEL 1600 800 400 200 100 50 25 VINP SQUARE WAVE PERIOD IN ns FIGURE 7. ISL55142 ICC 1 AND 2 CHANNELS ACTIVE FIGURE 8. ISL55143 ICC 1, 2, 3, 4 CHANNELS ACTIVE 100 250 90 225 80 VCC = 18V VCC = 18V 200 70 175 60 ICC (mA) VCC = 14V 50 40 150 100 75 20 50 10 25 VCC = 10V 1600 800 400 200 100 50 25 VINP SQUARE WAVE PERIOD IN ns FIGURE 9. ISL55142 2-CHANNEL ICC @ 10V, 14V, AND 18V 8 VCC = 14V 125 30 3200 25 140 2 CHANNELS 48 0 50 180 64 ICC (mA) 200 200 72 ICC (mA) 400 FIGURE 6. ISL55141 ICC vs FREQUENCY @ 10V, 14V, AND 18V 80 0 800 VINP SQUARE WAVE PERIOD IN ns VCC - VEE VOLTAGE 0 3200 VCC = 10V 1600 800 400 200 100 50 25 VINP SQUARE WAVE PERIOD IN ns FIGURE 10. ISL55143 4-CHANNEL ICC @ 10V, 14V, AND 18V FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Typical Performance Curves Device installed on Intersil ISL55141, ISL55142, ISL55143 Evaluation Boards. (Continued) 15.0 13.5 +tpd DELAY tPDLH 10.5 9.0 7.5 6.0 VCC 15.0 VEE - 3.0 0.5V/DIV DELAY (ns) 12.0 0 -tpd DELAY tPDHL 4.5 3.0 0 0.05 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 VINP INPUT OFFSET ±1.5 VOLT REFERENCE FIGURE 11. PROPAGATION DELAY @ 14V VCC-VEE 9 1.0V/DIV 1.5 0 10ns/DIV FIGURE 12. MINIMUM PULSE WIDTH RESPONSE FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.4x4A 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGD-10) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 9 A3 b 0.20 REF 0.18 D 0.30 5, 8 4.00 BSC D1 D2 0.25 9 - 3.75 BSC 2.30 2.40 9 2.55 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 2.30 e 2.40 2.55 7, 8 0.50 BSC - k 0.25 - - - L 0.30 0.40 0.50 8 L1 - - 0.15 10 N 16 2 Nd 4 3 Ne 4 3 P - - 0.60 9 θ - - 12 9 Rev. 2 3/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. 10 FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- e α A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE A2 c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX α 14 0o 14 7 8o Rev. 2 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 11 FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.5x5 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - 0.02 0.05 - A2 - 0.65 1.00 9 0.38 5, 8 A3 b 0.20 REF 0.23 0.30 9 D 5.00 BSC - D1 4.75 BSC 9 D2 2.95 E E1 E2 3.10 3.25 7, 8 5.00 BSC - 4.75 BSC 2.95 e 3.10 9 3.25 7, 8 0.65 BSC - k 0.20 - - - L 0.35 0.60 0.75 8 N 20 2 Nd 5 3 Ne 5 3 P - - 0.60 9 θ - - 12 9 Rev. 4 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VHHC Issue I except for the "b" dimension. 12 FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Thin Shrink Small Outline Plastic Packages (TSSOP) M20.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- α e A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE A2 c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX α 20 0o 20 7 8o Rev. 1 6/98 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 13 FN6230.0 July 17, 2006 ISL55141, ISL55142, ISL55143 Thin Quad Flat No-Lead Plastic Package (TQFN) L36.6x6 2X 0.15 C A D A 36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) D/2 MILLIMETERS 2X 6 INDEX AREA N 0.15 C B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - 0.30 5, 8 A3 E/2 b E 0.20 REF 0.18 D D2 3.80 E B TOP VIEW E2 A / / 0.10 C 0.08 C SEATING PLANE A3 SIDE VIEW A1 3.95 4.05 6.00 BSC 3.80 e C 0.25 6.00 BSC 3.95 7, 8 - 4.05 0.50 BSC 7, 8 - k 0.20 - - - L 0.45 0.55 0.65 8 N 36 2 Nd 9 3 Ne 9 3 Rev. 2 04/06 NX b 5 0.10 M C A B D2 NX k D2 2 (DATUM B) 8 7 N (DATUM A) 6 INDEX AREA E2 E2/2 3 2 1 NX L N 7 (Ne-1)Xe REF. 8 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. e 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 SECTION "C-C" All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6230.0 July 17, 2006