ISL59530 ® Data Sheet June 12, 2006 FN6220.1 16x16 Video Crosspoint Features The ISL59530 is a 300MHz 16x16 Video Crosspoint Switch. Each input has an integrated DC-restore clamp and an input buffer. Each output has a fast On-Screen Display (OSD) switch (for inserting graphics or other video) and an output buffer. The switch is non-blocking, so any combination of inputs to outputs can be chosen, including one channel driving multiple outputs. The Broadcast Mode directs one input to all 16 outputs. The output buffers can be individually controlled through the SPI interface, the gain can be programmed to x1 or x2, and each output can be placed into a high impedance mode. • 16x16 non-blocking switch with buffered inputs and outputs The ISL59530 offers a typical -3dB signal bandwidth of 300MHz. Differential gain of 0.025% and differential phase of 0.05°, along with 0.1dB flatness out to 50MHz, make the ISL59530 suitable for many video applications. • Pb-free plus anneal available (RoHS compliant) The switch matrix configuration and output buffer gain are programmed through an SPI/QSPI™-compatible three-wire serial interface. The ISL59530 interface is designed to facilitate both fast updates and initialization. On power-up, all outputs are high impedance to avoid output conflicts. • RGB routing • 300MHz typical bandwidth • 0.025%/0.05° dG/dP • Output gain switchable x1 or x2 for each channel • Individual outputs can be put in a high impedance state • -90dB Isolation at 6MHz • SPI digital interface • Single +5V supply operation Applications • Security camera switching • HDTV routing Ordering Information The ISL59530 is available in a 356 ball BGA package and specified over an extended -40°C to +85°C temperature range. The single-supply ISL59530 can accommodate input signals from 0V to 3.5V and output voltages from 0V to 3.8V. Each input includes a clamp circuit that restores the input level to an externally applied reference in AC-coupled applications. PART NUMBER TAPE & REEL ISL59530IKZ (Note) - PACKAGE PKG. DWG. # 356 Ld PBGA (Pb-free) V356.27x27 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. The ISL59531 is a fully differential input version of this device. Block Diagram VS+ VOVERn OVERn VREF 16 OVERLAY INPUT + 16 LOGIC CONTROL 2uA Power-on 16 INPUTS Clamp Enable SWITCH MATRIX 16 OUTPUTS + 2uA Av x1, x2 SDI SCLK SLATCH 1 SPI INTERFACE, REGISTER Output Enable Power-on SDO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59530 Pinout ISL59530 (356 LD BGA) TOP VIEW A In12 In13 In14 In15 Over15 Over14 Out13 Out12 Out15 Out14 Over13 Over12 Vover15 Vover14 Vover13 Vover12 B C D VSDO In11 Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vover11 Out11 Over11 E Vs Vs F Vs GND GND GND GND GND GND GND GND GND GND Vs SDO Vs GND GND GND GND GND GND GND GND GND GND Vs RESET Vs GND GND GND GND GND GND GND GND GND GND Vs SLATCH Vs GND GND GND GND GND GND GND GND GND GND Vs SCLK Vs GND GND GND GND GND GND GND GND GND GND Vs SDI Vs GND GND GND GND GND GND GND GND GND GND Vs VREF Vs GND GND GND GND GND GND GND GND GND GND Vs Vs GND GND GND GND GND GND GND GND GND GND Vs Vs GND GND GND GND GND GND GND GND GND GND Vs Vs GND GND GND GND GND GND GND GND GND GND Vs In10 Vover10 Out10 Over10 G H In9 Vover9 Over9 Out9 Vover8 Over8 Out8 Vover7 Out7 Over7 Vover6 Out6 Over6 Vover5 Over5 Out5 Vover4 Over4 Out4 18 19 20 J K In8 L M In7 N P In6 R T Vs In5 Vs U Vs Vs Vs NC NC Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs NC Vover0 Vover1 Vover2 Vover3 Over0 Over1 Out2 Out3 Out0 Out1 Over2 Over3 Vs V In4 W Y In3 1 2 In2 3 In1 4 5 6 In0 7 8 9 10 11 12 13 14 15 16 17 = NO BALLS Balls labelled “NC” should be left unconnected - do not tie them to ground! Balls with no labels may be tied to ground to slightly reduce thermal impedance. 2 FN6220.1 June 12, 2006 ISL59530 Absolute Maximum Ratings (TA = +25°C) Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 6.0V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum power supply (VS) slew rate . . . . . . . . . . . . . . . . . . 1V/µs ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VS = 5V, RL = 150Ω unless otherwise noted. DESCRIPTION CONDITION MIN TYP MAX UNIT 4.5 5.5 V 5.5 V VS Power Supply Voltage VSDO Power Supply for SDO output pin Establishes serial data output high level 1.2 AV Gain AV = 1 0.98 1 1.02 V/V AV = 2 1.96 2 2.04 V/V AV = 1 -1.5 +1.5 % AV = 2 -1.5 +1.5 % GM Gain Matching (to average of all other outputs) VIN Video Input Voltage Range AV = 1 0 3.5 V VOUT Video Output Voltage Range AV = 2 0.1 3.8 V IB Input Bias Current Clamp function disabled (DC coupled inputs) -10 -5 1 µA Clamp function enabled, VIN = VREF + 0.5V 0.5 2 10 µA AV = 1 -20 8 35 mV AV = 2 -70 -10 40 mV Sourcing, RL = 10Ω to GND 60 108 mA Sinking, RL = 10Ω to 2.5V 24 31 mA dB VOS IOUT Output Offset Voltage Output Current PSRR Power Supply Rejection Ratio AV = 1 and AV = 2 50 70 IS Supply Current Enabled, all outputs enabled, no load current 275 320 360 mA Enabled, all outputs disabled, no load current 135 165 195 mA Disabled 1.2 1.8 2.4 mA MIN TYP MAX UNIT AC Electrical Specifications PARAMETER VS = 5V, RL = 150Ω unless otherwise noted. DESCRIPTION CONDITION BW -3dB 3dB Bandwidth VOUT = 200mVP-P, AV = 2 300 MHz BW 0.1dB 0.1dB Bandwidth VOUT = 200mVP-P, AV = 2 50 MHz SR Slew Rate VOUT = 2VP-P, AV = 2 TS Settling Time to 0.1% VOUT = 2VP-P, AV = 2 12 ns Glitch Switching Glitch, Peak AV = 1 40 mV Tover Overlay Delay Time From OVER rising edge to output transition 6 ns dG Diff Gain AV = 2, RL = 150Ω 0.025 % dP Diff Phase AV = 2, RL = 150Ω 0.05 ° Xt Hostile Crosstalk 6MHz -85 dB VN Input Referred Noise Voltage 18 nV/√Hz 3 300 520 740 V/µs FN6220.1 June 12, 2006 ISL59530 Pin Descriptions (Continued) Pin Descriptions NAME NUMBER Crosspoint Video Input OVER6 P20 Overlay Logic Control (with pulldown) Y6 Crosspoint Video Input OVER7 M20 Overlay Logic Control (with pulldown) IN2 Y4 Crosspoint Video Input OVER8 K19 Overlay Logic Control (with pulldown) IN3 Y2 Crosspoint Video Input OVER9 H19 Overlay Logic Control (with pulldown) IN4 V1 Crosspoint Video Input OVER10 F20 Overlay Logic Control (with pulldown) IN5 T1 Crosspoint Video Input OVER11 D20 Overlay Logic Control (with pulldown) IN6 P1 Crosspoint Video Input OVER12 B17 Overlay Logic Control (with pulldown) IN7 M1 Crosspoint Video Input OVER13 B15 Overlay Logic Control (with pulldown) IN8 K1 Crosspoint Video Input OVER14 A13 Overlay Logic Control (with pulldown) IN9 H1 Crosspoint Video Input OVER15 A11 Overlay Logic Control (with pulldown) IN10 F1 Crosspoint Video Input VOVER0 V10 Overlay Video Input IN11 D1 Crosspoint Video Input VOVER1 V12 Overlay Video Input IN12 A1 Crosspoint Video Input VOVER2 V14 Overlay Video Input IN13 A3 Crosspoint Video Input VOVER3 V16 Overlay Video Input IN14 A5 Crosspoint Video Input VOVER4 V18 Overlay Video Input IN15 A7 Crosspoint Video Input VOVER5 T18 Overlay Video Input OUT0 Y10 Crosspoint Video Output VOVER6 P18 Overlay Video Input OUT1 Y12 Crosspoint Video Output VOVER7 M18 Overlay Video Input OUT2 W14 Crosspoint Video Output VOVER8 K18 Overlay Video Input OUT3 W16 Crosspoint Video Output VOVER9 H18 Overlay Video Input OUT4 V20 Crosspoint Video Output VOVER10 F18 Overlay Video Input OUT5 T20 Crosspoint Video Output VOVER11 D18 Overlay Video Input OUT6 P19 Crosspoint Video Output VOVER12 C17 Overlay Video Input OUT7 M19 Crosspoint Video Output VOVER13 C15 Overlay Video Input OUT8 K20 Crosspoint Video Output VOVER14 C13 Overlay Video Input OUT9 H20 Crosspoint Video Output VOVER15 C11 Overlay Video Input OUT10 F19 Crosspoint Video Output VREF M3 OUT11 D19 Crosspoint Video Output OUT12 A17 Crosspoint Video Output OUT13 A15 Crosspoint Video Output OUT14 B13 Crosspoint Video Output OUT15 B11 Crosspoint Video Output OVER0 W10 Overlay Logic Control (with pulldown) OVER1 W12 Overlay Logic Control (with pulldown) OVER2 Y14 Overlay Logic Control (with pulldown) DC-restore clamp reference input. In an AC-coupled configuration (DC-Restore clamp enabled), the sync tip of composite video inputs will be restored to this level. Set to 0.3 to 0.7V for optimum performance. In an DC-coupled configuration (DC-Restore clamp disabled), this pin should be tied to ground. Never let the VREF pin float! A floating VREF pin drifts high (and if the clamp function is enabled) will cause all of the outputs to simultaneously try to OVER3 Y16 Overlay Logic Control (with pulldown) OVER4 V19 Overlay Logic Control (with pulldown) OVER5 T19 Overlay Logic Control (with pulldown) NAME NUMBER IN0 Y8 IN1 DESCRIPTION 4 DESCRIPTION drive ~4V DC into their 150Ω loads. SLATCH J3 Serial Latch. Serial data is latched into ISL59530 on rising edge of SLATCH. FN6220.1 June 12, 2006 ISL59530 Pin Descriptions (Continued) NAME NUMBER DESCRIPTION SCLK K3 Serial data clock SDI L3 Serial data input SDO G3 Serial data output. Can be tied to SDI of another ISL59530 to enable daisychaining of multiple devices. RESET H3 VSDO D3 Reset input. Pull high then low to reset device, but not needed in normal operation. Tie to ground in final application. Power supply for SDO pin. Tie to +5V for a 0 to 5V SDO output signal swing. VS GND NC +5V power supply Ground No Connect - Do not electrically connect to anything, including ground. 5 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves 15pF Vs=+5V AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 VS=+5V AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 10pF 15pF 10pF 4.7pF 4.7pF 0pF 0pF FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, MUX MODE VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0 150Ω 50Ω FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, MUX MODE VS=+5V AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0 150Ω 50Ω 500Ω 500Ω 1.03kΩ 1.03kΩ FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, MUX MODE Overlay mode AV = 1 RL = 100Ω CL=0pF INPUT_CH 0 OUTPUT_CH 15 FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, MUX MODE Overlay mode AV = 2 RL = 100Ω CL=0pF INPUT_CH 0 OUTPUT_CH 15 FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 1 6 FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 2 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves (Continued) VS=+5V AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 15pF 10pF 15pF 10pF 4.7pF 4.7pF VS=+5V AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 0pF 0pF FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, BROADCAST MODE VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0 150Ω 50Ω FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, BROADCAST MODE VS=+5V AV = 2 CL = 0pF INPUT_CH 0 OUTPUT_CH 0 503Ω 50Ω 150Ω 503Ω 1.03kΩ 1.03kΩ FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, BROADCAST MODE AV = 1 RL = 100Ω CL = 0 AV = 2 RL = 100Ω CL = 0 ADJACENT INPUT_CH14 OUTPUT_CH15 ALL HOSTILE INPUT_CH0 OUTPUT_CH15 FIGURE 11. CROSSTALK - AV = 1 7 FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, BROADCAST MODE ADJACENT INPUT_CH14 OUTPUT_CH15 ALL HOSTILE INPUT_CH0 OUTPUT_CH15 FIGURE 12. CROSSTALK - AV = 2 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves (Continued) THD VS=+5V AV=2 RL=100Ω INPUT_CH 1 OUTPUT_CH1 FIN= 1MHz THD 2nd HD 2nd HD 3rd HD VS=+5V AV=2 RL=100Ω INPUT_CH 1 OUTPUT_CH 1 VOP-P =2V 3rd HD FIGURE 13. HARMONIC DISTORTION vs FREQUENCY FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P FIGURE 15. DISABLED OUTPUT IMPEDANCE FIGURE 16. ENABLED OUTPUT IMPEDANCE MUX MODE AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 FALL TIME 2.44ns RISE TIME 2.42ns MUX MODE AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 TIME (ns) FIGURE 17. RISE TIME - AV = 1 8 TIME (ns) FIGURE 18. FALL TIME - AV = 1 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves (Continued) MUX MODE AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 FALL TIME 2.40ns RISE TIME 2.32ns MUX MODE AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 TIME (ns) TIME (ns) FIGURE 19. RISE TIME - AV = 2 FIGURE 20. FALL TIME - AV = 2 MUX MODE AV = 1 RL=100Ω INPUT_CH 0 OUTPUT_CH 0 SLEW RATE -395V/µs SLEW RATE 405V/µs MUX MODE AV = 1 RL=100Ω INPUT_CH 0 OUTPUT_CH 0 TIME (ns) TIME (ns) FIGURE 21. RISING SLEW RATE - AV = 1 FIGURE 22. FALLING SLEW RATE - AV = 1 MUX MODE AV = 2 RL=100Ω INPUT_CH 0 OUTPUT_CH 0 SLEW RATE -420V/µs SLEW RATE 430V/µs MUX MODE AV = 2 RL=100Ω INPUT_CH 0 OUTPUT_CH 0 TIME (ns) FIGURE 23. RISING SLEW RATE - AV = 2 9 TIME (ns) FIGURE 24. FALLING SLEW RATE - AV = 2 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves (Continued) OUTPUT OUTPUT OVERLAY LOGIC INPUT FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME OVERLAY LOGIC INPUT FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME AV = 2 RL = 100Ω INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV AV = 2 RL = 100Ω INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 27. DIFFERENTIAL GAIN, AV = 2 AV = 2 RL = 100Ω INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 28. DIFFERENTIAL PHASE, AV = 2 AV = 2 RL = 100Ω INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 29. DIFFERENTIAL GAIN, AV = 2 10 FIGURE 30. DIFFERENTIAL PHASE, AV = 2 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves (Continued) AV = 1 RL = 100Ω INPUT_CH 1 OUTPUT_CH1 OSC = 40mV AV = 1 RL = 100Ω INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 31. DIFFERENTIAL GAIN, AV = 1 AV = 1 RL = 100Ω INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 32. DIFFERENTIAL PHASE, AV = 1 AV = 1 RL = 100Ω INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 33. DIFFERENTIAL GAIN, AV = 1 AV = 2 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 34. DIFFERENTIAL GAIN, AV = 1 AV = 2 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 35. DIFFERENTIAL GAIN, AV = 2 11 FIGURE 36. DIFFERENTIAL PHASE, AV = 2 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves (Continued) AV = 2 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV AV = 2 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 37. DIFFERENTIAL GAIN, AV = 2 FIGURE 38. DIFFERENTIAL PHASE, AV = 2 AV = 1 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV AV = 1 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 39. DIFFERENTIAL GAIN, AV = 1 FIGURE 40. DIFFERENTIAL PHASE, AV = 1 AV = 1 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV AV = 1 RL = 100Ω INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 41. DIFFERENTIAL GAIN, AV = 1 12 FIGURE 42. DIFFERENTIAL PHASE, AV = 1 FN6220.1 June 12, 2006 ISL59530 Typical Performance Curves (Continued) AV = 2 RL = 100Ω INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV AV = 2 RL = 100Ω INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2 FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2 AV = 1 RL = 100Ω INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV AV = 1 RL = 100Ω INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1 13 FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1 FN6220.1 June 12, 2006 ISL59530 3dB Bandwidth, MUX Mode, AV = 1, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 255 229 229 210 222 221 224 190 169 152 233 190 212 189 207 166 1 244 217 180 168 193 160 2 257 186 171 3 264 183 175 4 255 174 177 5 253 176 177 6 247 226 171 178 157 7 253 227 235 218 223 228 230 174 184 163 240 223 219 217 211 178 8 255 236 240 239 223 236 231 175 187 168 241 242 222 235 213 183 9 241 210 169 188 165 10 235 11 223 12 220 13 211 14 199 212 15 193 217 235 217 220 218 236 207 209 214 207 202 185 216 186 168 186 164 188 161 192 160 192 160 194 222 197 204 169 219 171 202 167 237 173 170 182 230 185 225 186 205 185 224 177 225 217 198 223 189 197 193 197 238 3dB Bandwidth, MUX Mode, AV = 2, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 295 316 290 397 384 405 395 220 288 240 299 250 385 234 396 188 1 268 290 2 277 3 279 4 269 5 263 6 259 7 263 411 307 402 387 8 262 407 308 402 383 9 253 10 253 300 408 391 407 11 246 241 13 236 14 233 279 15 227 274 14 192 392 196 402 192 196 196 283 412 398 201 205 407 307 402 387 413 398 211 412 394 203 212 411 300 403 385 415 394 216 388 194 210 410 194 215 272 367 196 201 183 196 201 385 396 213 291 289 196 412 244 183 192 404 417 12 211 216 407 230 187 213 184 216 182 220 178 220 183 223 298 200 200 214 293 216 412 217 391 225 419 324 276 400 379 413 225 396 230 385 293 FN6220.1 June 12, 2006 ISL59530 3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 215 198 195 183 184 188 172 178 151 145 157 145 140 146 144 158 1 214 195 174 152 144 158 2 210 171 153 3 212 171 157 4 206 169 157 5 203 165 159 6 201 156 163 159 151 7 204 187 182 170 170 175 160 167 167 156 168 157 151 158 154 170 8 204 187 183 172 171 176 161 167 171 160 172 160 155 161 159 175 9 202 157 164 170 160 10 196 11 194 12 193 13 191 14 189 172 15 187 173 188 178 174 177 170 161 162 170 167 157 155 161 149 160 169 157 171 156 171 151 174 151 175 153 178 147 159 143 164 150 164 161 164 164 174 169 178 160 174 156 178 164 167 179 167 160 166 178 162 178 164 181 3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 234 216 209 199 204 205 190 196 169 160 172 162 158 163 161 178 1 232 215 193 169 161 178 2 228 189 171 3 229 191 175 4 223 186 177 5 219 6 217 7 220 204 198 189 190 8 220 205 199 190 191 9 218 10 220 204 196 193 192 11 212 211 13 209 14 208 191 15 205 191 15 183 177 178 167 192 175 183 184 173 184 174 169 174 172 189 193 177 184 187 178 188 178 173 178 178 193 174 181 188 178 176 186 187 171 182 183 179 172 163 168 181 179 184 178 174 185 12 164 176 160 174 188 174 192 170 192 167 194 166 197 177 183 183 193 187 192 177 192 176 195 181 185 195 184 179 185 195 181 196 182 198 FN6220.1 June 12, 2006 ISL59530 Block Diagram VS+ VOVERn OVERn 16 OVERLAY INPUT + VREF 16 LOGIC CONTROL 2uA Power-on 16 INPUTS SWITCH MATRIX Clamp Enable 16 OUTPUTS + 2uA Av x1, x2 SDI SCLK SLATCH SPI INTERFACE, REGISTER General Description The ISL59530 is a 16x16 integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) insertion. This device operates from a single +5V supply. Any output can be generated from any of the 16 input video signal sources, and each output can have OSD information inserted through a dedicated, fast 2:1 mux located before the output buffer. There is also a Broadcast mode allowing any one input to be broadcast to all 16 outputs. A DC restore clamp function enables the ISL59530 to AC-couple incoming video. The ISL59530 offers a -3dB signal bandwidth of 300MHz. Differential gain and differential phase of 0.025% and 0.05° respectively, along with 0.1dB flatness out to 50MHz make this ideal for multiplexing composite NTSC and PAL signals. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPI™-compatible, three-wire serial interface. The ISL59530 interface is designed to facilitate both fast initialization and configuration changes. On power-up, all outputs are initialized to the disabled state to avoid output conflicts in the user’s system. Digital Interface The ISL59530 uses a serial interface to program the configuration registers. The serial interface uses three signals (SCLK, SDI, and SLATCH) for programming the ISL59530, while a fourth signal (SDO) enables optional 16 Output Enable Power-on SDO daisy-chaining of multiple devices. The serial clock can run at up to 5MHz (5Mbits/s). Serial Interface The ISL59530 is programmed through a simple serial interface. Data on the SDI (serial data input) pin is shifted into a 16-bit shift register on the rising edge of the SCLK (serial clock) signal. (This is continuously done regardless of the state of the SLATCH signal.) The LSB (bit 0) is loaded first and the MSB (bit 15) is loaded last (see the Serial Timing Diagram). After all 16 bits of data have been loaded into the shift register, the rising edge of SLATCH updates the internal registers. While the ISL59530 has an SDO (Serial Data Out) pin, it does not have a register readback feature. The data on the SDO pin is an exact replica of the incoming data on the SDI pin, delayed by 15.5 SCLKs (an input bit is latched on the rising edge of SLCK, and is output on SDO on the falling edge of SLCK 15.5 SCLKs later). Multiple ISL59530’s can be daisy-chained by connecting the SDO of one to the SDI of the other, with SCLK and SLATCH common to all the daisychained parts. After all the serial data is transmitted (16 bits * n devices = 16*n SCLKs), the rising edge of SLATCH will update the configuration registers of all n devices simultaneously. The Serial Timing Diagram and Serial Timing Parameters table show the timing requirements for the serial interface. FN6220.1 June 12, 2006 ISL59530 Serial Timing Diagram SLATCH SLATCH falling edge timing/placement is a “don’t care.” Serial data is latched only on rising edge of SLATCH. tSL T SCLK tHD tw tSD B0 (LSB) SDI SDO B1 B15 (MSB) B2 B0 B1 B2 B15 (previous) (previous) (previous) (previous) B0 (LSB) B1 B2 SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59530s. SDO changes on the falling edge of SCLK. TABLE 1. SERIAL TIMING PARAMETERS PARAMETER RECOMMENDED OPERATING RANGE DESCRIPTION T ≥200ns SCLK period tW 0.50 * T Clock Pulse Width tSD ≥20ns Data Setup Time tHD ≥20ns Data Hold Time tSL ≥20ns Final SLCK rising edge (latching B15) to SLATCH rising edge Programming Model The ISL59530 is configured by a series of 16 bit serial control words. The three MSBs (B15-13) of each serial word determine the basic command: TABLE 2. COMMAND FORMAT B15 B14 B13 COMMAND NUMBER OF WRITES 0 0 0 INPUT/OUTPUT: Maps input channels to output channels 16 (1 channel per write) 0 0 1 OUTPUT ENABLE: Output enable for individual channels 4 (4 channels per write) 0 1 0 GAIN SET: Gain (x1 or x2) for each channel 4 (4 channels per write) 0 1 1 BROADCAST: Enables broadcast mode and selects the input channel to be broadcast to all output channels 1 1 1 1 CONTROL: Clamp on/off, operational/standby mode, and global output enable/disable 1 Mapping Inputs to Outputs Inputs are mapped to their desired outputs using the input/output control word. Its format is: TABLE 3. INPUT/OUTPUT WORD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 I3 I2 I1 I0 0 0 0 0 O3 O2 O1 O0 0 I3:I0 form the 4 bit word indicating the input channel (0 to 15), and O3:O0 determine the output channel which that input channel will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59530, 16 INPUT/OUTPUT words must be transmitted - one for each input channel. 17 FN6220.1 June 12, 2006 ISL59530 Enabling Outputs The output enable control word is used to enable individual outputs. There are 16 channels to configure, so this is accomplished by writing 4 serial words, each controlling a bank of four outputs at a time. The bank is selected by bits B9 and B8. The output enable control word format is: TABLE 4. OUTPUT ENABLE FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 0 0 0 0 0 O3 O2 O1 O0 0 0 1 0 0 0 0 1 O7 O6 O5 O4 0 0 1 0 0 0 1 0 O11 O10 O9 O8 0 0 1 0 0 0 1 1 O15 O14 O13 O12 Setting the ON bit = 0 tristates the output. Setting the ON bit = 1 enables the output if the Global Output Enable bit is also set (the individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage). Setting the Gain The gain of each output may be set to x1 or x2 using the Gain Set word. It is in the same format as the output enable control word: TABLE 5. GAIN SET FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 0 0 0 G3 G2 G1 G0 0 1 0 0 0 0 0 1 G7 G6 G5 G4 0 1 0 0 0 0 1 0 G11 G10 G9 G8 0 1 0 0 0 0 1 1 G15 G14 G13 G12 Set GN = 0 for a gain of x1 or 1 for a gain of x2. Broadcast Mode The Broadcast Mode routes one input to all 16 outputs. The broadcast control word is: TABLE 6. BROADCAST FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 0 1 1 I3 I2 I1 I0 0 0 0 0 0 0 0 0 B0 Enable Broadcast 0: Broadcast Mode Disabled 1: Broadcast Mode Enabled I3:I0 form the 4 bit word indicating the input channel (0 to 15) to be sent to all 16 outputs. Set the Enable Broadcast bit (B0) = 1 to enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments are restored. Control Word The ISL59530’s power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the following control word should be sent: TABLE 7. CONTROL WORD FORMAT B15 B14 B13 B12 B11 B10 1 1 1 0 0 0 B9 B8 B7 B6 B5 B4 B3 B2 0 Clamp 0: Clamp Disabled 1: Clamp Enabled 0 0 0 0 0 0 B1 B0 Global Output Enable Power 0: All outputs tristated 0: Standby 1: Operational 1: Individual Output Enable bits control outputs The Clamp bit enables the input clamp function, forcing the AC-coupled signal’s most negative point to be equal to VREF. Note: The Clamp bit turns the DC-Restore clamp function on or off for all channels - there is no DC-Restore on/off control for individual channels. The DC-Restore function only works with signals with sync tips (composite video). Signals that do not have sync tips (the Chroma/C signal in s-video and the Pb, Pr signals in Component video), will be severely distorted if run through a DC-Restore/clamp function. 18 FN6220.1 June 12, 2006 ISL59530 For this reason, the ISL59530 must be in DC-coupled mode (Clamp Disabled) to be compatible with s-video and component video signals. Bandwidth Considerations Wide frequency response (high bandwidth) in a video system means better video resolution. Four sets of frequency response curves are shown in Figure 47. Depending on the switch configurations, and the routing (the path from the input to the output), bandwidth can vary between 100MHz and 350MHz. A short discussion of the trade-offs — including matrix configuration, output buffer gain selection, channel selection, and loading — follows. Linear Operating Region In addition to bandwidth optimization, to get the best linearity the ISL59530 should be configured to operate in its most linear operating region. Figure 48 shows the differential gain curve. The ISL59530 is a single supply 5V design with its most linear region between 0.1 and 2V. This range is fine for most video signals whose nominal signal amplitude is 1V. The most negative input level (the sync tip for composite video) should be maintained at 0.3V or above for best operation. 2 Mux, Av = 2 Normalized Gain [dB] 0 Mux, Av = 1 Broadcast, Av = 2 -2 Broadcast, Av = 1 -4 -6 -8 -10 1 10 100 Frequency [MHz] 1000 FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES In multiplexer mode, one input typically drives one output channel, while in broadcast mode, one input drives all 16 outputs. As the number of outputs driven increases, the parasitic loading on that input increases. Broadcast Mode is the worst-case, where the capacitance of all 16 channels loads one input, reducing the overall bandwidth. In addition, due to internal device compensation, an output buffer gain of x2 has higher bandwidth than a gain of x1. Therefore, the highest bandwidth configuration is multiplexer mode (with each input mapped to only one output) and an output buffer gain of x2. The relative locations of the input and output channels also have significant impact on the device bandwidth (due to the layout of the ISL59530 silicon). When the input and output channels are further away, there are additional parasitics as a result of the additional routing, resulting in lower bandwidth. FIGURE 48. DIFFERENTIAL GAIN RESPONSE In a DC-coupled application, it is the system designer’s responsibility to ensure that the video signal is always in the optimum range. When AC coupling, the ISL59530’s DC restore function automatically adjusts the DC level so that the most negative portion of the video is always equal to VREF. A discussion of the benefits of the DC-restored system begins by understanding the block diagram of a typical DCrestore circuit (Figure 49). It consists of 4 sections: an AC coupling (DC blocking) capacitor at the input, an opamp, a FET switch, and a current source. In the absence of an input signal, RTERM pulls the input node to ground. The 2µA current source slowly drains the input capacitor of charge, slowly lowering VOUT. However when VOUT goes below VREF, Q1 turns on, sourcing current into the capacitor until VOUT is equal to VREF, at which point Q1 will turn off. So with no VIN signal, the voltage at the noninverting input of the opamp will settle to approximately VREF, with Q1 sourcing the same 2µA as the current source. The bandwidth does not change significantly with resistive loading as shown in the typical performance curves. However several of the curves demonstrate that frequency response is sensitive to capacitance loading. This is most significant when laying out the PCB. If the PCB trace length between the output of the crosspoint switch and the backtermination resistor is not minimized, the additional parasitic capacitance will result in some peaking and eventually a reduction in overall bandwidth. 19 FN6220.1 June 12, 2006 ISL59530 0.086µF. Figure 50 shows the result of CIN = 0.1µF delivering acceptable droop and CIN = 0.001µF producing excessive droop VS VREF + Q1 VOUT VIN RTERM CIN 2uA FIGURE 49. DC RESTORE BLOCK DIAGRAM When a video signal is applied to VIN, the most negative signal will be the sync tip. If the sync tip goes below VREF, Q1 will turn on and quickly source enough current into CIN so that the sync tip is forced to be equal to VREF. After the sync tip, the video jumps up by 300mV or more, so VOUT becomes >> VREF, so Q1 will not turn on for the rest of the video line. However the 2µA current source continues to slowly discharge CIN, so that by the end of the video line, the next sync tip will again be slightly below VREF, forcing Q1 to source some current into C1 to make VOUT = VREF during the sync tip. This is how the video is “DC-restored” after being AC coupled into the ISL59530. The sync tip voltage will be equal to VREF, on the right side of CIN, regardless of the DC level of the video on the left side of CIN. Due to various sources of offset in the actual clamp function, the actual sync tip level is typically about 75mV higher than VREF (for VREF = 0.5V). . When the clamp function is disabled in the CONTROL register (Clamp = 0) to allow DC-coupled operation, the ICLAMP current sinks/sources are disabled and the input passes through the DC Restore block unaffected. In this application VREF may be tied to GND. Overlay Operation The ISL59530 features an overlay feature, that allows an external video signal or DC level to be inserted in place of that output channel’s video. When the OVERN signal is taken high, the output signal on the OUTN pin is replaced with the signal on the VOVERN pin. There are several ways the overlay feature can be used. Toggling the OVERN signal at the frame rate or slower will replace the video frame(s) on the OUTN pin with the video supplied on the VOVERN pin. Another option (for OSD displays, for example), is to put a DC level on the VOVERN line and toggle the OVERN signal at the pixel rate to create a monocolor image “overlaid” on channel N’s output signal. Finally, by enabling the OVERN signal for some portion of each line over a certain amount of lines, a picture-in-picture function can be constructed. It’s important to note that the overlay inputs do not have the DC Restore function previously described - the overlay signal is DC coupled into the output. It is the system designer’s responsibility to ensure that the video levels are in the ISL59530’s linear region and matching the output channel’s offset and amplitude. One easy way to do this is to run the video to be overlaid through one of the ISL59530’s unused channels and then into the VOVERN input. The OVERN pins all have weak pulldowns, so if they are unused, they can either be left unconnected or tied to GND. Power Dissipation and Thermal Resistance FIGURE 50. DC RESTORE VIDEO WAVEFORMS It is important to choose the correct value for CIN. Too small a value will generate too much droop, and the image will be visibly darker on the right than on the left. A CIN value that is too large may cause the clamp to fail to converge. The droop rate (dV/dt) is iPULLDOWN/CIN volts/second. In general, the droop voltage should be limited to <1 IRE over a period of one line of video; so for 1 IRE = 7mV, IB = 10µA maximum, and an NTSC waveform we will set CIN > 10µA*60µs/7mV = 20 With a large number of switches, it is possible to exceed the 150°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------Θ JA FN6220.1 June 12, 2006 ISL59530 Where: • TJMAX = Maximum junction temperature = 125°C • TAMAX = Maximum ambient temperature = 85°C • θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: n V OUTi ∑ ( VS – VOUTi ) × ---------------R Li PD MAX = V S × I SMAX + i=1 Where: • VS = Supply voltage = 5V • ISMAX = Maximum quiescent supply current = 360mA • VOUT = Maximum output voltage of the application = 2V • RLOAD = Load resistance tied to ground = 150 • n = 1 to 16 channels n PD MAX = V S × I SMAX + V OUTi -= ∑ ( VS – VOUTi ) × ---------------R Li 2.44W i=1 The required θJA to dissipate 2.44W is: T JMAX – T AMAX Θ JA = --------------------------------------------- = 16.4 ( °C/W ) PD MAX Table 8 shows θJA thermal resistance results with a Wakefield heatsink and without heatsink and various airflow. At the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature. TABLE 8. θJA THERMAL RESISTANCE [°C/W] Airflow [LFM] 0 250 500 750 No Heatsink 18 14.3 13.0 12.6 Wakefield 658-25AB Heatsink 16.0 7.0 6.0 4.7 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN6220.1 June 12, 2006 356 Ld PBGA Package 22 ISL59530 FN6220.1 June 12, 2006