ISL59531 ® Data Sheet PRELIMINARY March 21, 2006 16x16 Video Crosspoint with Differential Inputs The ISL59531 is a 16x16 integrated video crosspoint switch matrix with differential input and On-Screen Display (OSD) insertion. The ISL59531 is ideal for routing video signals in security and video-on-demand systems. This device operates from a single +5V supply. Any output of the 16 video inputs cable can be switched to any of the 16 outputs. OSD information can be inserted into any output through an internal, dedicated fast 2:1 mux (15ns switching times) located before the output buffer. Also, any input can be broadcast to all 16 outputs. Each output can be tri-stated and its gain set to +1 or +2 through the SPI interface. Features • 16x16 non-blocking switch with differential inputs and outputs • Operates from a single +5V supply • Output gain switchable +1 or +2 • SPI digital interface • Tri-state output • -90dB Isolation at 6MHz • 0.025%/0.05° dG/dP • Pb-free plus anneal available (RoHS compliant) The ISL59531 offers a -3dB signal bandwidth of 320MHz. The differential gain and differential phase of 0.025%, along with 0.1dB flatness out to 50MHz, making the ISL59531 suitable for many video applications. Applications The switch matrix configuration and output buffer gain are programmed through an SPI/QSPI™-compatible three-wire serial interface. The ISL59531 interface is set up to facilitate both fast updates and initialization. On power-up, all outputs are initialized in the disabled state to avoid output conflicts within the user system. The ISL59531 has single-supply signal operation. It can accommodate input common mode voltages from 0V to 3.5V and 0V to 4V at the outputs. • HDTV routing The ISL59531 is available in a 356-pin BGA package and specified over an extended -40°C to +85°C temperature range. The ISL59530 is a single-ended input version of this device. For capacitor-coupled applications, the ISL59530 inputs include a clamp circuit that restores the input level to an externally applied reference. 1 FN6251.0 • Security camera switching • RGB routing Ordering Information PART NUMBER ISL59531IKZ (See Note) TAPE & REEL - PACKAGE 356-Pin BGA (Pb-free) PKG. DWG. # V356.27x27 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59531 Pinout ISL59531 (356-PIN BGA) TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A In12 In13 In14 In15 Over15 Over14 Out13 Out12 Inb12 Inb13 Inb14 Inb15 Out15 Out14 Over13 Over12 Vover15 Vover14 Vover13 Vover12 B C D In11 Inb11 Vlogic Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vover11 Out11 Over11 E Vs Vs F In10 Inb10 Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Vover10Out10 Over10 Sout Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Inb9 Reset Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Vover9 Over9 Out9 Senb Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Inb8 Clock Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Vover8 Over8 Out8 Sdi Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Ref Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Vover7 Out7 Over7 Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Vover6 Out6 Over6 Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs G H In9 J K In8 L M In7 Inb7 N P In6 Inb6 R T In5 Inb5 Vs Vs Vover5 Over5 Out5 U Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs V In4 Inb4 Spare1 Spare0 Diode Vover0 Vover1 Vover2 Vover3 Vover4 Over4 Out4 W Inb3 Inb2 Inb1 Inb0 Over0 Over1 Out2 Out3 In3 In2 In1 In0 Out0 Out1 Over2 Over3 Y = Empty location (unpopulated) = Ballgrid Pad name "GND" is the same as package or ball name "ground" or "G" Pad name "VS" is the same as package or ball name "power" or "P" Pad X, Y is from pad center. All pads are 70µ by 70µ 2 FN6251.0 March 21, 2006 ISL59531 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 5.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VS = 5V DESCRIPTION CONDITION MIN TYP MAX UNIT 4.5 5.5 V 5.5 V VS Supply Range VD Digital Supply Establishes serial output high level 1.2 AV Gain AV = 1, RL = 500Ω 0.97 1 1.03 V/V AV= 2, RL = 150Ω 1.94 2 2.06 V/V AV = 1 -1.5 1 1.5 % 0.5 1.0 % GM Gain Matching (to average of all other outputs) AV = 2 VIN Input Voltage Range AV = 1 0 3.5 V VOUT Output Voltage Range AV = 2, RL = 150Ω 0 4.0 V IB Input Bias Current VOS Output Offset Voltage IOUT Output Current PSRR Power Supply Rejection Ratio IS Supply Current -10 -5 0 µA AV = 1 -25 0 25 mV AV = 2 -70 0 70 mV Sourcing, RL = 10Ω to GND 60 100 mA Sinking, RL to 2.5V 25 35 mA 80 dB Enabled, all outputs enable, no load current 312 Enable, all outputs disable, no load current 140 Disabled 0.8 Supply current per output channel 375 mA mA 1.1 mA 7 mA AC Electrical Specifications PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT BW -3dB 3dB Bandwidth VOUT = 200mVP-P, AV = 2 320 MHz BW 0.1dB 0.1dB Bandwidth VOUT = 200mVP-P, AV = 2 50 MHz SR Slew Rate VOUT = 2VP-P, AV = 2 520 V/µs TS Settling Time to 0.1% VOUT = 2VP-P, AV = 2 12 ns Glitch Switching Glitch, Peak AV = 1 40 mV Tover Overlay Delay Time Beginning of output transition 6 ns dG Diff Gain AV = 2, RL = 150Ω 0.025 % dP Diff Phase AV = 2, RL = 150Ω 0.05 ° Xt Hostile Crosstalk 6MHz -85 dB VN Input Noise Voltage 42 nV/√Hz 3 360 FN6251.0 March 21, 2006 ISL59531 Pin Descriptions (Continued) Pin Descriptions NAME NUMBER DESCRIPTION INB2 W4 Complementary input IN2 Y4 Input INB3 W2 Complementary input IN3 Y2 Input REF M3 Output reference GND GND SDI L3 Serial data input VS VS Power supply INB4 V2 Complementary input IN4 V1 Input INB5 T2 Complementary input IN5 T1 Input VS VS Power supply GND GND Ground INB6 P2 Complementary input IN6 P1 Input INB7 M2 Complementary input IN7 M1 Input CLOCK K3 Serial data clock VS VS Power supply SENB J3 Serial enable-inverted GND GND INB8 K2 Complementary input IN8 K1 Input INB9 H2 Complementary input IN9 H1 Input VS VS Power supply GND GND INB10 F2 Complementary input IN10 F1 Input INB11 D2 Complementary input IN11 D1 Input RESET H3 Reset input VS VS Power supply SOUT G3 Serial data output GND GND INB12 B1 Complementary input IN12 A1 Input INB13 B3 Complementary input Ground Ground Ground Ground 4 NAME NUMBER DESCRIPTION IN13 A3 INPUT TEST BAR NONE GND GND Ground GND GND Ground VS VS Power supply VS VS Power supply VLOGIC D3 Logic power supply for serial output driver INB14 B5 Complementary input IN14 A5 Input INB15 B7 Complementary input IN15 A7 Input VSL VS Power supply VGL GND VS VS GND GND Ground OVER15 A11 Overlay logic control VOVER15 C11 Overlay analog input OUT15 B11 Output OVER14 A13 Overlay logic control VOVER14 C13 Overlay analog input OUT14 B13 Output GND GND Ground VS VS Power supply OUT13 A15 Output VOVER13 C15 Overlay analog input OVER13 B15 Overlay logic control OUT12 A17 Output VOVER12 C17 Overlay analog input OVER12 B17 Overlay logic control GND GND Ground OUT TEST 3 NONE VS VS Power supply OVER11 D20 Overlay logic control VOVER11 D18 Overlay analog input OUT11 D19 Output OVER10 F20 Overlay logic control VOVER10 F18 Overlay analog input OUT10 F19 Output Input Manufacturing test pin - leave open Ground Power supply Manufacturing test pin - leave open FN6251.0 March 21, 2006 ISL59531 Pin Descriptions (Continued) Pin Descriptions (Continued) NAME NUMBER DESCRIPTION NAME NUMBER GND GND VOVER0 V10 Overlay analog input VS VS Power supply OVER0 W10 Overlay logic control OUT9 H20 Output VS VS VOVER9 H18 Overlay analog input OUT TEST 0 NONE OVER9 H19 Overlay logic control GND GND OUT8 K20 Output IN0 Y8 Input VOVER8 K18 Overlay analog input INB0 W8 Complementary input OVER8 K19 Overlay logic control IN1 Y6 Input OUT TEST 2 NONE INB1 W6 Complementary input GND GND DIODE V9 VS VS Anode of a ground-connected diode: useful for measuring die temperature OVER7 M20 Overlay logic control VS VS Power supply VOVER7 M18 Overlay analog input GND GND OUT7 M19 Output VS VS OVER6 P20 Overlay logic control GND GND VOVER6 P18 Overlay analog input SPARE0 V6 Not assigned-do not connect OUT6 P19 Output SPARE1 V5 Not assigned-do not connect GND GND Ground VS VS Power supply OUT5 T20 Output VOVER5 T18 Overlay analog input OVER5 T19 Overlay logic control OUT4 V20 Output VOVER4 V18 Overlay analog input OVER4 V19 Overlay logic control VS VS Power supply OUT TEST 1 NONE GND GND Ground OVER3 Y16 Overlay logic control VOVER3 V16 Overlay analog input OUT3 W16 Output OVER2 Y14 Overlay logic control VOVER2 V14 Overlay analog input OUT2 W14 Output VS VS GND GND Ground OUT1 Y12 Output VOVER1 V12 Overlay analog input OVER1 W12 Overlay logic control OUT0 Y10 Output Ground Manufacturing test pin - leave open Ground Power supply DESCRIPTION Power supply Manufacturing test pin - leave open Ground Ground Power supply Ground Manufacturing test pin - leave open Power supply 5 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves Vs=+5V AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 15pF VS=+5V AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 10pF 15pF 10pF 4.7pF 4.7pF 0pF 0pF FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, MUX MODE VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0 150Ω 50Ω FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, MUX MODE VS=+5V AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0 150Ω 50Ω 500Ω 500Ω 1.03kΩ 1.03kΩ FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, MUX MODE FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, MUX MODE Overlay mode AV = 2 RL = 100Ω CL=0pF INPUT_CH 15 OUTPUT_CH 15 Overlay mode AV = 1 RL = 100Ω CL=0pF INPUT_CH 15 OUTPUT_CH 31 FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 1 6 FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 2 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves (Continued) VS=+5V AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 VS=+5V AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 15pF 15pF 10pF 10pF 4.7pF 4.7pF 0pF 0pF FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, BROADCAST MODE VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0 150Ω 50Ω FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, BROADCAST MODE VS=+5V AV = 2 CL = 0pF INPUT_CH 0 OUTPUT_CH 0 503Ω 50Ω 150KΩ 503kΩ 1.03KΩ 1.03kΩ FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, BROADCAST MODE AV = 1 RL = 100Ω CL = 0 AV = 2 RL = 100Ω CL = 0 ADJACENT INPUT_CH14 OUTPUT_CH15 ALL HOSTILE INPUT_CH0 OUTPUT_CH31 FIGURE 11. CROSSTALK - AV = 1 7 FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, BROADCAST MODE ADJACENT INPUT_CH14 OUTPUT_CH15 ALL HOSTILE INPUT_CH0 OUTPUT_CH15 FIGURE 12. CROSSTALK - AV = 2 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves (Continued) THD VS=+5V AV=2 RL=100Ω INPUT_CH 0 OUTPUT_CH 0 FREQUENCY = 1MHz THD 2nd HD 2nd HD 3rd HD VS=+5V AV=2 RL=100Ω INPUT_CH 0 OUTPUT_CH 0 VOP-P =2V 3rd HD FIGURE 13. HARMONIC DISTORTION vs FREQUENCY FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P FIGURE 15. DISABLE OUTPUT IMPEDANCE FIGURE 16. ENABLE OUTPUT IMPEDANCE MUX MODE AV = 1 RL = 100Ω INPUT_CH 15 OUTPUT_CH 15 FALL TIME 2.65ns RISE TIME 2.35ns FIGURE 17. RISE TIME - AV = 1 8 MUX MODE AV = 1 RL = 100Ω INPUT_CH 15 OUTPUT_CH 15 FIGURE 18. FALL TIME - AV = 1 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves (Continued) MUX MODE AV = 2 RL = 100Ω INPUT_CH 15 OUTPUT_CH 15 FALL TIME 2.35ns RISE TIME 2.19ns FIGURE 19. RISE TIME - AV = 2 MUX MODE AV = 2 RL = 100Ω INPUT_CH 15 OUTPUT_CH 15 FIGURE 20. FALL TIME - AV = 2 MUX MODE AV = 1 RL=100Ω INPUT_CH 15 OUTPUT_CH 15 SLEW RATE -436V/µs SLEW RATE 448V/µs MUX MODE AV = 1 RL=100Ω INPUT_CH 15 OUTPUT_CH 15 FIGURE 21. RISING SLEW RATE - AV = 1 FIGURE 22. FALLING SLEW RATE - AV = 1 MUX MODE AV = 2 RL=100Ω INPUT_CH 15 OUTPUT_CH 15 SLEW RATE -511V/µs SLEW RATE 531V/µs MUX MODE AV = 2 RL=100Ω INPUT_CH 15 OUTPUT_CH 15 FIGURE 23. RISING SLEW RATE - AV = 2 9 FIGURE 24. FALLING SLEW RATE - AV = 2 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves (Continued) OUTPUT OUTPUT OVERLAY LOGIC INPUT FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME OVERLAY LOGIC INPUT FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME AV = 2 RL = 150Ω INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV FIGURE 27. DIFFERENTIAL GAIN, AV = 2 AV = 2 RL = 150Ω INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV FIGURE 28. DIFFERENTIAL PHASE, AV = 2 AV = 2 RL = 150Ω INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV FIGURE 29. DIFFERENTIAL GAIN, AV = 2 10 FIGURE 30. DIFFERENTIAL PHASE, AV = 2 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves (Continued) AV = 1 RL = 150Ω INPUT_CH 15 OUTPUT_CH15 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV FIGURE 31. DIFFERENTIAL GAIN, AV = 1 AV = 1 RL = 150Ω INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV FIGURE 32. DIFFERENTIAL PHASE, AV = 1 AV = 1 RL = 150Ω INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV FIGURE 33. DIFFERENTIAL GAIN, AV = 1 AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV FIGURE 34. DIFFERENTIAL GAIN, AV = 1 AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV FIGURE 35. DIFFERENTIAL GAIN, AV = 2 11 FIGURE 36. DIFFERENTIAL PHASE, AV = 2 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves (Continued) AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV FIGURE 37. DIFFERENTIAL GAIN, AV = 2 FIGURE 38. DIFFERENTIAL PHASE, AV = 2 AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV FIGURE 39. DIFFERENTIAL GAIN, AV = 1 FIGURE 40. DIFFERENTIAL PHASE, AV = 1 AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV FIGURE 41. DIFFERENTIAL GAIN, AV = 1 12 FIGURE 42. DIFFERENTIAL PHASE, AV = 1 FN6251.0 March 21, 2006 ISL59531 Typical Performance Curves (Continued) AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2 FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2 AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1 13 FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1 FN6251.0 March 21, 2006 ISL59531 3dB Bandwidth, MUX Mode, AV = 1, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 255 229 229 210 222 221 224 190 169 152 233 190 212 189 207 166 1 244 217 180 168 193 160 2 257 186 171 3 264 183 175 4 255 174 177 5 253 176 177 6 247 226 171 178 157 7 253 227 235 218 223 228 230 174 184 163 240 223 219 217 211 178 8 255 236 240 239 223 236 231 175 187 168 241 242 222 235 213 183 9 241 210 169 188 165 10 235 11 223 12 220 13 211 14 199 212 15 193 217 235 217 220 218 236 207 209 214 207 202 185 216 186 168 186 164 188 161 192 160 192 160 194 222 197 204 169 219 171 202 167 237 173 170 182 230 185 225 186 205 185 224 177 225 217 198 223 189 197 193 197 238 3dB Bandwidth, MUX Mode, AV = 2, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 295 316 290 397 384 405 395 220 288 240 299 250 385 234 396 188 1 268 290 2 277 3 279 4 269 5 263 6 259 7 263 411 307 402 387 8 262 407 308 402 383 9 253 10 253 300 408 391 407 11 246 241 13 236 14 233 279 15 227 274 14 192 392 196 402 192 196 196 283 412 398 201 205 407 307 402 387 413 398 211 412 394 203 212 411 300 403 385 415 394 216 388 194 210 410 194 215 272 367 196 201 183 196 201 385 396 213 291 289 196 412 244 183 192 404 417 12 211 216 407 230 187 213 184 216 182 220 178 220 183 223 298 200 200 214 293 216 412 217 391 225 419 324 276 400 379 413 225 396 230 385 293 FN6251.0 March 21, 2006 ISL59531 3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 215 198 195 183 184 188 172 178 151 145 157 145 140 146 144 158 1 214 195 174 152 144 158 2 210 171 153 3 212 171 157 4 206 169 157 5 203 165 159 6 201 156 163 159 151 7 204 187 182 170 170 175 160 167 167 156 168 157 151 158 154 170 8 204 187 183 172 171 176 161 167 171 160 172 160 155 161 159 175 9 202 157 164 170 160 10 196 11 194 12 193 13 191 14 189 172 15 187 173 188 178 174 177 170 161 162 170 167 157 155 161 149 160 169 157 171 156 171 151 174 151 175 153 178 147 159 143 164 150 164 161 164 164 174 169 178 160 174 156 178 164 167 179 167 178 162 178 160 166 164 181 3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100Ω [MHz] OUTPUT CHANNELS INPUT CHANNELS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 234 216 209 199 204 205 190 196 169 160 172 162 158 163 161 178 1 232 215 193 169 161 178 2 228 189 171 3 229 191 175 4 223 186 177 5 219 183 177 6 217 174 181 178 167 7 220 204 198 189 190 192 175 183 184 173 184 174 169 174 172 189 8 220 205 199 190 191 193 177 184 187 178 188 178 173 178 178 193 9 218 174 181 188 178 10 220 176 186 11 212 174 188 174 192 170 192 204 196 193 192 185 179 12 211 13 209 179 14 208 191 15 205 191 187 184 172 171 15 176 160 167 194 166 197 164 178 163 182 168 183 177 183 183 193 187 192 177 192 176 195 181 185 195 184 179 185 195 181 196 182 198 FN6251.0 March 21, 2006 ISL59531 Block Diagram VS+ VOVERn 16 OVERLAY INPUT + VIN0 POWER-ON 16 INPUTS OVERn 16 LOGIC CONTROL SWITCH MATRIX 16 OUTPUTS + VIN15 REF AV +1, +2 SDI CLK ENA SPI INTERFACE, REGISTER General Description The ISL59531 is a 16x16 integrated video crosspoint switch matrix with differential input and output buffers and OnScreen Display (OSD) insertion. This device operates from a single +5V supply. Any output can be switched to any of the 16 input video signal sources and OSD information through an internal, dedicated fast 2:1 mux located before the output buffer. Also, any one input can be broadcast to all 16 outputs. Each output X is defined as: OUTPUT ENABLE POWER-ON SDO ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The LSB (bit 0) is loaded first and the MSB (bit 15) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals. Voutx = Avx*(INx-INBx+REF) Where Avx = 1, or Avx = 2. Note that all REF’s are common between channels and must be externally well buffered and/or bypassed. The ISL59531 offers a -3dB signal bandwidth of 320MHz. The differential gain and differential phase of 0.025% and 0.05° respectively, along with 0.1dB flatness out to 50MHz. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPI™-compatible, three-wire serial interface. The ISL59531 interface is set up to facilitate both fast updates and initialization. On power-up, all facilities are initialized in the disabled state to avoid output conflicts within the user system. Digital Interface The ISL59531 uses a simple 3-wire SPI compliant digital interface to program the outputs. The ISL59531 can support the clock rate up to 5MHz. Serial Interface The ISL59531 is programmed through a three-wire serial interface. The start and stop conditions are defined by the 16 FN6251.0 March 21, 2006 ISL59531 Serial Timing Diagram tE ENA T tr tf tHE tSE SCLK tSD SDI tHD B0 tw B1 B2 B14 B12-B2 B15 t LSB MSB LOAD MSB FIRST, LSB LAST TABLE 1. SERIAL TIMING PARAMETERS PARAMETER RECOMMENDED OPERATING RANGE DESCRIPTION T ≥200ns Clock Period tHE ≥20ns ENA Hold Time tSE ≥20ns ENA Setup Time tHD ≥20ns Data Hold Time tSD ≥20ns Data Setup Time tW 0.50 * T Clock Pulse Width Programming Model The device has power-on reset that disables outputs, disables test mode, and turns off analog currents. To start up the device the control word is sent: TABLE 2. CONTROL WORD FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 - - - - 0 --0 0 0 0 0 0 Power on Common output enable It is important to always program control bits 2-8 as zeros to avoid activating test modes designed for device manufacturing.The clamp bit activates the input clamp and bleed current sink and works only in the single-ended version. To enable individual outputs, the output enable control word is sent. There are 16 enables to set; this is done with serial words controlling four at a time. The output enable control word format is: TABLE 3. OUTPUT ENABLE FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 - - - N1 N0 - On+3 - On+2 - On+1 - On The Ox bits represent output enables of eight individual registers. The N1 and N0 bits represent a two bit binary number which is used in setting n = 2N1N0. For instance, to access the control bit of the 5th output enable, we send the word: TABLE 4. OUTPUT ENABLE WORD OF 2ND GROUP OF OUTPUTS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 - - - 0 1 - O7 - O6 - 1 - O4 Individual output enables are ended with the control register’s common output enable bit and the power on bit. 17 FN6251.0 March 21, 2006 ISL59531 Gain Setting The gain of each output may be set to 1 or 2 using the gain set word. It is in the same format as the output enable control word: TABLE 5. GAIN SET FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 - - - N1 N0 - Gn+3 - Gn+2 - Gn+1 - Gn Input to Output Selection Individual outputs receive their input selection choice using the input/output control word. Its format is: TABLE 6. INPUT/OUTPUT WORD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 I3 I2 I1 I0 0 - - - O3 O2 O1 O0 0 For a given binarily selected output, as specified by the O's, an input channel is assigned by the binarily selected I's. Sixteen transmissions of the input/output control words will be required to set up all outputs. Note that B8 and B0 must be logic 0. Broadcast Mode The broadcast mode routs one input to all 16 outputs. It has a memory bit that remembers its state. The configuration of input/output assignments that existed before setting broadcast mode is kept in memory and when broadcast mode is disabled the previous configuration is restored. The broadcast control word format is: TABLE 7. BROADCAST WORD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 1 I3 I2 I1 I0 0 - - - - - - - EB EB sets or resets the broadcast mode memory bit. The I's binarily select the input channel to be broadcast to all outputs. Note that B8 must be logic 0. Bandwidth Considerations Wide frequency response (high bandwidth) in a video system means better video resolution. Four sets of frequency response curves are shown in Figure 47. Depending on the switch configurations, one can get between 250MHz to 350MHz bandwidth. A short discussion of the trade-offs follows—including matrix configuration, output buffer gain selection, channel selection, and loading. 2 Mux, Av = 2 Normalized Gain [dB] 0 Mux, Av = 1 Broadcast, Av = 2 -2 Broadcast, Av = 1 -4 -6 -8 -10 1 10 100 Frequency [MHz] 1000 FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES In multiplexer mode, the input only drives one output channel, while in broadcast mode the same input drives all 16 outputs. The parasitic capacitance of all 16 channels loads down the input and reduces bandwidth in broadcast 18 mode. In addition, output buffer gain of +2 has higher bandwidth than gain of +1 due to internal device compensation. Therefore, the highest bandwidth set-up is multiplexer mode and output buffer gain of +2. The relative location of the input and output channel also has significant impact on the device bandwidth. Again this is due to the layout of the device. When the input and output channels are further away, there are additional parasitics as a result of the distance and lower bandwidth results. The bandwidth does not change significantly with resistive loading as shown in figure 3 in the typical performance curves. However, it does change greatly with capacitance loading, Figure 4 in typical performance curves. This is most significant when laying out the PCB. If the PCB trace between the output of the crosspoint switch and the back termination resistor is not minimized, additional parasitic capacitance severely distorts the frequency response. To emphasize how critical the PCB layout is to performance, let’s compare the two boards presented in figures 48 and 49. Figure 48 shows a larger engineering evaluation board where the termination resistor is far away from the device because of the use of a socket. The board in figure 48 is a demoboard without the socket. The parasitic capacitance of the demoboard is about 2.7pF less. ISL59531 Linear Operating Region In addition to bandwidth, one must also be very careful with operating the device at its linear operating region. Figure 50 shows differential gain curve. The ISL59534 is a single supply 5V device with its linear region is between 0.1 and 2V. FIGURE 48. ENGINEERING EVALUATION BOARD FIGURE 50. DIFFERENTIAL GAIN RESPONSE Power Dissipation and Thermal Resistance With a large number of switches, it is possible to exceed the 150°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------Θ JA Where: • TJMAX = Maximum junction temperature = 125°C FIGURE 49. CUSTOMER DEMOBOARD • TAMAX = Maximum ambient temperature = 85°C • θJA = Thermal resistance of the package To prove that the parasitic capacitance is the largest contributor to the difference in bandwidth of the two boards, we added 2.7pF at the output of the demoboard. Figure 50 shows the similarity in frequency response of the engineering evaluation board alongside the demoboard piggybacked with 2.7pF. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: n PD MAX = V S × I SMAX + i=1 19 V OUTi ∑ ( VS – VOUTi ) × ---------------R Li ISL59531 Where: • VS = Supply voltage = 5V • ISMAX = Maximum quiescent supply current = 375mA • VOUT = Maximum output voltage of the application = 2V • RLOAD = Load resistance tied to ground = 150 • n = 1 to 15 channels n PD MAX = V S × I SMAX + V OUTi -= ∑ ( VS – VOUTi ) × ---------------R Li 2.52W i=1 The reqired θJA to dissipate 2.52W is: T JMAX – T AMAX Θ JA = --------------------------------------------- = 15.9 ( °C/W ) PD MAX Table 8 shows θJA thermal resistance results for various airflows. At the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature. TABLE 8. θJA THERMAL RESISTANCE [°C/W] Airflow [LFM] 0 250 500 750 18 14.3 13.0 12.6 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 356 Ld PBGA Package 21 ISL59531