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Data
October 10, 2011
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1-88
ISL59534
FN6249.7
32x16 Video Crosspoint
Features
The ISL59534 is a 300MHz 32x16 Video Crosspoint Switch.
Each input has an integrated DC-restore clamp and an input
buffer. Each output has a fast On-Screen Display (OSD)
switch (for inserting graphics or other video) and an output
buffer. The switch is non-blocking, so any combination of
inputs to outputs can be chosen, including one channel
driving multiple outputs. The Broadcast Mode directs one
input to all 16 outputs. The output buffers can be individually
controlled through the SPI interface, the gain can be
programmed to +1 or +2, and each output can be placed into
a high impedance mode.
• 32x16 non-blocking switch with buffered inputs and
outputs
• 300MHz typical bandwidth
• 0.025%/0.05° dG/dP
• Output gain switchable x1 or x2 for each channel
• Individual outputs can be put in a high impedance state
• -90dB Isolation at 6MHz
• SPI digital interface
• Single +5V supply operation
The ISL59534 offers a typical -3dB signal bandwidth of
300MHz. Differential gain of 0.025% and differential gain of
0.05°, along with 0.1dB flatness out to 50MHz, make the
ISL59534 suitable for many video applications.
• Pb-free (RoHS compliant)
Applications
• Security camera switching
The switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible three-wire
serial interface. The ISL59534 interface is designed to
facilitate both fast updates and initialization. On power-up, all
outputs are high impedance to avoid output conflicts.
• RGB routing
• HDTV routing
Ordering Information
The ISL59534 is available in a 356 ball HBGA package and
specified over an extended -40°C to +85°C temperature range.
PART NUMBER
(Note)
The single-supply ISL59534 can accommodate input signals
from 0V to 3.5V and output voltages from 0V to 3.8V. Each
input includes a clamp circuit that restores the input level to
an externally applied reference in AC-coupled applications.
ISL59534IKEZ
PART
MARKING
PACKAGE
(Pb-Free)
ISL59534IKEZ 356 Ld HBGA
PKG.
DWG. #
V356.27x27C
NOTE: These Intersil Pb-free WLCSP and BGA packaged products
employ special Pb-free material sets; molding compounds/die attach
materials and SnAgCu - e1 solder ball terminals, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free WLCSP and BGA packaged products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
The ISL59535 is a fully differential input version of this device.
Block Diagram
VS
VOVERn
OVERn
16 OVERLAY
VIDEO INPUTS
VREF
16 OVERLAY
CHANNEL
ENABLES
CLAMP
32 VIDEO
INPUTS
IN0 - IN31
16 VIDEO
OUTPUTS
OUT0 – OUT15
32x16
SWITCH
MATRIX
CLAMP
CLAMP
ENABLE
SDI
SCLK
SLATCH
1
SPI INTERFACE AND
CONTROL REGISTERS
AV
X1, X2
OUTPUT
ENABLE
VSDO
SDO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
Copyright © Intersil Americas Inc. 2006, 2007, 2011. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59534
Pinout
ISL59534
(356 LD HBGA)
TOP VIEW
A
In24
In25
In26
In27
In28
In29
In30
In31
Over15
Over14
Out13
Out12
Out15
Out14
Over13
Over12
Vover15
Vover14
Vover13
Vover12
B
C
In23
D
VSDO
In22
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vover11 Out11
Over11
E
In21
Vs
Vs
In20
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
F
Vover10 Out10 Over10
G
In19
SDO
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In18
RESET
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In17
SLATCH
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In16
SCLK
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In15
SDI
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In14
VREF
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In13
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In12
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In11
Vs
GND GND GND GND GND GND GND GND GND GND
Vs
In10
Vs
In9
Vs
H
Vover9
Over9
Out9
Vover8
Over8
Out8
Vover7
Out7
Over7
Vover6
Out6
Over6
Vover5
Over5
Out5
Vover4
Over4
Out4
18
19
20
J
K
L
M
N
P
R
T
Vs
U
Vs
Vs
NC
NC
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
NC
Vover0
Vover1
Vover2
Vover3
Over0
Over1
Out2
Out3
Out0
Out1
Over2
Over3
Vs
V
In8
W
Y
In7
In6
In5
In4
In3
In2
In1
In0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
= NO BALLS
BALLS LABELLED “NC” SHOULD BE LEFT UNCONNECTED - DO NOT TIE THEM TO
GROUND!
BALLS WITH NO LABELS MAY BE TIED TO GROUND TO SLIGHTLY REDUCE
THERMAL IMPEDANCE.
2
FN6249.7
October 10, 2011
ISL59534
Absolute Maximum Ratings (TA = +25°C)
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 6.0V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA
Maximum power supply (VS) slew rate . . . . . . . . . . . . . . . . . . 1V/µs
Operating Conditions
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Information
JA (°C/W)
Thermal Resistance (Typical)
JC (°C/W)
356 Ld HBGA (Notes 1, 2) . . . . . . . . . .
24
13.1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For JC, the “case temp” location is taken at the package top center.
DC Electrical Specifications
PARAMETER
VS = 5V, RL = 150 unless otherwise noted.
DESCRIPTION
VS
Power Supply Voltage
VSDO
Power Supply for SDO output pin
AV
Gain (between all primary inputs and all
overlay inputs)
GM
Gain Matching (to average of all other
outputs)
CONDITION
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
4.5
5.5
V
Establishes serial data output high level
1.2
5.5
V
AV = 1
0.98
1
1.02
V/V
AV = 2
1.96
2
2.04
V/V
AV = 1
-1.5
+1.5
%
AV = 2
-1.5
+1.5
%
VIN
Video Input Voltage Range
AV = 1
0
3.5
V
VOUT
Video Output Voltage Range
AV = 2
0.1
3.8
V
IB
Input Bias Current
Clamp function disabled (DC coupled inputs)
-10
-5
1
µA
Clamp function enabled, VIN = VREF + 0.5V
0.5
2
10
µA
8
35
mV
40
mV
IREF
VREF Input Current
Clamp function enabled
VOS
Output Offset Voltage
AV = 1
-20
AV = 2
-100
-24
IOUT
Output Current
Sourcing, RL = 10to GND
60
108
mA
Sinking, RL = 10to 2.5V
24
31
mA
PSRR
Power Supply Rejection Ratio
AV = 2
50
70
dB
IS
Supply Current
AC Electrical Specifications
PARAMETER
BW -3dB
-110
µA
Enabled, all outputs enabled, no load current
385
445
505
mA
Enabled, all outputs disabled, no load current
280
320
360
mA
Disabled
1.2
1.8
2.4
mA
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
VS = 5V, RL = 150 unless otherwise noted.
DESCRIPTION
CONDITION
3dB Bandwidth
VOUT = 200mVP-P, AV = 2
BW 0.1dB
0.1dB Bandwidth
VOUT = 200mVP-P, AV = 2
SR
Slew Rate
VOUT = 2VP-P, AV = 2
300
MHz
50
300
520
MHz
740
V/µs
TS
Settling Time to 0.1%
VOUT = 2VP-P, AV = 2
12
ns
Glitch
Switching Glitch, Peak
AV = 1
40
mV
Tover
Overlay Delay Time
From OVER rising edge to output transition
6
ns
dG
Diff Gain
AV = 2, RL = 150
0.025
%
dP
Diff Phase
AV = 2, RL = 150
0.05
°
XTADJACENT
Adjacent Channel Crosstalk
6MHz, AV = 1
-90
dB
XTHOSTILE
Hostile Crosstalk
6MHz, AV = 1
-72
dB
3
FN6249.7
October 10, 2011
ISL59534
AC Electrical Specifications
PARAMETER
VN
VS = 5V, RL = 150 unless otherwise noted. (Continued)
DESCRIPTION
MIN
(Note 3)
CONDITION
TYP
Input Referred Noise Voltage
MAX
(Note 3)
18
UNIT
nV/Hz
NOTE:
3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Pin Descriptions (Continued)
Pin Descriptions
NAME
NUMBER
Crosspoint Video Input
OUT0
Y10
Crosspoint Video Output
Y7
Crosspoint Video Input
OUT1
Y12
Crosspoint Video Output
IN2
Y6
Crosspoint Video Input
OUT2
W14
Crosspoint Video Output
IN3
Y5
Crosspoint Video Input
OUT3
W16
Crosspoint Video Output
IN4
Y4
Crosspoint Video Input
OUT4
V20
Crosspoint Video Output
IN5
Y3
Crosspoint Video Input
OUT5
T20
Crosspoint Video Output
IN6
Y2
Crosspoint Video Input
OUT6
P19
Crosspoint Video Output
IN7
Y1
Crosspoint Video Input
OUT7
M19
Crosspoint Video Output
IN8
V1
Crosspoint Video Input
OUT8
K20
Crosspoint Video Output
IN9
U1
Crosspoint Video Input
OUT9
H20
Crosspoint Video Output
IN10
T1
Crosspoint Video Input
OUT10
F19
Crosspoint Video Output
IN11
R1
Crosspoint Video Input
OUT11
D19
Crosspoint Video Output
IN12
P1
Crosspoint Video Input
OUT12
A17
Crosspoint Video Output
IN13
N1
Crosspoint Video Input
OUT13
A15
Crosspoint Video Output
IN14
M1
Crosspoint Video Input
OUT14
B13
Crosspoint Video Output
IN15
L1
Crosspoint Video Input
OUT15
B11
Crosspoint Video Output
IN16
K1
Crosspoint Video Input
OVER0
W10
Overlay Logic Control (with pulldown)
IN17
J1
Crosspoint Video Input
OVER1
W12
Overlay Logic Control (with pulldown)
IN18
H1
Crosspoint Video Input
OVER2
Y14
Overlay Logic Control (with pulldown)
IN19
G1
Crosspoint Video Input
OVER3
Y16
Overlay Logic Control (with pulldown)
IN20
F1
Crosspoint Video Input
OVER4
V19
Overlay Logic Control (with pulldown)
IN21
E1
Crosspoint Video Input
OVER5
T19
Overlay Logic Control (with pulldown)
IN22
D1
Crosspoint Video Input
OVER6
P20
Overlay Logic Control (with pulldown)
IN23
C1
Crosspoint Video Input
OVER7
M20
Overlay Logic Control (with pulldown)
IN24
A1
Crosspoint Video Input
OVER8
K19
Overlay Logic Control (with pulldown)
IN25
A2
Crosspoint Video Input
OVER9
H19
Overlay Logic Control (with pulldown)
IN26
A3
Crosspoint Video Input
OVER10
F20
Overlay Logic Control (with pulldown)
IN27
A4
Crosspoint Video Input
OVER11
D20
Overlay Logic Control (with pulldown)
IN28
A5
Crosspoint Video Input
OVER12
B17
Overlay Logic Control (with pulldown)
IN29
A6
Crosspoint Video Input
OVER13
B15
Overlay Logic Control (with pulldown)
IN30
A7
Crosspoint Video Input
OVER14
A13
Overlay Logic Control (with pulldown)
IN31
A8
Crosspoint Video Input
OVER15
A11
Overlay Logic Control (with pulldown)
NAME
NUMBER
IN0
Y8
IN1
DESCRIPTION
4
DESCRIPTION
FN6249.7
October 10, 2011
ISL59534
Pin Descriptions (Continued)
DESCRIPTION
Pin Descriptions (Continued)
NAME
NUMBER
NAME
VOVER0
V10
Overlay Video Input
GND
VOVER1
V12
Overlay Video Input
NC
VOVER2
V14
Overlay Video Input
VOVER3
V16
Overlay Video Input
VOVER4
V18
Overlay Video Input
VOVER5
T18
Overlay Video Input
VOVER6
P18
Overlay Video Input
VOVER7
M18
Overlay Video Input
VOVER8
K18
Overlay Video Input
VOVER9
H18
Overlay Video Input
VOVER10
F18
Overlay Video Input
VOVER11
D18
Overlay Video Input
VOVER12
C17
Overlay Video Input
VOVER13
C15
Overlay Video Input
VOVER14
C13
Overlay Video Input
VOVER15
C11
Overlay Video Input
VREF
M3
DC-restore clamp reference input. In an
AC-coupled configuration (DC-Restore
clamp enabled), the sync tip of
composite video inputs will be restored
to this level. Set to 0.3 to 0.7V for
optimum performance.
In an DC-coupled configuration
(DC-Restore clamp disabled), this pin
should be tied to ground.
Do not let the VREF pin float! A
NUMBER
DESCRIPTION
Ground
No Connect - Do not electrically connect to anything, including ground.
floating VREF pin drifts high and, if the
clamp function is enabled, will cause all
of the outputs to simultaneously try to
drive ~4V DC into their 150 loads.
SLATCH
J3
Serial Latch. Serial data is latched into
ISL59534 on rising edge of SLATCH.
SCLK
K3
Serial data clock
SDI
L3
Serial data input
SDO
G3
Serial data output. Can be tied to SDI of
another ISL59534 to enable daisy-chaining of multiple devices.
RESET
H3
Reset input. Pull high then low to reset
device, but not needed in normal
operation. Tie to ground in final application.
VSDO
D3
Power supply for SDO pin. Tie to +5V
for a 0 to 5V SDO output signal swing.
VS
+5V power supply
5
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves
33pF
MUX MODE
AV = 1
RL = 100
INPUT_CH 0
OUTPUT_CH 0
MUX MODE
AV = 2
RL = 100
INPUT_CH 0
OUTPUT_CH 0
27pF
22pF
15pF
33pF
27pF
22pF
15pF
10pF
10pF
4.7pF
4.7pF
1pF
1pF
FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1,
MUX MODE
FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2,
MUX MODE
100
100
150
150
500
500
1.07k
MUX MODE
AV = 1
CL = 1pF
INPUT_CH 0
OUTPUT_CH 0
MUX MODE
AV = 2
CL = 1pF
INPUT_CH 0
OUTPUT_CH 0
FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1,
MUX MODE
OVERLAY MODE
AV = 1
RL = 100
CL = 1pF
INPUT_CH 31
OUTPUT_CH 31
1.07k
FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2,
MUX MODE
OVERLAY MODE
AV = 2
RL = 100
CL = 1pF
INPUT_CH 31
OUTPUT_CH 31
FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT,
AV = 1
6
FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT,
AV = 2
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves (Continued)
BROADCAST MODE
AV = 1
RL = 100
INPUT_CH 0
OUTPUT_CH 0
33pF
BROADCAST MODE
AV = 2
RL = 100
INPUT_CH 0
OUTPUT_CH 0
27pF
22pF
15pF
33pF
27pF
22pF
15pF
10pF
10pF
4.7pF
1pF
4.7pF
1pF
FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1,
BROADCAST MODE
FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2,
BROADCAST MODE
100
100
150
503
1.07k
BROADCAST MODE
AV = 2
CL = 1pF
INPUT_CH 0
OUTPUT_CH 0
BROADCAST MODE
AV = 1
CL = 1pF
INPUT_CH 0
OUTPUT_CH 0
FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1,
BROADCAST MODE
FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2,
BROADCAST MODE
-30
-30
CROSSTALK (dB)
-40
-50
-35
ALL HOSTILE IN_CH14
BROADCAST TO
ALL EXCEPT OUT_CH15
-40
ISOLATION (dB)
AV = 1
RL = 100
CL = 1pF
-60
-70
ADJACENT
IN CH14
OUT CH15
-80
-90
-100
10
100
FREQUENCY (MHz)
FIGURE 11. CROSSTALK - AV = 1
7
ALL HOSTILE IN_CH14
BROADCAST TO
ALL EXCEPT OUT_CH15
-50
-55
-60
-65
-70
1k
AV = 2
RL = 100
CL = 1pF
-45
-75
1
1.07k
-80
1M
ADJACENT
IN CH14
OUT CH15
10M
100M
FREQUENCY (Hz)
1G
FIGURE 12. CROSSTALK - AV = 2
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves (Continued)
AV = 2
RL = 100
INPUT_CH 0
OUTPUT_CH 0
VOP-P = 2V
THD
2nd HD
AV = 2
RL = 100
INPUT_CH 0
OUTPUT_CH 0
FREQUENCY = 1MHz
THD
2nd HD
3rd HD
3rd HD
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P
FIGURE 15. DISABLED OUTPUT IMPEDANCE
FIGURE 16. ENABLED OUTPUT IMPEDANCE
MUX MODE
AV = 1
RL = 100
INPUT_CH 31
OUTPUT_CH 31
FALL TIME
2.65ns
RISE TIME
2.35ns
FIGURE 17. RISE TIME - AV = 1
8
MUX MODE
AV = 1
RL = 100
INPUT_CH 31
OUTPUT_CH 31
FIGURE 18. FALL TIME - AV = 1
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves (Continued)
MUX MODE
AV = 2
RL = 100
INPUT_CH 31
OUTPUT_CH 31
FALL TIME
2.35ns
RISE TIME
2.19ns
FIGURE 19. RISE TIME - AV = 2
MUX MODE
AV = 2
RL = 100
INPUT_CH 31
OUTPUT_CH 31
FIGURE 20. FALL TIME - AV = 2
MUX MODE
AV = 1
RL = 100
INPUT_CH 31
OUTPUT_CH 31
SLEW RATE
-436V/µs
SLEW RATE
448V/µs
MUX MODE
AV = 1
RL = 100
INPUT_CH 31
OUTPUT_CH 31
FIGURE 21. RISING SLEW RATE - AV = 1
FIGURE 22. FALLING SLEW RATE - AV = 1
MUX MODE
AV = 2
RL = 100
INPUT_CH 31
OUTPUT_CH 31
SLEW RATE
-511V/µs
SLEW RATE
531V/µs
MUX MODE
AV = 2
RL = 100
INPUT_CH 31
OUTPUT_CH 31
FIGURE 23. RISING SLEW RATE - AV = 2
9
FIGURE 24. FALLING SLEW RATE - AV = 2
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves (Continued)
OUTPUT
OUTPUT
OVERLAY
LOGIC
INPUT
FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME
OVERLAY
LOGIC
INPUT
FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME
AV = 2
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
AV = 2
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 27. DIFFERENTIAL GAIN, AV = 2
FIGURE 28. DIFFERENTIAL PHASE, AV = 2
AV = 2
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
AV = 2
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 29. DIFFERENTIAL GAIN, AV = 2
10
FIGURE 30. DIFFERENTIAL PHASE, AV = 2
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves (Continued)
AV = 1
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
AV = 1
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 31. DIFFERENTIAL GAIN, AV = 1
FIGURE 32. DIFFERENTIAL PHASE, AV = 1
AV = 1
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
AV = 1
RL = 150
INPUT_CH 31
OUTPUT_CH 31
OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, AV = 1
FIGURE 34. DIFFERENTIAL GAIN, AV = 1
AV = 2
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
AV = 2
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
FIGURE 35. DIFFERENTIAL GAIN, AV = 2
11
FIGURE 36. DIFFERENTIAL PHASE, AV = 2
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves (Continued)
AV = 2
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
AV = 2
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
FIGURE 37. DIFFERENTIAL GAIN, AV = 2
FIGURE 38. DIFFERENTIAL PHASE, AV = 2
AV = 1
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
AV = 1
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
FIGURE 39. DIFFERENTIAL GAIN, AV = 1
FIGURE 40. DIFFERENTIAL PHASE, AV = 1
AV = 1
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
AV = 1
RL = 150
INPUT_CH 00
OUTPUT_CH 31
OSC = 40mV
FIGURE 41. DIFFERENTIAL GAIN, AV = 1
12
FIGURE 42. DIFFERENTIAL PHASE, AV = 1
FN6249.7
October 10, 2011
ISL59534
Typical Performance Curves (Continued)
AV = 2
RL = 150
INPUT_CH 00
OUTPUT_CH 00
OSC = 40mV
AV = 2
RL = 150
INPUT_CH 00
OUTPUT_CH 00
OSC = 40mV
FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2
FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2
AV = 1
RL = 150
INPUT_CH 00
OUTPUT_CH 00
OSC = 40mV
AV = 1
RL = 150
INPUT_CH 00
OUTPUT_CH 00
OSC = 40mV
FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1
13
FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1
FN6249.7
October 10, 2011
3dB Bandwidth, MUX Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS
0
0
1
2
3
4
262
5
6
7
1
10
11
12
13
14
268
17
18
19
20
21
22
23
24
236
25
26
27
28
288
30
31
236
290
269
271
14
273
274
256
272
255
268
8
274
278
9
286
265
281
277
282
11
265
288
283
285
12
267
258
7
350
196
13
216
269
285
199
281
238
230
238
220
280
287
274
3dB Bandwidth, MUX Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS
0
0
1
2
3
4
304
1
5
6
7
323
10
11
12
13
324
16
17
18
19
305
20
21
22
23
24
313
25
26
27
28
31
308
348
360
366
350
317
350
348
327
8
341
325
9
339
351
350
11
338
355
321
354
371
FN6249.7
October 10, 2011
12
348
381
289
13
340
350
7
334
350
366
288
311
30
370
351
14
29
320
371
6
15
15
353
4
10
14
294
3
OUTPUT CHANNELS
9
290
2
5
8
348
313
314
297
336
345
314
ISL59534
14
29
235
214
6
15
16
272
4
10
15
235
277
3
OUTPUT CHANNELS
9
217
2
5
8
270
3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100 [MHz]
15
OUTPUT CHANNELS
INPUT CHANNELS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
196
204
193
175
154
154
158
161
169
157
155
146
125
121
115
109
81
81
79
80
85
85
86
86
83
82
82
77
80
82
85
86
1
172
2
165
3
152
4
133
5
132
6
125
7
127
8
124
9
116
10
114
11
108
12
106
108
104
15
107
104
128
123
88
87
100
98
102
100
102
79
96
99
106
81
98
103
100
80
96
108
97
88
84
94
92
85
84
97
92
81
88
89
89
88
87
90
89
82
91
94
98
114
78
98
98
98
99
101
99
97
95
87
86
84
81
89
81
86
113
87
79
95
113
110
85
99
105
113
112
112
114
126
126
128
115
129
124
118
114
111
120
122
129
131
3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100[MHz]
OUTPUT CHANNELS
INPUT CHANNELS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
270
277
268
247
213
216
227
244
258
223
208
196
147
142
132
123
85
85
85
86
91
91
92
93
90
88
86
85
89
90
92
94
1
240
2
233
3
204
4
172
5
170
6
152
7
155
8
146
9
133
10
129
11
119
FN6249.7
October 10, 2011
12
116
13
120
14
113
15
117
223
112
158
108
146
94
106
105
109
93
109
89
103
106
113
107
112
83
107
117
84
106
112
89
84
103
118
99
94
90
102
98
89
94
93
94
94
93
96
95
85
97
103
108
135
82
105
105
106
108
110
107
104
101
93
91
88
85
95
88
92
126
92
83
105
128
121
88
113
130
127
127
130
153
150
158
163
149
140
133
126
140
133
146
161
164
ISL59534
13
14
163
ISL59534
Block Diagram
VS
VOVERn
OVERn
16 OVERLAY
VIDEO INPUTS
VREF
16 OVERLAY
CHANNEL
ENABLES
CLAMP
32 VIDEO
INPUTS
IN0 - IN31
16 VIDEO
OUTPUTS
OUT0 – OUT15
32x16
SWITCH
MATRIX
CLAMP
CLAMP
ENABLE
SDI
SCLK
SLATCH
SPI INTERFACE AND
CONTROL REGISTERS
AV
X1, X2
OUTPUT
ENABLE
VSDO
SDO
General Description
Serial Interface
The ISL59534 is a 32x16 integrated video crosspoint switch
matrix with input and output buffers and On-Screen Display
(OSD) insertion. This device operates from a single +5V
supply. Any output can be generated from any of the 32 input
video signal sources, and each output can have OSD
information inserted through a dedicated, fast 2:1 mux
located before the output buffer. There is also a Broadcast
mode allowing any one input to be broadcast to all 16
outputs. A DC restore clamp function enables the ISL59534
to AC-couple incoming video.
The ISL59534 is programmed through a simple serial
interface. Data on the SDI (serial data input) pin is shifted
into a 16-bit shift register on the rising edge of the SCLK
(serial clock) signal. (This is continuously done regardless of
the state of the SLATCH signal.) The LSB (bit 0) is loaded
first and the MSB (bit 15) is loaded last (see the Serial
Timing Diagram). After all 16 bits of data have been loaded
into the shift register, the rising edge of SLATCH updates the
internal registers.
The ISL59534 offers a -3dB signal bandwidth of 300MHz.
Differential gain and differential phase of 0.025% and 0.05°
respectively, along with 0.1dB flatness out to 50MHz make
this ideal for multiplexing composite NTSC and PAL signals.
The switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible, three-wire
serial interface. The ISL59534 interface is designed to
facilitate both fast initialization and configuration changes.
On power-up, all outputs are initialized to the disabled state
to avoid output conflicts in the user’s system.
Digital Interface
The ISL59534 uses a serial interface to program the
configuration registers. The serial interface uses three
signals (SCLK, SDI, and SLATCH) for programming the
ISL59534, while a fourth signal (SDO) enables optional
daisy-chaining of multiple devices. The serial clock can run
at up to 5MHz (5Mbits/s).
16
While the ISL59534 has an SDO (Serial Data Out) pin, it
does not have a register readback feature. The data on the
SDO pin is an exact replica of the incoming data on the SDI
pin, delayed by 15.5 SCLKs (an input bit is latched on the
rising edge of SLCK, and is output on SDO on the falling
edge of SLCK 15.5 SCLKs later). Multiple ISL59534’s can be
daisy-chained by connecting the SDO of one to the SDI of
the other, with SCLK and SLATCH common to all the daisychained parts. After all the serial data is transmitted (16 bits *
n devices = 16*n SCLKs), the rising edge of SLATCH will
update the configuration registers of all n devices
simultaneously.
The Serial Timing Diagram and Serial Timing Parameters
table on page 17 show the timing requirements for the serial
interface.
FN6249.7
October 10, 2011
ISL59534
Serial Timing Diagram
SLATCH
SLATCH falling edge timing/placement is a “don’t care.”
Serial data is latched only on rising edge of SLATCH.
tSL
T
SCLK
tHD
tw
tSD
B0
(LSB)
SDI
SDO
B1
B15
(MSB)
B2
B0
B1
B2
B15
(previous)
(previous)
(previous)
(previous)
B0
(LSB)
B1
B2
SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59534s. SDO changes on the falling edge of SCLK.
TABLE 1. SERIAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
T
200ns
SCLK period
tW
0.50 * T
Clock Pulse Width
tSD
20ns
Data Setup Time
tHD
20ns
Data Hold Time
tSL
20ns
Final SLCK rising edge (latching B15) to SLATCH rising edge
Programming Model
The ISL59534 is configured by a series of 16-bit serial control words. The three MSBs (B15-13) of each serial word determine the
basic command:
TABLE 2. COMMAND FORMAT
B15
B14
B13
COMMAND
NUMBER OF WRITES
0
0
0
INPUT/OUTPUT: Maps input channels to output channels
32 (1 channel per write)
0
0
1
OUTPUT ENABLE: Output enable for individual channels
4 (4 channels per write)
0
1
0
GAIN SET: Gain (+1 or +2) for each channel
4 (4 channels per write)
0
1
1
BROADCAST: Enables broadcast mode and selects the input channel to be
broadcast to all output channels
1
1
1
1
CONTROL: Clamp on/off, operational/standby mode, and global output
enable/disable
1
Mapping Inputs to Outputs
Inputs are mapped to their desired outputs using the input/output control word. Its format is:
TABLE 3. INPUT/OUTPUT WORD
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
0
0
0
I4
I3
I2
I1
I0
-
-
-
O3
O2
O1
O0
B0
I4:I0 form the 5-bit word indicating the input channel (0 to 31), and O3:O0 determine the output channel which that input channel
will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59534, 32 INPUT/OUTPUT words must
be transmitted - one for each input channel.
Note: Broadcast Mode must be disabled when configuring input/output mapping. INPUT/OUTPUT words transmitted while in
Broadcast Mode will not be processed correctly and result in corrupt channel mapping when Broadcast Mode is disabled.
17
FN6249.7
October 10, 2011
ISL59534
Enabling Outputs
The output enable control word is used to enable individual outputs. There are 16 channels to configure, so this is accomplished by
writing 4 serial words, each controlling a bank of eight outputs at a time. The bank is selected by bits B9 and B8. The output enable
control word format is:
TABLE 4. OUTPUT ENABLE FORMAT
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
0
0
0
0
O3
O2
O1
O0
0
0
1
0
0
0
0
1
O7
O6
O5
O4
0
0
1
0
0
0
1
0
O11
O10
O9
O8
0
0
1
0
0
0
1
1
O15
O14
O13
O12
Setting the ON bit = 0 tri-states the output. Setting the ON bit = 1 enables the output if the Global Output Enable bit is also set (the
individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage).
Setting the Gain
The gain of each output may be set to +1 or +2 using the Gain Set word. It is in the same format as the output enable control word:
TABLE 5. GAIN SET FORMAT
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
0
0
0
0
0
G3
G2
G1
G0
0
1
0
0
0
0
0
1
G7
G6
G5
G4
0
1
0
0
0
0
1
0
G11
G10
G9
G8
0
1
0
0
0
0
1
1
G15
G14
G13
G12
Set GN = 0 for a gain of +1 or 1 for a gain of +2.
Broadcast Mode
The Broadcast Mode routes one input to all 16 outputs. The broadcast control word is:
TABLE 6. BROADCAST FORMAT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
0
1
1
I4
I3
I2
I1
I0
0
0
0
0
0
0
0
B0
Enable Broadcast
0: Broadcast Mode Disabled
1: Broadcast Mode Enabled
I4:I0 form the 5 bit word indicating the input channel (0 to 31) to be sent to all 16 outputs. Set the Enable Broadcast bit (B0) = 1 to
enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments
are restored.
Control Word
The ISL59534’s power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the
following control word should be sent:
TABLE 7. CONTROL WORD FORMAT
B15 B14 B13 B12 B11 B10
1
1
1
0
0
0
B9
B8 B7 B6 B5 B4 B3 B2
0
Clamp
0: Clamp Disabled
1: Clamp Enabled
0
0
0
0
0
0
B1
B0
Global Output Enable
Power
0: All outputs tri-stated
0: Standby
1: Operational 1: Individual Output Enable bits control outputs
The Clamp bit enables the input clamp function, forcing the AC-coupled signal’s most negative point to be equal to VREF.
Note: The Clamp bit turns the DC-Restore clamp function on
or off for all channels - there is no DC-Restore on/off control
for individual channels. The DC-Restore function only works
with signals with sync tips (composite video). Signals that do
18
not have sync tips (the Chroma/C signal in s-video and the
Pb, Pr signals in Component video), will be severely
distorted if run through a DC-Restore/clamp function.
FN6249.7
October 10, 2011
ISL59534
For this reason, the ISL59534 must be in DC-coupled
mode (Clamp Disabled) to be compatible with s-video
and component video signals.
Bandwidth Considerations
Wide frequency response (high bandwidth) in a video
system means better video resolution. Four sets of
frequency response curves are shown in Figure 47.
Depending on the switch configurations, and the routing (the
path from the input to the output), bandwidth can vary
between 100MHz and 350MHz. A short discussion of the
trade-offs — including matrix configuration, output buffer
gain selection, channel selection, and loading — follows.
NORMALIZED GAIN (dB)
2
Linear Operating Region
In addition to bandwidth optimization, to get the best linearity
the ISL59534 should be configured to operate in its most
linear operating region. Figure 48 shows the differential gain
curve. The ISL59534 is a single supply 5V design with its
most linear region between 0.1 and 2V. This range is fine for
most video signals whose nominal signal amplitude is 1V.
The most negative input level (the sync tip for composite
video) should be maintained at 0.3V or above for best
operation.
MUX, AV = 2
0
MUX, AV = 1
BROADCAST,
AV = 1
-2
BROADCAST,
AV = 2
-4
-6
-8
-10
FIGURE 48. DIFFERENTIAL GAIN RESPONSE
1
10
100
1000
FREQUENCY (MHz)
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES
In multiplexer mode, one input typically drives one output
channel, while in broadcast mode, one input drives all 16
outputs. As the number of outputs driven increases, the
parasitic loading on that input increases. Broadcast Mode is
the worst-case, where the capacitance of all 16 channels
loads one input, reducing the overall bandwidth. In addition,
due to internal device compensation, an output buffer gain of
+2 has higher bandwidth than a gain of +1. Therefore, the
highest bandwidth configuration is multiplexer mode (with
each input mapped to only one output) and an output buffer
gain of +2.
The relative locations of the input and output channels also
have significant impact on the device bandwidth (due to the
layout of the ISL59534 silicon). When the input and output
channels are further away, there are additional parasitics as
a result of the additional routing, resulting in lower
bandwidth.
The bandwidth does not change significantly with resistive
loading as shown in the typical performance curves.
However several of the curves demonstrate that frequency
response is sensitive to capacitance loading. This is most
significant when laying out the PCB. If the PCB trace length
between the output of the crosspoint switch and the backtermination resistor is not minimized, the additional parasitic
capacitance will result in some peaking and eventually a
reduction in overall bandwidth.
19
In a DC-coupled application, it is the system designer’s
responsibility to ensure that the video signal is always in the
optimum range.
When AC coupling, the ISL59534’s Clamp (also called “DC
restore”) function automatically and continuously adjusts the
DC level so that the most negative portion of the video is
always equal to VREF.
A discussion of the benefits of the DC restoration function
begins by understanding the Clamp circuit shown in
Figure 49. The incoming video signal is typically terminated
into 75, then AC coupled through C1, at which point it is
connected to the base of the buffer’s diff pair. These
components form the video path.
The Clamp function consists of Q1, D1, Q2, D2, the two
current sources, and the 3 switches controlled by the Clamp
Enable signal. The VREF voltage is level-shifted up two
diode drops (Q1 and D1) to the base of Q2. If the voltage at
the cathode of D2 goes below VREF, Q2 and D2 will turn on,
keeping the INx voltage at VREF. If the voltage at INx is
greater than VREF, Q2 and D2 are off and the INx node is
high impedance. This is how the clamp function forces the
lowest portion of the video signal (the sync tip) to always be
equal to or greater than VREF.
To make sure that the sync tip is always equal to (not equal
to or greater than) VREF, i1 is constantly sinking ~2µA of
current from C1. This causes each sync tip to be slightly
lower voltage than the previous sync tip, causing Q2 and D2
to turn on at each sync tip and raise the voltage to VREF. The
2µA pulldown with a 0.1uF capacitor and a 15kHz HSYNC
frequency results in 1.3mV of “droop” across every line, or
FN6249.7
October 10, 2011
ISL59534
0.2% of the video signal. Because 1.3mV is only 0.2% of a
0.7V video signal, this droop is imperceptible to the human
eye.
delivering acceptable droop and CIN = 0.001µF producing
excessive droop.
When the clamp function is disabled in the CONTROL
register (Clamp = 0) to allow DC-coupled operation, the
ICLAMP current sinks/sources are disabled and the input
passes through the DC Restore block unaffected. In this
application VREF may be tied to GND.
Overlay Operation
The ISL59534 features an overlay feature, that allows an
external video signal or DC level to be inserted in place of
that output channel’s video. When the OVERN signal is
taken high, the output signal on the OUTN pin is replaced
with the signal on the VOVERN pin.
Q2
D1
VREF
~0.4V
Q1
C2 (110µA)
D3
D2
0.1µF
SS12
INPUT
TO
BUFFER
INx
VIDEOIN
C1
0.1µF
R1
75
i1
CLAMP
ENABLE
FIGURE 49. DC RESTORE BLOCK DIAGRAM
This is how the video is “DC-restored” after being AC
coupled into the ISL59534. The sync tip voltage will be equal
to VREF on the right side of C1, regardless of the DC level of
the video on the left side of C1. Due to various sources of
offset in the actual clamp function, the actual sync tip level is
typically about 75mV higher than VREF (for VREF = 0.4V).
There are several ways the overlay feature can be used.
Toggling the OVERN signal at the frame rate or slower will
replace the video frame(s) on the OUTN pin with the video
supplied on the VOVERN pin.
Another option (for OSD displays, for example), is to put a
DC level on the VOVERN line and toggle the OVERN signal
at the pixel rate to create a monocolor image “overlaid” on
channel N’s output signal.
Finally, by enabling the OVERN signal for some portion of
each line over a certain amount of lines, a picture-in-picture
function can be constructed.
It’s important to note that the overlay inputs do not have the
DC Restore function previously described - the overlay
signal is DC coupled into the output. It is the system
designer’s responsibility to ensure that the video levels are
in the ISL59534’s linear region and matching the output
channel’s offset and amplitude. One easy way to do this is to
run the video to be overlaid through one of the ISL59534’s
unused channels and then into the VOVERN input.
The OVERN pins all have weak pull-downs, so if they are
unused, they can either be left unconnected or tied to GND.
Power Dissipation and Thermal Resistance
FIGURE 50. DC RESTORE VIDEO WAVEFORMS
It is important to choose the correct value for CIN. Too small
a value will generate too much droop, and the image will be
visibly darker on the right than on the left. A CIN value that is
too large may cause the clamp to fail to converge. The droop
rate (dV/dt) is i1/CIN volts/second. In general, the droop
voltage should be limited to <1 IRE over a period of one line
of video; so for 1 IRE = 7mV, IB = 10µA maximum, and an
NTSC waveform we will set CIN > 10µA*60µs/7mV =
0.086µF. Figure 50 shows the result of CIN = 0.1µF
20
With a large number of switches, it is possible to exceed the
+150°C absolute maximum junction temperature under
certain load current conditions. Therefore, it is important to
calculate the maximum junction temperature for an
application to determine if load conditions or package types
need to be modified to assure operation of the crosspoint
switch in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
(EQ. 1)
FN6249.7
October 10, 2011
ISL59534
Where:
• TJMAX = Maximum junction temperature = +125°C
• TAMAX = Maximum ambient temperature = +85°C
• JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
n
PD MAX = V S  I SMAX +
V OUTi
  VS – VOUTi   ---------------R Li
i=1
(EQ. 2)
Where:
• VS = Supply voltage = 5V
• ISMAX = Maximum quiescent supply current = 505mA
• VOUT = Maximum output voltage of the application = 2V
• RLOAD = Load resistance tied to ground = 150
• n = 1 to 16 channels
n
PD MAX = V S  I SMAX +
V OUTi
-=
  VS – VOUTi   ---------------R Li
i=1
3.2W
(EQ. 3)
The required JA to dissipate 3.2W is:
T JMAX – T AMAX
 JA = --------------------------------------------- = 12.5  C/W 
PD MAX
(EQ. 4)
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21
FN6249.7
October 10, 2011
ISL59534
Package Outline Drawing
V356.27x27C
356 BALL HEATSINK PLASTIC BALL GRID ARRAY PACKAGE (HPBGA)
Rev 1, 6/10
0.20 (4X)
27.00
A1 BALL
PAD CORNER
24.00 +0.35
-0.05
4X 10.00
5.
A1 BALL PAD
INDICATOR, 1.0
DIA., OPTIONAL
A
B
4X 10.00
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1.27
27.00
+0.35
24.00 -0.05
(1.44)
4X 45°
CHAMFER
TOP VIEW
EXPOSED HEAT SPREADER
Ø16.8 AVAILABLE MARKING AREA
(1.44)
1.27
3X R0.50
BOTTOM VIEW
0.35 C
0.25 C
0.15 C
C
30° TYP
+0.14
3. 0.76 -0.16
Ø0.30 M C A B
Ø0.15 M C
1.27
1.27
4. SEATING PLANE
NON SOLDERMASK DEFINED PADS.
SOLDERMASK OPENING = 0.67MM (TYP x356)
PAD DIAMATER = 0.55MM (TYP X356)
1.17±0.05
2.33 ±0.21
0.60±0.10
0.56 ±0.06
TYPICAL RECOMMENDED LAND PATTERN
SIDE VIEW
NOTES:
1.
All dimensions and tolerances conform to ASME Y14.5m-1994.
2.
Dimensions are in millimeters.
3 . Dimension is measured at the maximum solder ball diameter,
parallel to primary datum C.
22
4.
Primary datum C and seating plane are defined by the spherical
crowns of the solder balls.
5.
A1 ball pad corner I.D. for plate mold: To be marked by ink.
Auto mold: Dimple to be formed by mold cap.
6.
Reference specifications: This drawing conforms to JEDEC
registered outline MS-034/A variation BAL-2.
FN6249.7
October 10, 2011