74HC1G00-Q100; 74HCT1G00-Q100 2-input NAND gate Rev. 1 — 16 September 2013 Product data sheet 1. General description The 74HC1G00-Q100; 74HCT1G00-Q100 is a single 2-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC1G00-Q100: CMOS level For 74HCT1G00-Q100: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number 74HC1G00GW-Q100 Package Temperature range Name 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 40 C to +125 C SC-74A SOT753 74HCT1G00GW-Q100 74HC1G00GV-Q100 74HCT1G00GV-Q100 Description plastic surface-mounted package; 5 leads Version 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate 4. Marking Table 2. Marking codes Type number Marking[1] 74HC1G00GW-Q100 HA 74HCT1G00GW-Q100 TA 74HC1G00GV-Q100 H00 74HCT1G00GV-Q100 T00 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B 1 B 2 A 1 Y & 4 Y 2 Logic symbol A mna098 mna097 Fig 1. 4 Fig 2. IEC logic symbol Fig 3. mna099 Logic diagram 6. Pinning information 6.1 Pinning +&*4 +&7*4 % $ *1' 9&& < DDD Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input A 2 data input GND 3 ground (0 V) Y 4 data output VCC 5 supply voltage 74HC_HCT1G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 2 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Input Output A B Y L L H L H H H L H H H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter VCC supply voltage IIK input clamping current IOK Conditions Min Max Unit 0.5 +7.0 V VI < 0.5 V or VI > VCC + 0.5 V - 20 mA output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA 0.5 V < VO < VCC + 0.5 V IO output current - 12.5 mA ICC supply current - 25 mA IGND ground current 25 - mA Tstg storage temperature 65 +150 C - 200 mW total power dissipation Ptot Tamb = 40 C to +125 C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Above 55 C, the value of Ptot derates linearly with 2.5 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC1G00-Q100 74HCT1G00-Q100 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature t/V input transition rise and fall rate 74HC_HCT1G00_Q100 Product data sheet 40 +25 +125 40 +25 +125 C VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - - 139 - - 139 ns/V VCC = 6.0 V - - 83 - - - ns/V All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 3 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C. Symbol Parameter 40 C to +85 C Conditions Min Typ 40 C to +125 C Max Min Unit Max For type 74HC1G00-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - V IO = 2.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V IO = 2.6 mA; VCC = 6.0 V 5.63 5.81 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 V IO = 2.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 2.6 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 10 - 20 A CI input capacitance - 1.5 - - - pF For type 74HCT1G00-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = 2.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V VOL II LOW-level output voltage input leakage current 74HC_HCT1G00_Q100 Product data sheet VI = VIH or VIL IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 2.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V VI = VCC or GND; VCC = 5.5 V - - 1.0 - 1.0 A All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 4 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C. Symbol Parameter 40 C to +85 C Conditions Min Typ 40 C to +125 C Max Min Unit Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 10 - 20 A ICC additional supply current per input; VCC = 4.5 V to 5.5 V; VI = VCC 2.1 V; IO = 0 A - - 500 - 850 A CI input capacitance - - - pF - 1.5 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; tr = tf 6.0 ns; All typical values are measured at Tamb = 25 C. For test circuit, see Figure 6 Symbol Parameter 40 C to +85 C Conditions Min Typ 40 C to +125 C Unit Max Min Max For type 74HC1G00-Q100 tpd propagation delay A and B to Y; see Figure 5 [1] VCC = 2.0 V; CL = 50 pF - 25 115 - 135 ns VCC = 4.5 V; CL = 50 pF - 9 23 - 27 ns VCC = 5.0 V; CL = 15 pF - 7 - - - ns - 8 20 - 23 ns - 19 - VCC = 4.5 V; CL = 50 pF - 12 24 - 27 ns VCC = 5.0 V; CL = 15 pF - 10 - - - ns - 21 - VCC = 6.0 V; CL = 50 pF CPD [2] power dissipation VI = GND to VCC capacitance - - pF For type 74HCT1G00-Q100 tpd CPD [1] [2] propagation delay A and B to Y; see Figure 5 power dissipation VI = GND to VCC 1.5 V capacitance [1] [2] - - pF tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation PD (W). PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts (CL VCC2 fo) = sum of outputs 74HC_HCT1G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 5 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate 12. Waveforms A, B input VM VCC tPHL Y output tPLH PULSE GENERATOR VM VI VO DUT CL RT mna100 mna101 For HC1G: VM = 0.5 VCC; VI = GND to VCC Test data is given in Table 8. For HCT1G: VM = 1.3 V; VI = GND to 3.0 V CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 5. Input to output propagation delays 74HC_HCT1G00_Q100 Product data sheet Fig 6. Load circuitry for switching times All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 6 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 Fig 7. REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Package outline SOT353-1 (TSSOP5) 74HC_HCT1G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 7 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 Fig 8. JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Package outline SOT753 (SC-74A) 74HC_HCT1G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 8 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate 14. Abbreviations Table 9. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT1G00_Q100 v.1 20130916 Product data sheet - - 74HC_HCT1G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 9 of 12 74HC1G00-Q100; 74HCT1G00-Q100 NXP Semiconductors 2-input NAND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT1G00_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 10 of 12 NXP Semiconductors 74HC1G00-Q100; 74HCT1G00-Q100 2-input NAND gate No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT1G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 September 2013 © NXP B.V. 2013. All rights reserved. 11 of 12 NXP Semiconductors 74HC1G00-Q100; 74HCT1G00-Q100 2-input NAND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 September 2013 Document identifier: 74HC_HCT1G00_Q100