CCD Delay Line Series MN3870S NTSC-Compatible CCD Comb Filter with Built-in 1 H Video Signal Delay Element Overview The MN3870S is a 4 fSC CMOS CCD comb filter with a built-in 4 fSC CMOS CCD signal delay element for video signal processing applications. It contains such components as a fourfold-frequency circuit, a shift register clock driver, a CCD analog shift register switchable between 911, 1 and 908 / 906 stages, and a resampling output amplifier. It samples the input using the supplied clock signal with a frequency of four times the color signal subcarrier frequency (3.58 MHz) and subtracts between the 911- and 1-stage CCD output signals to produce the color signal comb characteristics for the NTSC system. It also uses this fourfold frequency to drive a 908- or 906-stage CCD and samples the input to produce, after adding in the attached filter delay, a delay of 1 H (the horizontal scan period) when the SW pin is left open. Features Single 5.0 V power supply Low power consumption based on CMOS process Low EMI levels from clock during driving True comb filter produced by the subtraction of the through signal and the 1 H delay signal Pin Assignment X1 1 20 PCOUT & VCOIN VBB 2 19 N.C. N.C. 3 18 VSS3 VGC1 4 17 VDD3 VOC 5 16 VDD2 VINC 6 15 VSS2 N.C. 7 14 VGC2 N.C. 8 13 SW VSS1 9 12 VINY VDD1 10 11 VOY ( TOP VIEW ) SOP020-P-0300C Applications VCRs, Video cameras 1 MN3870S CCD Delay Line Series Clamp circuit Mode switch Bias circuit VGC2 Booster circuit VINY 12 Charge input block 908 or 906-stage analog shift register Charge detector 6 Charge input block 911-stage analog shift register Charge detector Charge input block 1-stage analog shift register Charge detector VINC 14 VGC1 4 13 SW VDD3 17 16 V DD2 10 VDD1 Block Diagram 11 Resampling output amplifier – 5 Resampling output amplifier øSY driver Waveform adjustment block øRY driver ø1Y driver øSHY driver Timing adjustment ø2Y driver øSHY driver øSC driver XI 1 1/4th frequency divider Waveform amplifier adjustment block Waveform adjustment block ø1C driver øRC driver øSHC driver Phase comparator VCO ø2C driver Timing adjustment øSHC driver 2 VBB 2 VSS3 18 VSS2 15 VSS1 PCOUT & VCOIN 9 20 Substrate bias generator VOY VOC CCD Delay Line Series MN3870S Pin Descriptions Pin No. 1 Symbol XI Pin Name 3.58 MHz clock input Remarks 2 VBB 4 VGC1 Substrate connection Output gate connection (1) 5 VOC C signal output 6 VINC C signal input 9 VSS1 GND (1) Ground for analog circuits 10 VDD1 Power supply (1) For analog circuits 11 VOY Y signal output 12 VINY Y signal input 13 SW Switch controlling number of stages for Y signal delay 14 VGC2 15 VSS2 GND (2) 16 VDD2 Power supply (2) For digital signals 17 VDD3 Power supply (3) For phase-locked loop 18 VSS3 GND (3) Ground for phase-locked loop 20 PCOUT &VCOIN Output gate connection (2) Ground for digital signals Phase comparator output and voltage controlled oscillator input Note: Leave pin 13 open. 3 MN3870S CCD Delay Line Series Operating Conditions Parameter Power supply voltage Symbol VDD min 4.75 Input clock frequency fck Input clock amplitude (sine wave) Vck 0.25 Ambient temperature Ta –20 typ 5.00 max 5.25 Unit V 3.579545 MHz 0.3 1.0 VP–P 60 ˚C Electrical Characteristics VDD=5.0V, Vck=0.3VP-P (sine wave), Vin=0.5VP-P (sine wave), fck=3.579545MHz, f=196.7kHz, Ta=25˚C Parameter Power supply voltage Insertion gain for VOC pin Total harmonic distortion for VOC Conditions Average current min IDD typ 55 max 80 Unit mA IG fsig=3.579545MHz –9 –5.5 –2 dB THD fsig=3.26486MHz 0.5 2.5 % S/N 3.264 86 MHz output (VP-P)/ Symbol pin Signal-to-noise ratio for VOC pin 48 56 dB noise output (rms) Output impedance for VOC pin Comb characteristics for VOC pin ZO Com1 3.571678MHz/3.579545MHz (fsc–1/2fH) / (fsc) 3.256993MHz/3.264860MHz Com2 (fsc–20.5fH) / (fsc–20fH) 3.902097MHz/3.894230MHz (fsc–20.5fH) / (fsc–20fH) Clock leak for VOC pin NC1 NC2 Signal bandwidth for VOY pin Insertion gain for VOY pin Total harmonic distortion for VOY BW 3.58-MHz component/main signal in output signal 14.32-MHz component/main signal in output signal 300 600 Ω –35 –25 dB –30 –20 dB –30 –20 dB –50 –40 dB –30 –20 dB –3 dB for 196.7 kHz 2.5 5.5 –1.5 1.5 4.5 dB 1 4.5 % IG fsig=196.7kHz THD fsig=196.7MHz S/N Signal output (P–P)/noise output MHz pin Signal-to-noise ratio for VOY pin 48 56 dB (rms) Clock leak for VOY pin NC3 NC4 Delay for VOY pin signal in output signal 14.32-MHz component/main signal in output signal τD Output impedance for VOY pin ZO Crosstalk CT 4 3.58-MHz component/main –50 –40 dB –20 –10 dB µs 63.46 250 fsig=196.7kHz 500 Ω –32 dB CCD Delay Line Series MN3870S Package Dimensions (Unit:mm) SOP020-P-0300C 12.63±0.3 20 +0.10 0.2 -0.05 7.6±0.3 5.5±0.3 11 0 to 10° 10 (0.4) (0.6) 0.10 1.27 0.4±0.25 0.1±0.1 2.05±0.2 1 SEATING PLANE 5