LSIs for Gray Scale Font Engine MN5572 Gray Scale Font Engine ■ Overview The MN5572 generates shaded gray-scale data from outline (path) data for figures and characters at high speeds. This IC includes built-in input and output FIFO buffers for high-speed processing, and provides three interface circuits, a 32-bit local bus, a 16-bit local bus, and a PCI bus, so that it can be used in a wide range of application products. Note) PCI bus is a registered trademark of the (US) Peripheral Component Interconnect Association. ■ Features • Gray levels: The number of gray levels can be set to any value between 2 and 128. • Bit size: The bit size can be set arbitrarily. • Generation processing speed: More than 20 000 frames/second (A single frame is 32 dots by 32 dots, when the Heisei Gothic (Japanese) font is used as the sample data.) • Interface specifications: Local bus (16 bits or 32 bits, 33 MHz), PCI bus (32 bits, 33 MHz) • Operating frequency: 66 MHz (maximum) • Operating supply voltage: 3.3 V ± 0.3 V (5 V inputs are also supported.) ■ Applications • High-quality character generation in STB, DTV, in-car navigation systems and other products. ■ Block Diagrams • Local Mode RAM • PCI Mode MN5572 ROM Network Local Bus Bridge Publication date: November 2001 MN5572 Graphics PCI Bus Host-PCI Bridge CPU SDF00008BEM CPU Bus CPU 1 MN5572 ■ Pin Assignments 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 N.C. ADRS1 ADRS2 ADRS3 NWE NCS NRE VDD DATA16 DATA17 DATA18 DATA19 VSS VDD DATA20 DATA21 DATA22 DATA23 VSS VDD DATA24 DATA25 DATA26 DATA27 VSS 1. Pin Assignment in Local 32/16 Mode 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VDD VSS IRQ MINTEST TESTON IFCFG BUSSEL CLKSEL2 CLKSEL1 CLKSEL0 MIN5 VDD OCLOCK VSS ICLOCK VDD CAPTON P1VDD P1VSS P1TCPOUT P1SEL2 P1SEL1 P1NPWD PLTEST N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ADRS0 VSS DATA15 DATA14 DATA13 DATA12 VDD VSS DATA11 DATA10 DATA9 DATA8 VDD VSS DATA7 DATA6 DATA5 DATA4 VDD VSS DATA3 DATA2 DATA1 DATA0 N.C. (TOP VIEW) Note) N.C.: No connection. 2 SDF00008BEM N.C. VDD DATA28 DATA29 DATA30 DATA31 VSS VDD WAIT NDEVSEL NSTOP PAR NPERR NSERR VSS NRST VDD HOSTCLK VSS P2VSS P2VDD P2TCPOUT P2NPWD PLTPDIN PLNRESET MN5572 ■ Pin Assignments (continued) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 N.C. NCBE1 NCBE2 NCBE3 NIRDY NFRAME IDSEL VDD AD16 AD17 AD18 AD19 VSS VDD AD20 AD21 AD22 AD23 VSS VDD AD24 AD25 AD26 AD27 VSS 2. Pin Assignment in PCI Mode 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 N.C. VDD AD28 AD29 AD30 AD31 VSS VDD NTRDY NDEVSEL NSTOP PAR NPERR NSERR VSS NRST VDD PCICLK VSS P2VSS P2VDD P2TCPOUT P2NPWD PLTPDIN PLNRESET VDD VSS IRQ MINTEST TESTON IFCFG BUSSEL CLKSEL2 CLKSEL1 CLKSEL0 MIN5 VDD OCLOCK VSS ICLOCK VDD CAPTON P1VDD P1VSS P1TCPOUT P1SEL2 P1SEL1 P1NPWD PLTEST N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NCBE0 VSS AD15 AD14 AD13 AD12 VDD VSS AD11 AD10 AD9 AD8 VDD VSS AD7 AD6 AD5 AD4 VDD VSS AD3 AD2 AD1 AD0 N.C. (TOP VIEW) Note) N.C.: No connection. SDF00008BEM 3 MN5572 ■ Pin Descriptions 1. Local 32 mode pin descriptions 4 Pin Name I/O Description ICLOCK I Internal operating clock input HOSTCLK I External interface clock input NRST I Hardware reset (active low) ADRS[3 : 0] I Address input from host NCS I Chip select from host (active low) NWE I Write enable from host (active low) NRE I Read enable from host (active low) DATA[31 : 16] I/O Data I/O to/from host (upper 16 bits) DATA[15 : 0] I/O Data I/O to/from host (lower 16 bits) WAIT O Wait output to host IRQ O Interrupt request output to host IFCFG I Interface mode setting (connect low) BUSSEL I Data bus width setting (connect high) CLKSEL[2 : 0] I Internal/external clock setting PLNRESET I Internal PLL reset (active low) P1NPWD I Low power mode control for internal frequency multiplier PLL (active low) P1SEL[2 : 1] I Frequency selector for internal frequency multiplier PLL P2NPWD I Low power mode control for external phase compensation PLL (active low) OCLOCK O Unused NSERR I Unused NPERR I Unused PAR I Unused NSTOP I Unused NDEVSEL I Unused MINTEST I Testing (Connect low during normal operation.) TESTON I Testing (Connect low during normal operation.) CAPTON I Testing (Connect low during normal operation.) PLTEST I Testing (Connect low during normal operation.) PLTPDIN I Testing (Connect low during normal operation.) P1TCPOUT O Testing P2TCPOUT O Testing MIN5 I 5 V voltage reference P1VDD I Internal frequency multiplier PLL power supply (3.3 V) P2VDD I External phase compensation PLL power supply (3.3 V) VDD I Power supply (3.3 V) SDF00008BEM MN5572 ■ Pin Descriptions (continued) 1. Local 32 mode pin descriptions (continued) Pin Name I/O Description P1VSS Ground P2VSS Ground VSS Ground 2. Local 16 mode pin descriptions Pin Name I/O Description ICLOCK I Internal operating clock input HOSTCLK I External interface clock input NRST I Hardware reset (active low) ADRS[3 : 0] I Address input from host NCS I Chip select from host (active low) NWE I Write enable from host (active low) NRE I Read enable from host (active low) DATA[31 : 16] I Unused DATA[15 : 0] I/O WAIT O Wait output to host IRQ O Interrupt request output to host IFCFG I Interface mode setting (connect low) BUSSEL I Data bus width setting (connect low) CLKSEL[2 : 0] I Internal/external clock setting PLNRESET I Internal PLL reset (active low) P1NPWD I Low power mode control for internal frequency multiplier PLL (active low) P1SEL[2 : 1] I Frequency selector for internal frequency multiplier PLL P2NPWD I Low power mode control for external phase compensation PLL (active low) OCLOCK O Unused NSERR I Unused NPERR I Unused PAR I Unused NSTOP I Unused NDEVSEL I Unused MINTEST I Testing (Connect low during normal operation.) TESTON I Testing (Connect low during normal operation.) CAPTON I Testing (Connect low during normal operation.) PLTEST I Testing (Connect low during normal operation.) PLTPDIN I Testing (Connect low during normal operation.) Data I/O to/from host (upper 16 bits) SDF00008BEM 5 MN5572 ■ Pin Descriptions (continued) 2. Local 16 mode pin descriptions (continued) Pin Name I/O Description P1TCPOUT O Testing P2TCPOUT O Testing MIN5 I 5 V voltage reference P1VDD I Internal frequency multiplier PLL power supply (3.3 V) P2VDD I External phase compensation PLL power supply (3.3 V) VDD I Power supply (3.3 V) P1VSS Ground P2VSS Ground VSS Ground 3. PCI mode pin descriptions 6 Pin Name I/O Description ICLOCK I Internal operating clock input PCICLK I PCI interface clock input NRST I Hardware reset (active low) NCBE[3 : 0] I PCI command/byte enable (active low) NFRAME I PCI cycle frame (active low) NIRDY I PCI initiator ready (active low) IDSEL I PCI initialization device select AD[31 : 16] I/O PCI address/data I/O (upper 16 bits) AD[15 : 0] I/O PCI address/data I/O (lower 16 bits) NDEVSEL O PCI target device select (active low) NTRDY O PCI target ready (active low) PAR I/O PCI parity I/O NSTOP O PCI stop (active low) NSERR O PCI system error NPERR O PCI parity error IFCFG I Interface mode setting (connect high) BUSSEL I Data bus width setting (connect high) CLKSEL[2 : 0] I Internal/external clock select PLNRESET I Internal PLL reset (active low) P1NPWD I Low power mode control for internal frequency multiplier PLL (active low) P1SEL[2 : 1] I Frequency selector for internal frequency multiplier PLL P2NPWD I Low power mode control for external phase compensation PLL (active low) OCLOCK O Unused SDF00008BEM MN5572 ■ Pin Descriptions (continued) 3. PCI mode pin descriptions (continued) Pin Name I/O Description IRQ O Unused MINTEST I Testing (Connect low during normal operation.) TESTON I Testing (Connect low during normal operation.) CAPTON I Testing (Connect low during normal operation.) PLTEST I Testing (Connect low during normal operation.) PLTPDIN I Testing (Connect low during normal operation.) P1TCPOUT O Testing P2TCPOUT O Testing MIN5 I 5 V voltage reference P1VDD I Internal frequency multiplier PLL power supply (3.3 V) P2VDD I External phase compensation PLL power supply (3.3 V) VDD I Power supply (3.3 V) P1VSS Ground P2VSS Ground VSS Ground ■ Functional Descriptions 1. Addressing The following describes the memory registers used to control this IC. 1.1 Local mode address map • Memory access ADRS3 ADRS2 ADRS1 ADRS0 Symbol Description R/W 0 0 0 0 POINT Path (outline) data input port W 0 0 0 1 RASTER Gray-scale data output port R ADRS3 ADRS2 ADRS1 ADRS0 Symbol Description R/W 1 0 0 0 COMMAND Command register W 1 0 0 1 STATUS Status register R 1 0 1 0 MASK Mask register R/W 1 0 1 1 FIFO FIFO status register R • IO access SDF00008BEM 7 MN5572 ■ Functional Description (continued) 1. Addressing (continued) 1.2 PCI mode address map • Memory access AD11 AD10 AD9 Symbol Description R/W 0 0 0 POINT Path (outline) data input port W 0 0 1 RASTER Gray-scale data output port R AD4 AD3 AD2 Symbol Description R/W 0 0 0 COMMAND Command register W 0 0 1 STATUS Status register R 0 1 0 MASK Mask register R/W 0 1 1 FIFO FIFO status register R • IO access 2. Memory register functions 2.1 Path (outline) data input port (Point FIFO) Memory port used for input of the outline font path (outline) data that will be expanded by the MN5572. This port allows 64 double-word values to be written at one time. If more than 64 double-word values must be written, the write operation must be split into multiple operations. The POINT FIFO has a total capacity of 256 doubleword values. • Local 32 and PCI mode bit 31 0 Path data • Local 16 mode Data is transferred in the order high-order bits first, low-order bits later. bit 31 cycle 1 16 Upper 16 bits of the path data bit 15 cycle 2 8 0 Lower 16 bits of the path data SDF00008BEM MN5572 ■ Functional Description (continued) 2. Memory register functions (continued) 2.1 Path (outline) data input port (continued) • POINT FIFO memory map Bank0 depth 64 width 32 bit depth 256 Bank1 Bank2 Bank3 2.2 Gray-scale data output port (RASTER FIFO) Memory port used for output of the gray-scale data generated by the MN5572. This port allows 64 doubleword values to be read at one time. If more than 64 double-word values must be read, the read operation must be split into multiple operations. The RASTER FIFO has a total capacity of 256 double-word values. • Local 32 and PCI mode bit 31 0 Gray data • Local 16 mode Data is transferred in the order high-order bits first, low-order bits later. bit 31 cycle 1 16 Upper 16 bits of the gray data bit 15 cycle 2 0 Lower 16 bits of the gray data SDF00008BEM 9 MN5572 ■ Functional Description (continued) 2. Memory register functions (continued) 2.2 Gray-scale data output port (RASTER FIFO) (continued) • RASTER FIFO memory map Bank0 depth 64 width 32 bit depth 256 Bank1 Bank2 Bank3 2.3 2.4 10 COMMAND register Write-only register used to set the IC operating mode. This is a 16-bit register. Only the low-order 16 bits of the data bus are used. Hex(DATA[15 : 0]) Command Function 0x0000 EXEC Execution mode 0x000F SRST Software reset 0x00F0 IRPT Interrupt 0xAAAA CKSP Sleep mode setting 0x5555 CKST Sleep mode clear STATUS register Read-only register that indicates the IC operating state. This is a 16-bit register. Only the low-order 16 bits of the data bus are used. When an interrupt request has occurred, that request can be cleared by reading the status register. SDF00008BEM MN5572 ■ Functional Description (continued) 2. Memory register functions (continued) 2.4 STATUS register (continued) bit 15 14 PMS PMS: RMS: REC: RVS: MIS: CES: CCS: 13 12 RMS 11 REC 10 5 4 0 RVS 3 MIS 2 0 1 0 CES CCS Indicates the status of the POINT FIFO. After a reset, the status will be FIFO empty. 11: FIFO full (Write not allowed) 01: FIFO ready (Write allowed) 00: FIFO empty (Write wait state) Indicates the status of the RASTER FIFO. During a reset, the status will be FIFO empty. 11: FIFO full (Read wait state) 01: FIFO ready (Read allowed) 00: FIFO empty (Read not allowed) Indicates whether or not the end of a single frame occurs within the 64 double-word values to be read out. 1: The readout of a single frame will be completed by reading out the data indicated by RVS. 0: The end of a frame does not exist in the data indicated by RVS. Indicates the amount of data that can be read out from the RASTER FIFO. Up to 64 double-word values (0x00 to 0x3F) Indicates the IC internal initialization state. An initialization operation is executed automatically after a reset. 1: Initializing (Initialization in progress) 0: Initialized (Initialization complete) Indicates the IC internal execution state. 0: Run mode Indicates the sleep state. 1: Sleep mode 2.5 MASK register Readable/writable register that sets the interrupt generation conditions for the MN5572. This is a 16-bit register. Only the low-order 16 bits of the data bus are used. bit 15 PM PM: RM: TM: 8 7 RM 0 TM Setting this bit enables the MN5572 to generate interrupt requests (IRQ) according to the PMS state. 1: Interrupts generated on FIFO empty. 0: Interrupt disabled. (default) Setting these bits enables the MN5572 to generate interrupt requests (IRQ) according to the RMS state. 11: Interrupts generated on FIFO full. (default) 01: Interrupts generated on FIFO ready. 00: Interrupt disabled. Setting this bit enables the MN5572 to generate interrupt requests (IRQ) according to the state of the MIS flag. 1: An interrupt is generated after initialization completes. (default) 0: Interrupt disabled. SDF00008BEM 11 MN5572 ■ Functional Description (continued) 2. Memory register functions (continued) 2.6 FIFO register (continued) Readable register that indicates the state of the MN5572 POINT and RASTER FIFOs. This is a 16-bit register. Only the low-order 16 bits of the data bus are used. bit 15 12 11 PRBANK 8 7 PWBANK 4 RRBANK 3 0 RWBANK • The 4 bits in PRBANK and PWBANK indicate the status for bank 0 to bank 3 of the POINT FIFO. When a given bit in PRBANK is 1, the data in the corresponding bank has not been read out. When a given bit in PWBANK is 1, the data for the corresponding bank can be written. • The 4 bits in RRBANK and RWBANK indicate the status for bank 0 to bank 3 of the RASTER FIFO. When a given bit in RRBANK is 1, the data in the corresponding bank can be read out. When a given bit in RWBANK is 1, the data in the corresponding bank has not been written. 3. Input data format This section describes the format of the path (outline) data accepted by the MN5572. • Overall structure 32 bit Header data Path data Footer data • Header data structure bit 31 30 28 27 26 25 24 23 0 tag eof vth bpp 16 15 max. cov • Path data structure bit 31 30 28 27 0 tag 8 7 bbox. x 14 13 vect. x 0 bbox. y 0 vect. y • Footer data structure bit 31 30 0 12 28 27 tag 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDF00008BEM MN5572 ■ Functional Description (continued) 3. Input data format (continued) • Parameters tag Data attribute 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : header quadratic's or cubic's control point 1 cubic's control point 2 end of data begin contour end of line end of quadratic end of cubic eof Fill rule setting 0 : Fill the inside of the curve when the outline intersects. 1 : Do not fill the inside of the curve when the outline intersects. vth Threshold setting used when expanding binary data. 0: off 1: on bpp Output bit size setting per pixel 00 : 1 bits 01 : 2 bits 10 : 4 bits 11 : 8 bits max. cov Setting of gray levels in an expanded frame 0x01h to 0x7Fh (2 levels) (128 levels) bbox. x Expanded frame output data width (X) 0x00h to 0x1Fh (1 pixel) (32 pixels) bbox. y Expanded frame output data width (Y) 0x00h to 0x1Fh (1 pixel) (32 pixels) vect. x Path data coordinate (X) vect. y Path data coordinate (Y ) SDF00008BEM 13 MN5572 ■ Functional Description (continued) 4. Output data format This section describes the format of the gray-scale data output by the MN5572. • When bpp = 11 (Here, bbox.x = n and bbox.y = m.) 0 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] line 0 pix[8] pix[9] pix[10] pix[11] ..... ..... ..... ..... pix[n-2] pix[0] pix[4] pix[8] ..... pix[n-1] pix[1] pix[5] pix[9] ..... pix[n] pix[2] pix[6] pix[10] ..... pix[3] pix[7] pix[11] ..... pix[n-2] pix[n-1] pix[n] ..... ..... ..... pix[1] pix[5] pix[9] ..... pix[2] pix[6] pix[10] ..... pix[3] pix[7] pix[11] ..... pix[n-2] pix[n-1] pix[n] ..... ...... pix[0] pix[4] pix[8] ..... line 1 line m • When bpp = 10 (Here, bbox.x = n and bbox.y = m.) 0 1 pix[n-4] pix[0] pix[8] ..... pix[n-3] pix[1] pix[9] ..... pix[n-2] pix[2] pix[10] ..... pix[n-1] pix[3] pix[11] ..... pix[n] pix[4] pix[12] ..... pix[5] pix[13] ..... pix[6] pix[14] ..... pix[7] pix[15] ..... pix[n-4] pix[n-3] pix[n-2] pix[n-1] pix[n] ...... ..... ..... ..... ..... ..... ..... pix[0] pix[8] ..... pix[1] pix[9] ..... pix[2] pix[10] ..... pix[3] pix[11] ..... pix[4] pix[12] ..... pix[5] pix[13] ..... pix[6] pix[14] ..... pix[7] pix[15] ..... pix[n-4] pix[n-3] pix[n-2] pix[n-1] pix[n] SDF00008BEM line 1 ..... ...... 14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pix[0] pix[2] pix[4] pix[6] pix[1] pix[3] pix[5] pix[7] pix[8] pix[10] pix[12] pix[14] pix[9] pix[11] pix[13] pix[15] line 0 ..... ..... ..... ..... ..... ..... ..... ..... line m MN5572 ■ Functional Description (continued) 4. Output data format (continued) • When bpp = 01 (Here, bbox.x = 26 and bbox.y = m.) 0 1 2 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] pix[8] pix[9] pix[10] pix[11] pix[12] pix[13] pix[16] pix[17] pix[18] pix[19] pix[20] pix[21] pix[22] pix[23] pix[24] pix[25] pix[26] pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] pix[8] pix[9] pix[10] pix[11] pix[12] pix[13] pix[16] pix[17] pix[18] pix[19] pix[20] pix[21] pix[22] pix[23] pix[24] pix[25] pix[26] 3 2 1 0 pix[14] pix[15] line 0 pix[14] pix[15] line 1 ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ...... ...... ...... ...... pix[0] pix[1] pix[2] pix[3] pix[4] pix[5] pix[6] pix[7] pix[8] pix[9] pix[10] pix[11] pix[12] pix[13] pix[14] pix[15] line m pix[16] pix[17] pix[18] pix[19] pix[20] pix[21] pix[22] pix[23] pix[24] pix[25] pix[26] • When bpp = 00 (Here, bbox.x = 29 and bbox.y = m.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pix[0 : 29] line 0 pix[0 : 29] line 1 pix[0 : 29] line 2 ..... ..... ..... pix[0 : 29] line m line 0 to line m 0 1 2 pix[0] to pix[n] SDF00008BEM 15 MN5572 ■ Operation 1. Pin settings This section describes the pin setting conditions that control the operating state of the MN5572. 1. 1. Clock settings The interface clock and the internal operating clock are set using the clock setting pins, CLKSEL[2:0]. The application must provide the same external clock signal to the HOSTCLK (PCICLK) and ICLOCK pins. CLKSEL2 CLKSEL1 CLKSEL0 Interface block clock Internal operating clock 0 0 0 HOSTCLK (PCICLK) phase compensation applied Multiplier of ICLOCK 0 0 1 HOSTCLK (PCICLK) phase compensation applied ICLOCK 0 1 0 HOSTCLK (PCICLK) phase compensation applied ICLOCK duty compensation applied. 0 1 1 HOSTCLK (PCICLK) phase compensation applied ICLOCK 1. 2. Phase compensation circuit settings The interface clock phase compensation circuit is set from external pins. These settings are required when the PCI interface is used. Pin Name Setting Notes PLNRESET This pin should be held low (reset) when power is applied, and the held high at other times. HOSTCLK(PCICLK) Input frequency: 13 MHz to 33 MHz P2NPWD Connect high. When the circuit is not used, this pin may be held low to save power. 1. 3. Frequency multiplier circuit settings The internal operating clock frequency multiplier circuit can be set by external pins. • When the clock setting pins CLKSEL[1:0] are 00 (Multiplied clock setting) Pin Name Setting Notes PLNRESET This pin should be held low (reset) when power is applied, and the held high at other times. ICLOCK Input frequency P1NPWD Connect high. When the circuit is not used, this pin may be held low to save power. P1SEL[2 : 1] 16 Multiplier setting P1SEL2 P1SEL1 Multiplier ICLOCK frequency Internal operating frequency 0 0 forbidden 0 1 2 26 MHz to 33 MHz 52 MHz to 66 MHz 1 0 4 13 MHz to 16.5 MHz 52 MHz to 66 MHz SDF00008BEM MN5572 ■ Operation 1. Pin settings (continued) 1. 3. Frequency multiplier circuit settings (contined) • When the clock setting pins CLKSEL[1:0] are 01 (Duty compensated clock setting) Pin Name Setting Notes PLNRESET This pin should be held low (reset) when power is applied, and the held high at other times. ICLOCK Input frequency P1NPWD Must be held high. When the circuit is not used, this pin may be held low to save power. P1SEL[2 : 1] Multiplier setting P1SEL2 P1SEL1 Multiplier ICLOCK frequency Internal operating frequency 0 0 forbidden 0 1 2 26 MHz to 33 MHz 26 MHz to 40 MHz 1 0 4 13 MHz to 20 MHz 26 MHz to 40 MHz 2. Operating Procedures This section presents the operating procedures for using this IC. 2. 1. Operating Procedures Overview This section presents an overview of the processing used to operate this IC. • Initialization Initialization is the processing performed after either the input of either a hardware reset (NRST) or the execution of a software reset. Initialization clears the IC internal memory and sets up the operating conditions. • Path data write The path data write operation consists of the input processing for the path data used by the IC to generate multi-level gray-scale data. • Gray-scale data readout The gray-scale data readout operation consists of the output processing for the multi-level gray-scale data generated by this IC. • Interrupt signal wait The interrupt signal wait operation is the standby processing performed by the external CPU until this IC issues an external interrupt signal when interrupt controlled processing is used. SDF00008BEM 17 MN5572 ■ Operation 2. Operating Procedures (continued) 2. 2. Initialization processing example • Initialization processing flowchart Hardware or software reset start Status register check (status read) PMS, RMS = 00, MIS = 1, CES = 0, CCS = 0 Mask register setup (mask write) PM, RM, TM Initialization completion verification (status read) MIS = 0 end • Initialization processing flowchart example description The IC registers are initialized by a reset due to either a hardware reset (HRST) or a software reset. And then memory initialization processing starts automatically. • Status register check The values of each parameter are verified by reading the status register. • Mask register setup Sets the conditions for the interrupt signal (IRQ) generated by the IC. If the mask is not set here, interrupts are processed under the initial conditions. • Initialization completion verification Completion of the memory initialization processing started automatically after the reset is cleared, is verified by monitoring a status register parameter (MIS). Note) When the mask register TM field is set to 1: In this case, the IC will notify the application that memory initialization processing has completed by issuing an interrupt signal (IRQ). In this case, the interrupt is issued after a wait, and then it should be verified that MIS has become 0 by reading the status register. 18 SDF00008BEM MN5572 ■ Operation 2. Operating Procedures (continued) 2. 3. Path data write operation example • Path data write operation flowchart start Status register check (status read) PMS verification PMS read FULL PMS 11 : FULL 01 : READY 00 : EMPTY EMPTY or READY Path data write (up to 64 double words) Has 1 frame completed? No Yes end • Path data write operation flowchart description This operation writes the path data to be processed by the IC. • Status register check The status register is read and checked. • PMS verification The operation performed will be determined by the value of the status register PMS field. If the PMS field indicates that the FIFO is full, it means that there is no free space in the IC internal memory and the status register must be checked again after a wait. If the PMS field indicates empty or ready, a write operation can be started. • Path data write The path data for a single figure or font character is input to the path data input port (POINT FIFO). The maximum amount of path data that can be input at one time is 64 double words. If the data exceeds this amount, the data must be divided up into 64 double word units and those units must be processed individually. Fewer than 64 double words can be input if that data includes the path data end code (tag = 011). • Has 1 frame completed? If input of the path data for a single figure or font character has completed, the processing terminates. If the path data is being processed in multiple units, or if there is data that must be input, the status register must be checked again and another write operation must be performed. SDF00008BEM 19 MN5572 ■ Operation 2. Operating Procedures (continued) 2. 4. Gray-scale data readout processing • Gray-scale data readout processing flowchart start Status register check (status read) RMS, REC, RVS EMPTY RMS verification RMS 11 : FULL 01 : READY 00 : EMPTY RVS 00h(1 double-word) to 3Fh(64 double-word) FULL or READY Gray-scale data readout (up to 64 double words) Has 1 frame completed? REC = 0 REC = 1 end • Gray-scale data readout processing flowchart description This operation reads out the gray-scale data created by the IC. • Status register check The status register is read and checked. • RMS verification The operation performed will be determined by the value of the status register RMS field. If the RMS field indicates that the FIFO is empty, it means that the IC has not yet completed generation of the gray-scale data and the status register must be checked again after a wait. If the RMS field indicates ready, a read operation can be started. If the RMS field indicates full, the IC will have to interrupt its gray-scale data generation processing. Therefore, the available data should be read out as quickly as possible. • Gray-scale data readout The multi-valued gray-scale data for a single figure or font character is output from the IC gray-scale data output port (RASTER FIFO). The maximum amount of gray-scale data that can be output at a time is 64 double words. The amount of gray-scale data that can actually be output is indicated by RVS. If the amount of gray-scale data to be output exceeds 64 double words, the data will be broken up into 64 double words units and processed internally. If the REC field in the status register is 1, the multi-valued gray-scale data for a single figure or font character can be completely read out by reading out the amount of data indicated by RVS. 20 SDF00008BEM MN5572 ■ Operation 2. Operating Procedures (continued) 2. 4. Gray-scale data readout processing (continued) • Gray-scale data readout processing flowchart (continued) • Has 1 frame completed? Processing terminates if the gray-scale data readout operation has completed the output of the gray-scale data for a single figure or font character. The IC divides the gray-scale data into units internally, and if there is still data that must be output (REC = 0), another read operation must be performed again by checking the status register. 2. 5. Interrupt signal wait processing • Interrupt signal wait processing flowchart start Interrupt signal check IRQ = "L" IRQ = "H" Status register check (status read) IRQ = "H"→"L" MIS = 1→0 Interrupt verification RMS = 11 PMS = 00 Initialization complete Path data write Gray-scale data readout • Interrupt signal wait processing flowchart description The IC internal state changes can be verified from the generated interrupt signal. • Interrupt signal check The interrupt signal (IRQ) is monitored until the interrupt generation conditions set in the IC's mask register are met and the IC asserts (sets to the high level) the interrupt signal. • Status register check The status register is read and checked. After the status register is read, the IC deasserts the interrupt signal (IRQ). • Interrupt verification The reason the interrupt was generated is verified from the values of the MIS, PMS, and RMS fields in the status register. This determines what processing must be performed next. Note: Interrupt signal wait processing can not be used in PCI mode. In that case, the IC internal state changes should be determined by periodically reading the status register. SDF00008BEM 21 MN5572 ■ Operation 3. Sleep Mode Setup This section presents the procedure used to set the IC to sleep mode. 3. 1. Sleep mode overview This IC operating clock can be stopped and the IC set to sleep mode by issuing a CKSP command to the command register. If the IC is processing path data internally, a CKSP command should only be issued after that processing has completed. IC internal data is not guaranteed after a CKSP command is issued. Sleep mode is released by issuing a CKST command to the command register. After clearing sleep mode, normal mode operation can be restored by initializing the IC internally with the SRST command. • Sleep mode setup and release flow chart start CCS = 1 CKSP command Sleep mode setup Status register check (status read) Sleep mode CKST command Status register check (status read) CCS = 0 SRTS command Initialization processing 22 SDF00008BEM Sleep mode release MN5572 ■ Electrical Characteristics 1. Absolute Maximum Ratings Parameter Supply voltage 5 V reference voltage †1 Symbol Rating Unit VDD − 0.3 to +4.6 V VREF5 − 0.3 to +5.7 V VI − 0.3 to VDD+0.3 V Input pin voltage (other than TYPE * pins) VI5 − 0.3 to +6.0 Input pin voltage (TYPE-B) VI5 − 0.3 to VREF5+0.3 Output pin voltage (other than TYPE * pins) VO − 0.3 to VDD+0.3 VO5 − 0.3 to VREF5+0.3 Input pin voltage (TYPE-A) Output pin voltage (TYPE-D) †2 V †2 V V †2 V Output current (TYPE-HL4 pins) IO ±12 mA Output current (TYPE-HL8 pins) IO ±24 mA Power dissipation PD 720 mW Operating temperature Topr −40 to +70 °C Storage temperature Tstg −55 to +150 °C Note) 1. †1: The power on and off sequences must meet the following stipulations. VDD 0V t3-5 t5-3 VREF5 0 V t3-5 and t5-3 must be 0 or longer than 0. Both VDD and VREF5 must transit smoothly. †2: When VDD ≤ 1.4 V, the range is − 0.3 V to +4.6 V. 2. TYPE-A pins : P1NPWD, P2NPWD, NCBE0 to NCBE3, NRST, IDSEL, IFCFG, NIRDY, P1SEL1, P1SEL2, BUSSEL, CAPTON, CLKSEL0 to CLKSEL2, ICLOCK, NFRAME, PCICLK, TESTON, PLTPDIN, PLNRESET TYPE-B pins : AD0 to AD31, IRQ, PAR, NPERR, NSERR, NSTOP, NTRDY, NDEVSEL TYPE-D pins : AD0 to AD31, IRQ, PAR, NPERR, NSERR, NSTOP, NTRDY, NDEVSEL TYPE-HL4 pins : IRQ, OCLOCK TYPE-HL8 pins : AD0 to AD31, PAR, NPERR, NSERR, NSTOP, NTRDY, NDEVSEL 3. The absolute maximum ratings are limiting values under which the chip will not be destroyed. Operation is not guaranteed within these ranges. 4. All of the VDD and VSS pins must be connected to power supply and ground, respectively. 2. Recommended Operating Conditions at VSS = 0 V Parameter Min Typ Max Unit VDD 3.0 3.3 3.6 V 5 V reference voltage VREF5 4.75 5.0 5.25 V Ambient temperature Ta 0 70 °C Input rise time tr 0 100 ns Input fall time tf 0 100 Supply voltage Symbol Conditions SDF00008BEM 23 MN5572 ■ Electrical Characteristics (continued) 3. DC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 66 MHz, Ta = 0°C to +70°C Parameter Quiescent supply current Symbol Conditions Min Typ Max Unit IDDS VI (pull up)= OPEN VI (pull down) = OPEN Either the VDD or the VSS level must be applied to all other input pins and I/O pins in the high-impedance state. 200 µA ±20 µA 90 180 mA 5 V reference supply (VREF5) input leakage current IREF Operating supply current IDDO VI = VDD or VSS f = 66 MHz VDD = 3.3 V, outputs open CMOS level inputs with built-in pull-down resistors: MINTEST High-level input voltage VIH VDD × 0.7 VDD V Low-level input voltage VIL 0 VDD × 0.3 V Pull-down resistor RIL VI = VDD 10 30 90 kΩ Input leakage current ILIL VI = VSS ±10 µA LVTTL level inputs with built-in pull-down resistors: PLTEST High-level input voltage VIH 2.0 VDD V Low-level input voltage VIL 0 0.8 V Pull-down resistor RIL VI = VDD 10 30 90 kΩ Input leakage current ILIL VI = VSS ±10 µA TTL level inputs: P1NPWD, P2NPWD, NCBE0 to NCBE3, NRST, IDSEL, IFCFG, NIRDY, P1SEL1, P1SEL2, BUSSEL, CAPTON, CLKSEL0 to CLKSEL2, ICLOCK, NFRAME, PCICLK, TESTON, PLTPDIN, PLNRESET High-level input voltage VIH 2.0 5.25 V Low-level input voltage VIL 0 0.8 V Input leakage current ILI ±10 µA VI = 5.25 V or VSS Push-pull outputs : OCLOCK High-level output voltage VOH IOH = −4.0 mA VI = VDD or VSS VDD− 0.6 V Low-level output voltage VOL IOL = 4.0 mA VI = VDD or VSS 0.4 V 24 SDF00008BEM MN5572 ■ Electrical Characteristics (continued) 3. DC Characteristics (continued) at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 66 MHz, Ta = 0°C to +70°C Parameter Symbol Conditions Min Typ Max Unit TTL level I/O pins: IRQ High-level input voltage VIH 2.0 VREF5 V Low-level input voltage VIL 0 0.8 V High-level output voltage VOH IOH = −4.0 mA VI = VDD or VSS 2.4 V Low-level output voltage VOL IOL = 4.0 mA VI = VDD or VSS 0.4 V Output leakage current ILO VO = high-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS ±10 µA TTL level I/O pins: AD0 to AD31, PAR, NPERR, NSERR, NSTOP, NTRDY, NDEVSEL High-level input voltage VIH 2.0 VREF5 V Low-level input voltage VIL 0 0.8 V High-level output voltage VOH IOH = −8.0 mA VI = VDD or VSS 2.4 V Low-level output voltage VOL IOL = 8.0 mA VI = VDD or VSS 0.4 V Output leakage current ILO VO = high-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS ±10 µA 4. PLL Characteristics VSS = 0.0 V, VDD = 3.3 V, Ta = 25 °C Parameter Symbol Conditions Min Typ Max Unit 50 80 MHz Min Typ Max Unit 26 66 MHz Clock generator (PLL): ICLOCK PLL oscillation frequency fICLOCK Multiplier: 2 fICLOCK = 26 MHz to 40 MHz Multiplier: 4 fICLOCK = 13 MHz to 20 MHz Multiplier: 6 fICLOCK = 9 MHz to 13 MHz VSS = 0.0 V, VDD = 3.3 V, Ta = 25 °C Parameter Symbol Conditions Clock generator (PLL): PCICLK PLL oscillation frequency fPCICLK fPCICLK = 13 MHz to 33 MHz SDF00008BEM 25 MN5572 ■ Electrical Characteristics (continued) 4. PLL Characteristics (continued) <PLL Reset Timing: ICLOCK> You should insert a delay of at least 50 ns after the rise of either P1VDD or P1NPWD, whichever occurs later, and then bring PLNRESET up to the high level. Also, if P1VDD is high, you should raise PLNRESET when P1NPWD is set low. (1) P1VDD P1NPWD PLNRESET 50 nsec (2) P1NPWD P1VDD PLNRESET 50 nsec <PLL Reset Timing: PCICLK> You should insert a delay of at least 50 ns after the rise of either P2VDD or P2NPWD, whichever occurs later, and then bring PLNRESET up to the high level. Also, if P2VDD is high, you should raise PLNRESET when P2NPWD is set low. (1) P2VDD P2NPWD PLNRESET 50 nsec (2) P2NPWD P2VDD PLNRESET 50 nsec 26 SDF00008BEM MN5572 ■ Package Dimensions (Unit: mm) • LQFP100-P-1414 (Lead-free package) 16.00±0.20 14.00±0.10 51 75 50 100 26 16.00±0.20 1.40±0.10 25 0.20±0.05 0.10 M 0.10 Seating plane SDF00008BEM (1.00) 0.15±0.05 0.50 0.10±0.10 (1.00) 1.70 max. 1 14.00±0.10 (1.00) 76 0° to 10° 0.50±0.20 27 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. 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