Digital Broadcast Reception LSI MN88413 Channel Decoder LSI for Digital Satellite Broadcast Reception ■ Overview The MN88413 is a channel decoder LSI that integrates functions for digital satellite communications and broadcast reception on a single chip. The MN88413 supports both the Digital Video Broadcast (DVB) and the Digital Satellite System (DSS) specifications. It also supports a variable transport rate that can be set under program control using a fixed system clock frequency and can implement a channel decoder with a minimal number of external components. ■ Features • Can be used in systems conforming to DVB, in US DIRECTV systems, and in single carrier per channel (SCPC) communication systems. • Integrates a 2-channel A/D converter, a variable rate QPSK demodulator, and forward error correction (FEC) on a single chip. • Supports transfer rates from 1 Mbps to 90 Mbps. • On-chip I/Q baseband signal offset voltage circuit and on-chip reference voltage circuit for the A/D and D/A converters. • On-chip PLL circuit • BER monitor function • I2C bus master circuit for tuner control • Supports LNB control clock and DiSEqC 1.0/1.1 and can output DiSEqC messages. • General-purpose input and output ports • On-chip boundary scan test circuit conforming to IEEE 1149.1 ■ Applications • Digital satellite broadcast receivers Note: DSS and DIRECTV are registered trademarks of DIRECTV, Inc. 1 PLL0-2 CPO 2 PLL Clock reproduction I2C I/F (Master) I2C I/F TDI TMS TCK TRST TDO ADC SADR0-1 SCL SDA QIN ADC MSCL MSDA IIN TAP controller (JTAG) LNB controller Energy dispersal decoder Reed-Solomon decoder De-interleaver Frame synchronization detector Viterbi decoder QPSK demodulator Roll-off filter Rate converter Bandwidth limiter Digital AFC Offset canceler AGC XI XO CKI CSEL0-1 SEL NRST TEST0-2 TIN3-7 DAIR DAVR QVRM IVRM ADVRB ADVRT VSSC0-19 VDDA1-2 VSSA0-2 VDD0-6 VSS0-6 MN88413 Digital Bloadcast Reception LSI ■ Block Diagram DAC NERRF FSYNC DAC DO0-7 DEN BYTCK PSYNC NPERR SCK OP0-2 LNBCK LNB Digital Bloadcast Reception LSI MN88413 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TCK TMS TRST VSSC14 SCK DO7 VDD4 VSSC13 VSS4 DO6 DO5 DO4 VSSC12 DO3 DO2 DO1 VDD3 VSSC11 VSS3 DO0 BYTCK VSSC10 DEN PSYNC NPERR ■ Pin Assignment 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PLL2 PLL1 PLL0 VSSC9 VDD2 VSS2 NERRF VSSC8 FSYNC SEL NRST SDA VSSC7 SCL VDD1 VSS1 MSDA VSSC6 MSCL SADR1 SADR0 VSSC5 TEST2 TEST1 TEST0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 CKI VSS0 VDD0 VSSC0 VSSA0 CPO VDDA0 VSSC1 DAVR DAIR LNB AGC VSSC2 VDDA1 VSSA1 IIN IVRM VSSC3 ADVRT ADVRB QVRM VSSC4 QIN VSSA2 VDDA2 TDI TDO TIN3 VSSC15 TIN4 VSS5 VDD5 VSSC16 TIN5 TIN6 TIN7 OP0 VSSC17 OP1 OP2 LNBCK CKO VSSC18 VSS6 VDD6 XO VSSC19 XI CSEL0 CSEL1 3 MN88413 Digital Bloadcast Reception LSI ■ Specifications Overview • QPSK demodulator Data rate A/D converter resolution Linearity error Differential linearity error : 1 Mbps to 90 Mbps : 6 bits : ±0.5 LSB (typical) : ±0.5 LSB (typical) Input voltage level Roll-off rate : 1.5 V [p-p] (typical) [On-chip self-bias circuit] : Switchable between the DVB and the DSS specifications. AFC range Synchronization establishment time : ± (<symbol rate>/8) : 100 ms or less. D/A converter used for LNB/AFC and AGC Resolution : 8 bits Linearity error Differential linearity error : ±0.5 LSB (typical) : ±0.5 LSB (typical) Output voltage level : 1.0 V [p-p] (typical) [0.0 V to 1.0 V] • Viterbi decoder : Switchable between the DVB and the DSS specifications. : Automatic detection of encoding ratios in the range 1/2 to 7/8. : Auto-synchronous operation • Frame synchronization detection, De-interleaver, Reed-Solomon decoding, and Energy dispersal : Switchable between the DVB and the DSS specifications. • PLL circuit : Reference clock input frequency: 4 MHz to 30 MHz • CPU interface : I2C bus interface • Supply voltage : 3.3 V ±0.165 V • Power dissipation : 990 mW (typical) [at VDD = 3.3 V, 60 Mbps, R = 7/8] • Package : QFP100-P-1818B (18 × 18 mm) 4 Digital Bloadcast Reception LSI MN88413 ■ System Application Example Antenna 12 GHz Tuner AGC 950 MHz ∼ 1.45 GHz BPF BPF AN8921SB IIN QIN DO0-7 BYTCK PSYNC 1.45 GHz ∼ 1.95 GHz NPERR DEN 500 MHz SCK AGC 8 To the descrambler Quadrature detector MN88413 XI XO LNB control I2C master Microcontroller MN1870877 I2C interface I2C host interface ■ Package Dimensions (units: mm) 22.90±0.20 18.00±0.10 75 51 (1.20) • QFP100-P-1818B 50 100 26 25 0.30±0.05 0.15 Seating plane 0.15±0.05 0.65 0.10±0.10 1 (1.20) 2.45±0.20 2.85max. 18.00±0.10 22.90±0.20 76 (2.45) 0 to 10° 1.30±0.20 5