1-6H005 12-Bit AID Converter 8-94 ITAC HYBRID TECHNOLOGY InterFET Features f--_ _-oBipolar Offset Parallel Digital Output :!!!:C1 }j "i f------oRef In L l1J iii!! 5::! B 12-81t SUccessive Approximation Register (SAR) Ref Out Input ""'''.I\/'--O L.------o JRange Select Convert Command i=--:-l-------oClock Out L...:..:..::...:~j-------oClock -oStatus L.- Rate Adjustment ' - - - - - - - - - - - - - o S e r i a J Out LSB B1112 <D Bn11 Bn10 Bn 9 ® 0 <D ® ® "$ Bn 8 ~ Bn :g; Btt6(!) ~ BH Btt 4 Btt 3 ® ® @ ® Btt 2 MSBBlt 1 MSBM 1 @ @ Olgttal Common ® @ serial Out Top bll hl @ @ I Reference I @ @ 5kn 5JlP. @ ;.~ @ 9.9kn @ @ I- - @ r @ View 1IJ i '•• J.. . .§ :!!!: Cl ii .J ~ ~ ® r----l 12-Blt Suc:cesslve ApproxllT8 lion Register ISAR) @) @ .... -15VDC S1w1y +15VDC SUpply RefOut+10V Analog Common 20VRange 10VRange Bpolar Offset Convert Command status Clodl Out Refln Clodl Rate +5VDCSIWIy L;~p.~ Clock 12-BitSuccessive Approximation Register (SAR) 151 _ _ _ _ _ _ _ _---:1....;.:4 _ 1.395 (35.40) 1.465 (37.21) --II-- 0.065 (1.65) Leads in true position within 0.0100 • Pin Numbers forreference only. T Numbers may not be marked 0.610 Typ. on the package. (15.49) Typ. 1 seating Plane 0.025 (0.63) 0.065 (1.65) ~\ 1_ --II-0.015 (0.38) 0.020 (0.50) --I I-0.100 Typ. (2.54) Typ. --I 0.025 (0.63) 0.065 (1.65) 0.135 (3.40) 0.205,(5.21) 0.009 (0.23) 0.012 (0.30) f ;~ 0.150 (3.80) 0.195 (4.95) 0.600 Typ. (15.24) Typ. --I I- • - 55°C to + 200°C Specifications • 50 psec Maximum Conversion Time • No Missing Codes Over Full Temperature Range • Complete With Internal Clock and Reference Voltage • Serial Output Data Available • TTL and +5V CMOS Compatible • Hermetic Package • Low Power Operation with External Reference (250mW) • Pin Compatible with Burr Brown ADC10HT Description The 1-6HOOS general purpose, 12-bit, successive approximation NO converter is ideally qualified for circuits that must operate over wide temperature ranges. The 1-6HOOS incorporates state-of-the art IC and laser-trimmed components. It is complete with an internal clock and reference voltage. Internal scaling resistors allow bipolar input voltage ranges of ±SV and ±10V. A pin is provided for serial output data. The 1-6HOOS is contained in a compact, dual-width, 28-pin hermetic OIL package and is fully PIN compatible with the Burr Brown AOC10HT. 100% screened versions available upon request. Refer to Table lion the back page for example. ~ InterFET (972) 238-1287 ~,(214) 487-1287 FAX (972) (214)238-5338 276-3375 8-94 1-6H005 12-Bit AID Converter ITAC HYBRID TECHNOLOGY InterFET Table II - 100% Device Screening I METHOD· I I TEST SCREEN 1. 2. Precap Internal Visual High Temperature Storage 2017 1008 Conditions C, TA = 150°C. Time = 24 hours minimum 3. 4. Temperature Cycling Constant Acceleration 1010 2001 Condition C, -65°C to + 150°C, 10Cycles Condition A, 5KGs, Y, and Y2 axis only. 5. 6. 7. 8. Fine Leak Gross Leak Interim Electrical Test Burn-In 1014 1014 9. Final Electrical Test Condition A Condition C Optional Condition B, Time = 160 hours minimum. TA = +5°C, VCC = 5.5V, IF = 20mA, ID = 25mA. Group A, Subgroup 1, 10% PDA applies. Group A, Subgroup 2, 3, 9. 10. External Visual • CONDITIONS 1015 2009 Refers to screening as defined in MIL-H-38534.lnterFET is not certified and does not imply certification byreferencing these methods. Timing Diagram 1 - - - - - - - - - Maximum Throughput Time 2 Conversion Time Status (EOC) (MSB) Bit 1 (0) Bit 2 (1) Bit 3 (1) Bit 4 (0) Bit 5 (0) Bit 6 (1) Bit 7 (1) Bit 8 (1) Bit 9 (0) Bit 10 (1) Bit 11 (1) (LSB) Bit 12) (0) ------------1 ~ _ ,'---- ----lr- r- L...-.. ----------, L. == e --'r- 1100 110 11 0 1 L----.J L----.J L----.J - Bit Number 1 7 8 9 10 11 2 3 4 5 6 12 (MSB) (LSB) Notes: 1. The internal clock runs continuously. The Convert Command must go low atleast 80 nSec before the rising edge of any clock pulse to initiate a conversion, and must return high atlease 80 nSec before the next low to high clock transition. 2. The maximum throughput time is54 ~Sec for 12bits. 3. Ifserial data isstrobed, use the trailing edge of the clock. During data conversion, the determination InterFET as to the proper state of any bit (bit lin") ismade on the rising edge of the clock pulse and the parallel output data isconsidered valid atthe negative edge ofthe clock cycle (actually valid following the clock (972) 238-1287 ~,(214) 487-1287 low to high transition). The serial output then is clocked atthe next clock cycle, thus it will recolre 13 FAX (972) (214)276-3375 238-5338 clock steps to obtain the correct serial 12bit data. Thus valid serial data isprovided at clock "nil + 1. Serial Data Out3 A 8-94 1-6H005 12-Bit AID Converter ITAC HYBRID InterFET TECHNOLOGY Electrical Characteristics Conditions I Min 1,-----;-T_Y_p..,.,.------':-I_--:-M_a:-x_--'-- Table 1. Specifications at rated power supply voltages and TA = +25°Cunless otherwise noted. I RESOLUTION I I I 12 1 Units _ Bits 1 INPUT ANALOG Voltage Ranges Impedance (direct input) DIGITAL1 Convert Command Logic Loading - 55°C to + 200°C (972) 238-1287 Unipolar oto + 10to + 20 (972) 238-1287 Bipolar ± 5, ± 10 (972) 238-1287 oto 10V, ± 5V 5 k.Q oto + 20V, ± 10V 10 k.Q 1 CMOS Load - 55°C to + 200°C TRANSFER CHARACTERISTICS - ACCURACY Gain Error2 Offset Error3 ±0.2 % Unipolar ± 0.05 ±0.O5 ±0.2 Bipolar ±0.05 ± 0.2 ± 0.012 % ofFSR3 % ofFSR % ofFSR LSB % ofFSR % of FSR % ofFSR % of FSR % ofFSR % ofFSR Linearity Error Inherent Quantization Error Differential Linearity Error Total Unadjusted Error6 Exclusive of Reference + 25°C - 55°C to + 200°C + 25°C - 55°C to + 200°C + 25°C - 55°C to + 200°C Total Adjusted Error? Exclusive ofReference + 25°C - 55°C to + 200°C Total Unadjusted Error4 Total Adjusted Error5 ± 1/2 ± 0.012 ± 0.10 ±0.30 ± 0.006 ± 0.2 I CONVERSION TIME Gain With Internal Reference Gain Exclusive of Reference Offset Offset With Internal Reference Offset Exclusive of Reference Linearity No Missing Codes Over Temp. Range ~ InterFET (972) 238-1287 ~,(214J 487-1287 FAX (972) (214J238-5338 276-3375 V V Bipolar Bipolar 12 ±1 ± 0.012 ±O.,p ±OA ±0.2 ±0.8 ± 0.006 ± 0.012 % ofFSR % of FSR ± 0.15 ±OA % of FSR 30 50 usec ±15 ±35 ±10 ppm/oC ppm/oC ±0.5 - 55°C to + 200°C ±OA ± 0.1 ±5 ±2 ±10 ±4 Unipolar ± 0.024 ±35 ±1 ±1 ppm of FSR/oC ppm of FSR/oC ppm of FSR/oC ppm of FSR/oC Bits _ 8-94 1-6H005 12-Bit AID Converter IlAC HYBRID TECHNOLOGY InterFET Min I Typ I Max I Units Table 1. (Continued) Specifications at rated power supply voltages and TA = +25°C unless otherwise noted. OUTPUT - DIGITAL DATA Unipolar SB Parallel Output Codes B OB,TC Bipolar9 Parallel Output Drive LSTrL Loads 1 Serial Data Code (NZR) SB, OB LSTrL Loads 1 Serial Output Drive Status Logic "1" during conversion Status Output Drive LSTIL Loads 1 Internal Clock - Output Drive LSTrL Loads 1 Internal Clock - Frequency kHz 400 Electrical Characteristics IConditions I r POWER SUPPLY & REFERENCE Rated Voltage vcc ± 14.5 ±15 VDC VDD ± 4.75 ±5 VDC +15 -30 mA rnA rnA + VCC Supply Drain -VCC VDD Power Supply Sensitivity ±VCC +16 0.01 0.10 % of FRS/% VCC VDD 0.01 0.10 % of FRS/% VDD 10 10.010 V Internal Reference Voltage Max Extemal Current with no degradaton of specs Temperature Coefficient 9.990 2 . rnA ppm/oC ±10 TEMPERATURE RANGE I Operating + 200 Storage + 200 Notes 1. + 5V CMOS compatible. Input current (low to high) = 1 ~A max. Use pull-Up resistor when driving convert command from m. 2. Adjustrable to zero. 3. FSR means Full scale Range. For example, connected fora ± 1OV has a 20V FSR. 4. Includes Gain, Offset, and Linearity Errors (Bipolar Mode). 5. Gain, Offset, Errors removed at + 25°C (Bipolar Mode). 4. Includes Gain, Offset, and Linearity Errors with external + 10V ± 1mV reference; does not include Reference Drift (Bipolar Mode). 5. Gain, Offset, Errors removed at + 25°C with external + 1OV ± 1mV reference; does not include Reference Drift (Bipolar Mooe). 8. SB - Straight Binary; OB - Offset Binary; TC - Two's Complement. 9. TC cooing obtained by useing MSB - pin 13 - instead of MSB - pin 12. ~ InterFET 238-1287 ~,(972) [214)487-1287 FAX (972) [214) 238-5338 276-3375