74LVC08A-Q100
Quad 2-input AND gate
Rev. 2 — 19 April 2016
Product data sheet
1. General description
The 74LVC08A-Q100 provides four 2-input AND gates.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
74LVC08AD-Q100
Temperature
range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC08APW-Q100 40 C to +125 C
74LVC08ABQ-Q100
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
4. Functional diagram
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PQD
Fig 1.
Logic symbol
74LVC08A_Q100
Product data sheet
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
PQD
Fig 3.
Logic diagram for one gate
© NXP Semiconductors N.V. 2016. All rights reserved.
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74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
5. Pinning information
5.1 Pinning
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(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data input
1B to 4B
2, 5, 10, 13
data input
1Y to 4Y
3, 6, 8, 11
data output
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
Output
nA
nB
nY
L
X
L
X
L
L
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care
74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
output voltage
output HIGH or LOW-state
IO
output current
VO = 0 V to VCC
ICC
supply current
IGND
ground current
total power dissipation
Tstg
storage temperature
Max
Unit
0.5
+6.5
V
50
-
0.5
+6.5
V
-
50
mA
0.5
VCC + 0.5
VO > VCC or VO < 0 V
VO
Ptot
Min
Tamb = 40 C to +125 C
[2]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
For SO14 packages: above 70 C derate linearly with 8 mW/K.
V
-
50
mA
-
100
mA
100
-
mA
-
500
mW
65
+150
C
[3]
[1]
mA
For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
Conditions
functional
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate
74LVC08A_Q100
Product data sheet
output HIGH or LOW-state
Min
Typ
Max
Unit
1.65
-
3.6
V
1.2
-
-
V
0
-
5.5
V
0
-
VCC
V
40
-
+125
C
VCC = 1.65 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 3.6 V
0
-
10
ns/V
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
VOH
HIGH-level
output
voltage
LOW-level
output
voltage
VOL
VCC = 1.2 V
Typ[1]
40 C to +125 C
Max
Min
Max
Unit
1.08
-
-
1.08
-
V
0.65 VCC
-
-
0.65 VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
0.12
V
VCC = 1.65 V to 1.95 V
VCC = 1.2 V
-
-
0.12
-
VCC = 1.65 V to 1.95 V
-
-
0.35 VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC 0.2
-
-
VCC 0.3
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
1.05
-
V
IO = 8 mA; VCC = 2.3 V
1.8
-
-
1.65
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
2.05
-
V
IO = 18 mA; VCC = 3.0 V
2.4
-
-
2.25
-
V
IO = 24 mA; VCC = 3.0 V
2.2
-
-
2.0
-
V
IO = 100 A;
VCC = 1.65 V to 3.6 V
-
-
0.2
-
0.3
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.65
V
IO = 8 mA; VCC = 2.3 V
-
-
0.6
-
0.8
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
0.35 VCC V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
VI = VIH or VIL
II
input leakage VCC = 3.6 V; VI = 5.5 V or GND
current
-
0.1
5
-
20
A
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.1
10
-
40
A
ICC
additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
-
5
500
-
5000
A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
4.0
-
-
-
pF
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
propagation delay
tpd
40 C to +85 C
Conditions
Min
Max
Min
Max
-
11.0
-
-
-
ns
VCC = 1.65 V to 1.95 V
0.5
4.2
9.0
0.5
10.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.5
6.9
1.0
8.0
ns
VCC = 2.7 V
1.5
2.5
4.8
1.5
5.6
ns
VCC = 3.0 V to 3.6 V
1.0
2.3
4.1
1.0
4.8
ns
-
-
1.0
-
1.5
ns
[2]
nA, nB to nY; see Figure 6
VCC = 1.2 V
tsk(o)
power dissipation
capacitance
CPD
[1]
output skew time
40 C to +125 C Unit
Typ[1]
VCC = 3.0 V to 3.6 V
[3]
per gate; VI = GND to VCC
[4]
VCC = 1.65 V to 1.95 V
-
4.4
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
7.7
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
10.5
-
-
-
pF
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
11. AC waveforms
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VM = 1.5 V at VCC 2.7 V
VM = 0.5 VCC at VCC < 2.7 V
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
The input nA, nB to output nY propagation delays
74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
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Test data is given in Table 8. Definitions for test circuit:
RL = Load resistance
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
Fig 7.
Table 8.
Test circuit for measuring switching times
Test data
Supply voltage
Input
Load
VI
tr, tf
CL
RL
1.2 V
VCC
2 ns
30 pF
1 k
1.65 V to 1.95 V
VCC
2 ns
30 pF
1 k
2.3 V to 2.7 V
VCC
2 ns
30 pF
500
2.7 V
2.7 V
2.5 ns
50 pF
500
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 14
74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
12. Package outline
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74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 14
74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
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74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 14
74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
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74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74LVC08A-Q100
NXP Semiconductors
Quad 2-input AND gate
13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
MIL
Military
14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
74LVC08A_Q100 v.2
20160419
Product data sheet
Modifications:
74LVC08A_Q100 v.1
74LVC08A_Q100
Product data sheet
•
Change notice
Supersedes
74LVC08A_Q100 v.1
Table 2: Pin description for 1A to 4A inputs and 1Y to 4Y outputs swapped (errata).
20120731
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
-
© NXP Semiconductors N.V. 2016. All rights reserved.
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Quad 2-input AND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC08A_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
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Quad 2-input AND gate
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVC08A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 14
NXP Semiconductors
74LVC08A-Q100
Quad 2-input AND gate
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 April 2016
Document identifier: 74LVC08A_Q100