TDA5221

P rel imin ar y S p ecif ica t ion , V 1 .1 , Oct o be r 20 0 4
TDA 5221
ASK/ FS K Sin gle Co nve rsio n Re ceiver
Ver s i on 1 .1
W i re l e s s C o n t r o l
Co mpo ne nts
N e v e r
s t o p
t h i n k i n g .
Edition 2004-10-20
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
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P rel imin ar y S p ecif ica t ion , V 1 .1 , Oct o be r 20 0 4
TDA 5221
ASK/ FS K Sin gle Co nve rsio n Re ceiver
Ver s i on 1 .1
W i re l e s s C o n t r o l
Co mpo ne nts
N e v e r
s t o p
t h i n k i n g .
TDA 5221
Revision History:
2004-10-20
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TDA 5221
Table of Contents
Page
1
1.1
1.2
1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
2.4.10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASK/FSK-Data Path Functional Description . . . . . . . . . . . . . . . . . . . . . . .
FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
21
22
22
23
25
26
28
28
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.3
4.4
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics at TAMB= -40 to 105°C . . . . . . . . . . . . . . . . . . . .
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
32
32
32
33
39
42
43
44
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Preliminary Specification
5
6
6
6
6
V 1.1, 2004-10-20
TDA 5221
Product Description
1
Product Description
1.1
Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiver (SHR) for the frequency band 300 to 340 MHz. The IC offers a high level of
integration and needs only a few external components. The device contains a low noise
amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a
crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, an
advanced data comparator (slicer) with selection between two threshold modes and a
peak detector. Additionally there is a power down feature to save current and extend
battery life, and two selectable alternatives of generating the data slicer threshold.
1.2
•
•
•
•
•
•
•
•
•
•
•
•
Low supply current (Is = 6.4 mA typ. in FSK mode, Is = 5.6 mA typ. in ASK mode)
Supply voltage range 5V ±10%
Power down mode with very low supply current (50nA typ.)
FSK and ASK demodulation capability
Fully integrated VCO and PLL Synthesiser
ASK sensitivity better than -110 dBm over specified temperature range (- 40 to
+105°C)
Selectable frequency ranges 300-320 MHz and 320-340 MHz
Switchable between two different frequency channels (see Section 2.4.3)
Limiter with RSSI generation, operating at 10.7MHz
2nd order low pass data filter with external capacitors
Data slicer with selection between two threshold modes (see Section 2.4.8)
FSK sensitivity better than -102 dBm over specified temperature range (- 40 to
+105°C)
1.3
•
•
•
•
Features
Application
Keyless Entry Systems
Remote Control Systems
Alarm Systems
Low Bitrate Communication Systems
Preliminary Specification
6
V 1.1, 2004-10-20
TDA 5221
Functional Description
2
Functional Description
2.1
Pin Configuration
Figure 1
CRST1
1
28
CRST2
VCC
2
27
PDW N
LN I
3
26
PDO
TAGC
4
25
DATA
AGND
5
24
3VO U T
LN O
6
23
THRES
VCC
7
22
FFB
MI
8
21
OPP
M IX
9
20
SLN
AGND
10
19
SLP
FSEL
11
18
L IM X
IF O
12
17
L IM
DGND
13
16
SSEL
VDD
14
15
MSEL
TD A 5221
Pin Configuration
Preliminary Specification
7
V 1.1, 2004-10-20
TDA 5221
Functional Description
2.2
Pin Definition and Functions
Table 1
Pin Defintion and Function
Pin
No.
Symbol
1
CRST1
Equivalent I/O Schematic
Function
External Crystal
Connector 1
4.15V
1
50uA
2
VCC
5V Supply
3
LNI
LNA Input
57uA
3
500uA
4k
1k
Preliminary Specification
8
V 1.1, 2004-10-20
TDA 5221
Functional Description
Pin
No.
Symbol
4
TAGC
Equivalent I/O Schematic
Function
AGC Time
Constant Control
4.3V
3uA
4
1k
1.4uA
1.7V
5
AGND
6
LNO
Analogue
Ground Return
LNA Output
5V
1k
6
7
VCC
Preliminary Specification
5V Supply
9
V 1.1, 2004-10-20
TDA 5221
Functional Description
Pin
No.
Symbol
8
MI
Equivalent I/O Schematic
Function
Mixer Input
1.7V
9
2k
MIX
2k
Complementary
Mixer Input
8
9
400uA
10
AGND
Analogue
Ground Return
11
FSEL
Frequency
Selector
1.
40k
11
12
IFO
10.7 MHz IF
Mixer Output
300uA
2.2V
60
12
4.5k
13
DGND
Preliminary Specification
Digital Ground
Return
10
V 1.1, 2004-10-20
TDA 5221
Functional Description
Pin
No.
Symbol
Equivalent I/O Schematic
Function
14
VDD
5V Supply (PLL
Counter Circuity)
15
MSEL
ASK/FSK
Modulation
Format Sector
1.2V
40k
15
16
SSEL
Data Slicer
Reference Level
Sector
1.2V
40k
16
17
LIM
Limiter Input
2.4V
15k
18
LIMX
Complementary
Limiter Input
17
330
75uA
18
15k
Preliminary Specification
11
V 1.1, 2004-10-20
TDA 5221
Functional Description
Pin
No.
Symbol
19
SLP
Equivalent I/O Schematic
Function
Data Slicer
Positive Input
15uA
100
3k
19
80µA
20
SLN
Data Slicer
Negative Input
5uA
10k
20
21
OPP
OpAmp
Noninverting
Input
5uA
200
21
22
FFB
Data Filter
Feedback Pin
5uA
100k
22
Preliminary Specification
12
V 1.1, 2004-10-20
TDA 5221
Functional Description
Pin
No.
Symbol
23
THRES
Equivalent I/O Schematic
Function
AGC Threshold
Input
5uA
10k
23
24
3VOUT
3V Reference
Output
24
20kΩ
3.1V
25
DATA
Data Output
500
25
40k
26
PDO
Peak Detector
Output
26
446k
Preliminary Specification
13
V 1.1, 2004-10-20
TDA 5221
Functional Description
Pin
No.
Symbol
27
PDWN
Equivalent I/O Schematic
Function
Power Down
Input
27
220k
220k
28
CRST2
External Crystal
Connector 2
4.15V
28
50uA
Preliminary Specification
14
V 1.1, 2004-10-20
TDA 5221
Functional Description
2.3
Functional Block Diagram
VCC
IF
Filter
MSEL
H=ASK
L=FSK
MI
LNO
6
LNI
RF
3
MIX
8
9
IFO
LIM
12
FFB
LIMX
17
18
OPP
22
15
SLP
21
19
20
Logic
+ CM
LNA
TDA 5221
4
SSEL
25
DATA
DATASLICER
OP
-
LIMITER
+ FSK
- ASK
+
+
FSK
PLL Demod
16
+ CP
-
-
TAGC
SLN
PEAK
DETECTOR
PDO
26
OTA
:2
VCC
VCO
: 128
: 129
Φ
DET
:2
U REF
CRYSTAL
OSC
AGC
Reference
23
THRES
24
3VOUT
14
Bandgap
Reference
Loop
Filter
DGND
13
2,7
5,10
VCC
AGND
11
28
1
27
PDWN
FSEL
Crystal
Figure 2
Block Diagram
2.4
Functional Block Description
2.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain
figure is determined by the external matching networks situated ahead of LNA and
between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9).
The noise figure of the LNA is approximately 3dB, the current consumption is 500µA.
The gain can be reduced by approximately 18dB. The switching point of this AGC action
can be determined externally by applying a threshold voltage at the THRES pin (Pin 23).
This voltage is compared internally with the received signal (RSSI) level generated by
the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the
LNA gain is reduced and vice versa. The threshold voltage can be generated by
attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a
temperature stable 3V output generated from the internal bandgap voltage and the
THRES pin as described in Section 3.1. The time constant of the AGC action can be
determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operating case
and interference scenario to be expected during operation. The optimum choice of AGC
time constant and the threshold voltage is described in Section 3.1.
Preliminary Specification
15
V 1.1, 2004-10-20
TDA 5221
Functional Description
2.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 310350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-tage gain of
approximately 21dB by utilising either high- or low-side injection of the local oscillator
signal. In case the mixer is interfaced only single-ended, the unused mixer input has to
be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner
frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin).
The IF output is internally consisting of an emitter follower that has a source impedance
of approximately 330Ω to facilitate interfacing the pin directly to a standard 10.7MHz
ceramic filter without additional matching circuitry.
2.4.3
PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain,
a phase detector with charge pump and a loop filter and is fully implemented on-chip.
The VCO is including spiral inductors and varactor diodes. The tuning range of the VCO
was designed to guarantee over production spread and the specified temperature range
a receive frequency range between 300 and 340 MHz depending on whether high- or
low-side injection of the local oscillator is used. The oscillator signal is fed both to the
synthesiser divider chain and to a divider that is dividing the signal by 2 before it is
applied to the downconverting mixer. Local oscillator high side injection has to be used
for receive frequencies between approximately 300 and 320 MHz, low side injection for
receive frequencies between 320 and 340MHz - see also Section 3.4. To be able to
switch between two different frequency channels a divider ratio of either 32 or 32.25 can
be selected via the FSEL-Pin.
Table 2
Dependence of PLL overall division ratio on FSEL
FSEL
Ratio r=(fL0/fQU)
Open
32
GND
32.25
2.4.4
Crystal Oscillator
The calculation of the value of the necessary crystal load capacitance is shown in
Section 3.3, the crystal frequency calculation is explained in Section 3.4.
2.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It
has a typical input impedance of 330 Ω to allow for easy interfacing to a 10.7 MHz
ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator
Preliminary Specification
16
V 1.1, 2004-10-20
TDA 5221
Functional Description
(RSSI) generator which produces a DC voltage that is directly proportional to the input
signal level as can be seen in Figure 4. This signal is used to demodulate ASKmodulated receive signals in the subsequent baseband circuitry. The RSSI output is
applied to the modulation format switch, to the Peak Detector input and to the AGC
circuitry.
In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state as
described in the next chapter.
2.4.6
FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear phase
detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain
is typically 200µV/kHz. The passive loop filter output that is comprised fully on chip is fed
to both the VCO and the modulation format switch described in more detail below. This
signal is representing the demodulated signal with low frequencies applied to the
demodulator demodulated to logic ones and high frequencies demodulated to logic
zeroes. However this is only valid in case the local oscillator is low-side injected to the
mixer which is applicable to receive frequencies above 320MHz. In case of receive
frequencies below 320MHz (e.g.315MHz) high frequencies are demodulated as logical
ones due to a sign inversion in the downconversion mixing process. See also Section
3.4.
The modulation format switch is actually a switchable amplifier with an AC gain of 11 that
is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was
chosen to facilitate detection in the subsequent circuits. The DC gain is 1 in order not to
saturate the subsequent Data Filter wih the DC offset produced by the demodulator in
case of large frequency offsets of the IF signal. The resulting frequency characteristic
and details on the principle of operation of the switch are described in Section 3.6.
Table 3
MSEL Pin Operating States
MSEL
Modulation Format
Open
ASK
Shorted to ground
FSK
The demodulator circuit is switched off in case of reception of ASK signals.
2.4.7
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage
follower and two 100kΩ on-chip resistors. Along with two external capacitors a 2nd order
Preliminary Specification
17
V 1.1, 2004-10-20
TDA 5221
Functional Description
Sallen-Key low pass filter is formed. The selection of the capacitor values is described
in Section 3.2.
2.4.8
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a
maximum receive data rate of up to 100kBaud. The maximum achievable data rate also
depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs
are accessible. The output delivers a digital data signal (CMOS-like levels) for
subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RCterm. In ASK-mode alternatively a scaled value of the voltage at the PDO-output (approx.
87%) can be used as the slicer-threshold as shown in Table 4. The data slicer threshold
generation alternatives are described in more detail in Section 3.5.
Table 4
SSEL Pin Operating States
SSEL
MSEL
Selected Slicing Level (SL)
X
Low
external SL on Pin 20 (RC-term, e.g.)
High
High
external SL on Pin 20 (RC-term, e.g.)
Low
High
87% of PDO-output (approx.)
2.4.9
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the
receive data signal. A capacitor is necessary. The input is connected to the output of the
RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This output
can be used as an indicator for the received signal strength to use in wake-up circuits
and as a reference for the data slicer in ASK mode. Note that the RSSI level is also
output in case of FSK mode.
2.4.10
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the
device. A power down mode is available to switch off all subcircuits which is controlled
by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in
this case is typically 50nA.
Table 5
PDWN Pin Operating States
PDWN
Operating State
Open or tied to ground
Powerdown Mode
Tied to Vs
Receiver On
Preliminary Specification
18
V 1.1, 2004-10-20
TDA 5221
Applications
3
Applications
3.1
Application Circuit
C 18
R4
R5
U t h r e s h o ld
3V O U T
THRES
24
23
R S S I (0 .8 - 2 .8 V )
20kΩ
OTA
VCC
+ 3 .1 V
I lo a d
LN A
G a in c o n t r o l
v o lt a g e
R S S I > U t h re s h o ld : I lo a d = 4 . 2 µ A
R S S I < U t h r e s h o ld : I lo a d = - 1 .5 µ A
4
TAGC
UC
C5
Figure 3
U c : < 2 . 6 V : G a in h ig h
U c : > 2 . 6 V : G a in lo w
U cm a x= V C C - 0 .7 V
U c m in = 1 . 6 7 V
LNA Automatic Gain Control Circuity
The LNA automatic gain control circuitry consists of an operational transimpedance
amplifier that is used to compare the received signal strength signal (RSSI) generated
by the Limiter with an externally provided threshold voltage Uthres. As shown in the
following figure the threshold voltage can have any value between approximately 0.8 and
2.8V to provide a switching point within the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be
generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the internal
bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher
than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the
TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do
not have the same values in order to achieve a fast-attack and slow-release action of the
Preliminary Specification
19
V 1.1, 2004-10-20
TDA 5221
Applications
AGC and are used to charge an external capacitor which finally generates the LNA gain
control voltage.
LNA always
in high gain mode
3
2
RSSI Level Range
UTHRES Voltage Range
2.5
RSSI Level
1.5
1
LNA always
in low gain mode
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
Figure 4
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The
determination of the optimum point is described in the accompanying Application Note,
a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the
output of the 3VOUT pin is capable of driving up to 50µA, but that the THRES pin input
current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly
related to the receiver power consumption, the power divider resistors should have high
impedance values. The sum of R1 and R2 has to be 600kΩ in order to yield 3V at the
3VOUT pin. R1 can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT
output current of 5µA1) and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to be
accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain
mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as
a short to the 3VOLT pin. In order to achieve low gain mode operation THRES has to be
connected to GND.
As stated above the capacitor connected to the TAGC pin is generating the gain control
voltage of the LNA due to the charging and discharging currents of the OTA and thus is
also responsible for the AGC time constant. As the charging and discharging currents
are not equal two different time constants will result. The time constant corresponding to
the charging process of the capacitor shall be chosen according to the data rate.
According to measurements performed at Infineon the capacitor value should be greater
than 47nF.
1)
note the 20kΩ resistor in series with the 3.1V internal voltage source
Preliminary Specification
20
V 1.1, 2004-10-20
TDA 5221
Applications
3.2
Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a 2nd order
Sallen-Key low pass data filter can be constructed by adding 2 external capacitors
between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following
figure and described in the following formulas1).
C14
C12
FFB
RF1 int
OPP
22
100k
Figure 5
SLP
21
RF2 int
19
100k
Data Filter Design
with RF1int=RF2int=R
C14 =
2Q b
R2πf 3dB
C12 =
b
4QRπf 3dB
with
Q=
b
a
Q is the qualify factor of the poles where, in case of a Bessel filter a=1.3617, b=0.618
and thus Q=0.577
and in case of a Butter worth filter a=1.414, b=1
and thus Q=0.71
Example: Butter worth filter with f3dB=5kHz and R=100kΩ:
C14=450pF, C12=225pF
1)
taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Preliminary Specification
21
V 1.1, 2004-10-20
TDA 5221
Applications
3.3
Crystal Load Capacitance Calculation
The value of the capacitor necessary to achieve that the crystal oscillator is operating at
the intended frequency is determined by the reactive part of the negative resistance of
the oscillator circuit as shown in Section 4.1.3 and by the crystal specifications given by
the crystal manufacturer.
CS
CRST2
Crystal
28
Input
impedance
Z1-28
TDA521X
1
CRST1
Figure 6
Determination of Series Capacitance Vale for the Quartz Oscillator
The required series capacitor for a crystal with specified load capacitance CL can be
calculated as
CS =
1
1
+ 2π f X L
CL
CL is the nominal load capacitance specified by the crystal manufacturer.
Example:
10.18 MHz: CL = 12 pF
XL=870 Ω
CS = 7.2 pF
This value may be obtained by putting two capacitors in series to the crystal, such as
18pF and 12pF in the 10.2MHz case.
But please note that the calculated CS-value includes all parasitic.
3.4
Crystal Frequency Calculation
As described in Section 2.4.3 the operating range of the on-chip VCO is wide enough to
guarantee a receive frequency range between 300 and 340MHz. The VCO signal is
divided by 2 before applied to the mixer . This local oscillator signal can be used to
downconvert the RF signals both with high- or low-side injection at the mixer. High-side
Preliminary Specification
22
V 1.1, 2004-10-20
TDA 5221
Applications
injection of the local oscillator has to be used for receive frequencies between 300 and
320 MHz. In this case the local oscillator frequency is calculated by adding the IF
frequency (10.7 MHz) to the RF frequency. In this case the higher frequency of a FSKmodulated signal is demodulated as a logical one (high).
Low-side injection has to be used for receive frequencies between 320 and 340 MHz.
The local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz)
from the RF frequency then. Please note that in this case sign-inversion occurs and the
higher frequency of a FSK-modulated signal is demodulated as a logical zero (low). The
overall division ratios in the PLL are 32 or 32.25 depending on whether the FSEL-pin is
left open or tied to ground.
Therefore the crystal frequency may be calculated by using the following formula:
f QU =
with
f RF ± 10.7
r
ƒRF receive frequency
ƒLO local oscillator (PLL) frequency (ƒRF ± 10.7)
ƒQU quartz crystal oscillator frequency
r ratio of local oscillator (PLL) frequency and crystal frequency as
shown in the subsequent table
Table 6
Dependence of PLL Overall Division Ratio on FSEL
FSEL
Ratio r=(fLO/fQU)
open
32
GND
32.25
This yields the following examples:
FSEL is „Low“:
f QU =
318 . 55 MHz + 10 .7 MHz
= 10 .209375 MHz
32 . 25
FSEL is „High“:
f QU =
3.5
316 MHz + 10 . 7 MHz
= 10 . 209375 MHz
32
Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C integrator as
shown in Figure 7.
Preliminary Specification
23
V 1.1, 2004-10-20
TDA 5221
Applications
The time constant TA of this circuit including also the internal resistors RF3int and RF4int
(see Figure 9) has to be significantly larger than the longest period of no signal change
TL within the data sequence.
In order to keep distortion low, the minimum value for R is 20kΩ.
TA has to be calculated as
TA =
R1⋅ ( RF 3int + RF 4 int )
R1 + RF 3int + RF 4 int
⋅ C13
= R1II ( RF 3 int + RF 4 int ) ⋅ C13
⋅ C13
=
... for ASK
and
TA =
R1⋅ RF 4 int
R1 + RF 3 int + RF 4 int
R1II ( RF 3int + RF 4 int )
v
⋅ C13
... for FSK
R1, RF3 int, RF4 int and C13 see also Figure 7 and .Figure 9
19
20
Uthreshold
25
CM
data
filter
data slicer
Figure 7
Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use the peak
detector in connection with an internal resistive divider and one capacitor as shown in
the following Figure 8. For selecting the peak detector as reference for the slicing level
a logic low as to be applied on the SSEL pin.
In case of MSEL is high (or open), which means that ASK-Mode is selected, a logic low
on the SSEL pin yields a logic high on the AND-output and thus the peak-detector is
selected (see Figure 9).
In case of FSK the MSEL-pin and furthermore the one input of the AND-gate is low, so
the peak detector can not be selected.
The capacitor value is depending on the coding scheme and the protocol used.
Preliminary Specification
24
V 1.1, 2004-10-20
TDA 5221
Applications
C
Pins:
26
25
peak detector
56k
390k
data slicer
Uthreshold
CP
Figure 8
3.6
Data Slicer Threshold Generation Utilising the Peak Detector
ASK/FSK-Data Path Functional Description
The TDA5221 is containing an ASK/FSK switch which can be controlled via Pin 15
(MSEL). This switch is actually consisting of 2 operational amplifiers that are having a
gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in
order to achieve an appropriate demodulation gain characteristic. In order to
compensate for the DC-offset generated especially in case of the FSK PLL demodulator
there is a feedback connection between the threshold voltage of the bit slicer comparator
(Pin 20) to the negative input of the FSK switch amplifier.
In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87% of the
peak-detector output-voltage at Pin 26 (PDO) can be used as the slicer-reference level.
The slicing reference level is generated by an internal voltage divider (RT1int, RT2int),
which is applied on the peak detector output.
The selection between these modes is controlled by Pin 16 (SSEL), as described in
Section 3.5.
This is shown in the following Figure 9.
Preliminary Specification
25
V 1.1, 2004-10-20
TDA 5221
Applications
MSEL
15
H=ASK
L=FSK
PDO
PEAK
DETECTOR
from RSSI Gen
(ASK signal)
26
RT1 int
ASK/FSK Switch
56k
C15
100nF
RT2
390k
Data Filter
+
ASK
+FSK
RF3 int
FSK PLL Demodulator
AC
0.18 mV/kHz
v=1
100k
+ CM
H=CP
L=CM
100k
25
DATA Out
300k
DC
1
RF4 int
typ. 2 V
1.5 V......2.5 V
Comp
+ CP
RF2 int
RF1 int
30k
ASK mode: v=1
FSK mode: v=11
22
21
FFB
19
OOP
C14
20
SLP
16
SLN
SSEL
R1
C12
C13
Figure 9
3.7
ASK/FSK mode datapath
FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown above
(highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by
the external RC-combination. The upper cutoff frequency f3 is determined by the data
filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 200µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic
gain of this circuit is 2.2mV/kHz within the bandpass. The gain for the DC content of FSK
signal remains at 200µV/kHz. The cut-off frequencies of the bandpass have to be chosen
such that the spectrum of the data signal is influenced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the effect of the
drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at
the negative input of the slicer comparator (Pin20) is used. The comparator has no
hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises the
voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain benefit of this
Preliminary Specification
26
V 1.1, 2004-10-20
TDA 5221
Applications
asymmetrical offset for the demodulation of long zeros the lower of the two FSK
frequencies should be chosen in the transmitter as the zero-symbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v
v-3dB
20dB/dec
-40dB/dec
3dB
0dB
f
DC
f1
f2
0.18mV/kHz
Figure 10
f3
2mV/kHz
Frequency characteristic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f1 =
1
R1× 330kΩ
2π
× C13
R1 + 330kΩ
f 2 = v × f1 = 11× f1
f 3 = f 3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 3.2.
Example:
R1 = 100kΩ, C13 = 47nF
This leads tof1 = 44Hz and f2 = 485Hz
Preliminary Specification
27
V 1.1, 2004-10-20
TDA 5221
Applications
3.8
ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is
dominated by the data filter alone, thus it is lowpass shaped.The cutoff frequency is
determined by the external capacitors C12 and C14 and the internal 100k resistors as
described in Section 3.2
0dB
-3dB
-40dB/dec
f
f3dB
Figure 11
3.9
Frequency characteristic in case of ASK mode
Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network as
described in Section 3.5 it is necessary to use large values for the capacitor C attached
to the SLN pin (pin 20) in order to achieve long time constants. This results also from the
fact that the choice of the value for R1 connected between the SLP and SLN pins (pins
19 and 20) is limited by the 330kΩ resistor appearing in parallel to R1 as can be seen in
Figure 9. Apart from this a resistor value of 100kΩ leads to a voltage offset of 1mv at the
comparator input. The resulting startup time constant τ1 can be calculated with:
τ1 = (R1 || 330kΩ) × C13
In case R1 is chosen to be 100kΩ and C13 is chosen as 47nF this leads to
τ 1 = (100kΩ || 330kΩ ) × 47nF = 77kΩ × 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary for the
device to be able to demodulate data properly. In the powerdown mode the capacitor is
only discharged by leakage currents.
Preliminary Specification
28
V 1.1, 2004-10-20
TDA 5221
Applications
In order to reduce the turn-on time in the presence of large values of C a precharge
circuit was included in the TDA5221 as shown in the following figure.
C18
R4+R5=600k
R5
R4
C13
R1
Uthreshold
24
23
Uc>Us
20
Uc<Us
Iload
19
Uc
Data Filter
ASK/FSK Switch
-
U2
0 / 240uA
+
Us
OTA
+
-
U2<2.4V : I=240uA
U2>2.4V : I=0
20k
+3.1V
Figure 12
+2.4V
Principle of the precharge circuit
This circuit charges the capacitor C13 with an inrush current Iload of typically 220µA for a
duration of T2 until the voltage Uc appearing on the capacitor is equal to the voltage Us
at the input of the data filter. This voltage is limited to 2.5V. As soon as these voltages
are equal or the duration T2 is exceeded the precharge circuit is disabled.
τ2 is the time constant of the charging process of C18 which can be calculated as
τ 2 ≈ 20kΩ × C 2
as the sum of R4 and R5 is sufficiently large and thus can be neglected. T2 can then be
calculated according to the following formula:


1
T2 = τ 2 ln
2
 1 − .4V

3V

Preliminary Specification
29


 ≈ τ 2 × 1.6



V 1.1, 2004-10-20
TDA 5221
Applications
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V
2.4V
T2
2
Figure 13
Voltage appearing on C18 during precharging process
The voltage appearing on the capacitor C13 connected to pin 20 is shown in the following
figure. It can be seen that due to the fact that it is charged by a constant current source
it exhibits is a linear increase in voltage which is limited to USmax = 2.5V which is also the
approximate operating point of the data filter input. The time constant appearing in this
case can be denoted as T3, which can be calculated with:
T3 =
Preliminary Specification
US max × C13 2.5V
=
× C13
220µA
220µA
30
V 1.1, 2004-10-20
TDA 5221
Applications
Uc
Us
T3
Figure 14
Voltage transient on capacitor C13 attached to pin 20
As an example the choice of C18 = 22nF and C13 = 47nF yields
τ2 = 0.44ms
T2 = 0.71ms
T3 = 0.53ms
This means that in this case the inrush current could flow for a duration of 0.64ms but
stops already after 0.49ms when the USmax limit has been reached. T3 should always be
chosen to be shorter than T2.
It has to be noted finally that during the turn-on duration T2 the overall device power
consumption is increased by the 220µA needed to charge C13.
The precharge circuit may be disabled if C18 is not equipped. This yields a T2 close to
zero. Note that the sum of R4 and R5 has to be 600kΩ in order to produce 3V at the
THRES pin as this voltage is internally used also as the reference for the FSK
demodulator.
Preliminary Specification
31
V 1.1, 2004-10-20
TDA 5221
Reference
4
Reference
4.1
Electrical Data
4.1.1
Absolute Maximum Ratings
Attention: The maximum ratings may not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
may result. The AC/DC characteristic limits are not guaranteed.
Table 7
Absolute Maximum Ratings, Tamb = -40 °C … +105 °C
Parameter
#
Symbol
Limit Values
min.
Unit Remarks
max.
1
Supply Voltage
Vs
-0.3
5.5
V
2
Junction Temperature
Tj
-40
+125
°C
3
Storage Temperature
Ts
-40
+150
°C
4
Thermal Resistance
RthJA
114
K/W
5
ESD integrity, all pins
excl. Pins 1,3, 6, 28
ESD integrity Pins
1,3,6,28
VESD
+2
kV
+1.5
kV
4.1.2
HBM according to
MIL STD 883D,
method 3015.7
Operating Range
Within the operational range the IC operates as explained in the circuit description.
Currents flowing into the device are denoted as positive currents and vice versa. The
device parameters marked with ■ are not part of the production test, but either verified
by design or measured in the Infineon Evalboard as described in Section 4.2.
Supply voltage: VCC = 4.5V .. 5.5V
Table 8
#
Operating Range, Tamb = -40 °C … +105 °C
Parameter
Symbol
Limit Values Unit
min.
max.
ISF
ISA
4.1
3.5
8.1
7.3
mA
mA
1
Supply Current
2
Receiver Input Level
ASK
FSK, frequ. dev. ± 50kHz
RFin
-110
-102
-13
-13
dBm
dBm
LNI Input Frequency
fRF
300
340
MHz
3
Preliminary Specification
Test Conditions/
Notes
L
■
32
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values Unit
min.
max.
4
MI/X Input Frequency
fMI
300
340
MHz
5
3dB IF Frequency Range
ASK
FSK
fIF -3dB
5
10.4
23
11
MHz
V
Test Conditions/
Notes
L
■
6
Powerdown Mode On
PWDNON
2
VS
7
Powerdown Mode Off
PWDNOFF 0
0.8
V
8
Gain Control Voltage,
LNA high gain state
VTHRES
2.8
VS
V
9
Gain Control Voltage,
LNA low gain state
VTHRES
0
0.7
V
■ Not part of the production test - either verified by design or measured in an Infineon Evalboard
described in Section 4.2.
4.1.3
AC/DC Characteristics at TAMB = 25°C
AC/DC characteristics involve the spread of values guaranteed within the specified
voltage and ambient temperature range. Typical characteristics are the median of the
production. Currents flowing into the device are denoted as po-sitive currents and vice
versa. The device performance parameters marked with ■ are not part of the production
test, but either verified by design or measured in the Infineon Evalboard as described in
Section 4.2.
Table 9
#
AC/DC Characteristics with TA 25°C, VVCC=4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min.
Unit
Test Conditions/ L
Notes
typ.
max.
50
100
nA
Pin 27 (PDWN)
open or tied to 0 V
SUPPLY
Supply Current
1
Supply current,
standby mode
IS PDWN
2
Supply current,
device operating in
FSK mode
ISF
5.1
6.2
7.1
mA
Pin 11 (FSEL) open,
Pin 15 (MSEL) tied
to GND
3
Supply current,
device operating in
ASK mode
ISA
4.5
5.5
6.3
mA
Pin 11 (FSEL) open,
Pin 15 (MSEL) open
Preliminary Specification
33
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Conditions/ L
Notes
max.
LNA
Signal Input LNI (PIN 3), VTHRES>2.8V, high gain mode
■
1
Average Power Level
at BER = 2E-3
(Sensitivity)
RFin
-113
dBm
Manchester
encoded datarate
4kBit, 280kHz IF
Bandwidth
2
Average Power Level
at BER = 2E-3
(Sensitivity) FSK
RFin
-105
dBm
Manchester enc.
■
datarate 4kBit,
280kHz IF Bandw., ±
50kHz pk. dev.
3
Input impedance,
fRF = 315 MHz
S11 LNA
4
Input level @ 1dB
C.P.
fRF=315 MHz
P1dBLNA
-14
dBm
5
Input 3rd order
intercept point fRF =
315 MHz
IIP3LNA
-10
dBm
6
LO signal feedthrough LOLNI
at antenna port
-119
dBm
■
0.895 / -25.5 deg
■
fin = 315 & 317MHz
■
■
Signal Output LNO (PIN 6), VTHRES>2.8V, high gain mode
1
Gain fRF = 315 MHz
S21 LNA
1.577 / 150.3 deg
■
2
Output impedance,
fRF = 315 MHz
S22 LNA
0.897 / -10.3 deg
■
3
Voltage Gain Antenna
to MI fRF = 315 MHz
GAntMI
21
dB
4
Noise Figure
NFLNA
2
dB
■
excluding matching
network loss - see
Appendix
■
Signal Input LNI, VTHRES=GND, lwo gain mode
1
Input impedance,
fRF = 315 MHz
S11 LNA
2
Input level @ 1dB C.
P. fRF = 315 MHz
P1dBLNA
Preliminary Specification
■
0.918 / -25.2 deg
-7
34
dBm
matched input
■
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
3
Input 3rd order
intercept point fRF =
315 MHz
IIP3LNA
typ.
Unit
Test Conditions/ L
Notes
dBm
fin = 315 & 317MHz
max.
-13
■
Signal Output LNO, VTHRES=GND, lwo gain mode
1
Gain fRF = 315 MHz
S21 LNA
0.193 / 153.7 deg
■
2
Output impedance,
fRF = 315 MHz
S22 LNA
0.907 / -10.5 deg
■
3
Voltage Gain Antenna GAntMI
to MI fRF = 315 MHz
2
■
dB
Signal 3VOUT (PIN 24)
1
Output voltage
V3VOUT
2.9
3.1
3.3
V
3VOUT Pin open
2
Current out
I3VOUT
-3
-5
-10
µA
see Section 4.1
VTHRES
0
VS-1
V
see Section 4.1
VS-1
V
Signal THRES (PIN 23)
1
Input Voltage range
2
LNA low gain mode
VTHRES
0
3
LNA high gain mode
VTHRES
3
4
Current in
ITHRES_in
V
5
or shorted to Pin 24
■
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-3.6
-4.2
-5.5
µA
RSSI > VTHRES
2
Current in,
LNA high gain state
ITAGC_in
1
1.6
2.2
µA
RSSI < VTHRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1
Input impedance,
fRF = 315 MHz
S11 MIX
2
Input 3rd order
intercept point
IIP3MIX
■
0.954 / -10.9 deg
-25
dBm
■
Signal Output IFO (PIN 12)
1
Output impedance
ZIFO
330
Ω
■
2
Conversion Voltage
Gain fRF = 315 MHz
GMIX
21
dB
■
3
Noise Figure, SSB
(~DSB NF+3dB)
NFMIX
13
dB
■
Preliminary Specification
35
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
4
RF to IF isolation
typ.
46
ARF-IF
Unit
max.
Test Conditions/ L
Notes
dB
■
Ω
■
LIMITER
Signal Input LIM/X (PINS 17/18)
1
Input Impedance
ZLIM
264
330
2
RSSI dynamic range
DRRSSI
70
3
RSSI linearity
LINRSSI
±1
4
Operating frequency
(3dB points)
fLIM
5
10.7
396
dB
dB
■
23
MHz
■
100
kHz
■
DATA FILTER
1
Useable bandwidth
BWBB
FILT
2
RSSI Level at Data
Filter Output SLP,
RFIN=-103dBm
RSSIlow
1.1
V
LNA in high gain
mode
3
RSSI Level at Data
Filter Output SLP,
RFIN=-30dBm
RSSIhigh
2.65
V
LNA in high gain
mode
100
kBps
NRZ, 20pF
capacitive loading
0.1
V
VS-1
V S0.7
V
output
current=200µA
-220
-300
µA
see Section 3.9
SLICER
Signal Output DATA (PIN 25)
1
Maximum Datarate
DRmax
2
LOW output voltage
VSLIC_L
0
3
HIGH output voltage
VSLIC_H
VS1.3
■
Slicer, SLN (PIN 20)
1
Precharge Current
Out
IPCH_SLN -100
PEAK DETECTOR
Signal Output PDO (PIN 26)
Preliminary Specification
36
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
1
Load current
Iload
-500
2
Internal resistive load
R
357
typ.
446
Unit
Test Conditions/ L
Notes
µA
static load current
must not exceed 500µA
max.
535
kΩ
11
MHz
CRYSTAL OSCILLATOR
Signals CRSTL 1, CRSTL 2 (PINS 1/28)
5
fundamental mode,
series resonance
1
Operating frequency
fCRSTL
2
Input Impedance
@ ~10MHz
Z1-28
-700 +
j 865
Ω
■
3
Serial Capacity
@ ~10MHz
CS10=C1
7.2
pF
■
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
ASK Mode
VMSEL
1.4
2
3
FSK Mode
VMSEL
0
Input Bias Current
MSEL
IMSEL
-11
GFMDEM
200
4
V
or open
0.2
V
or tied to ground
-19
µA
MSEL tied to GND
FSK DEMODULATOR
1
Demodulation Gain
2
Useable IF Bandwidth BWIFPLL
10.2
10.7
µV/k
Hz
11.2
MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1
Powerdown Mode On PWDNON 2.8
VS
V
2
Powerdown Mode Off PWDNOff 0
Input bias current
IPDWN
PDWN
0.8
V
3
Preliminary Specification
19
37
µA
Power On Mode
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
4
Start-up Time until
valid IF signal is
detected
TSU
typ.
Unit
Test Conditions/ L
Notes
ms
depends on the
used crystal
max.
1
■
PLL DIVIDER
Signal FSEL (PIN 11)
1
Overal divison ratio
32
VFSEL
1.4
4
V
or open
2
Overal division ratio
32.25
VFSEL
0
0.2
V
or tied to GND
3
Input bias current
FSEL
IFSEL
-19
µA
FSEL tied to GND
or open
-11
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1
Slicer-Reference is
voltage at Pin 20
(SLN)
VSSEL
1.4
4
V
2
Slicer-Reference is
approx. 87% of the
voltage at Pin 26
(PDO)
VSSEL
0
0.2
V
3
Input bias current
SSEL
ISSEL
-19
µA
-11
SSEL tied to GND
■ Not part of the production test - either verified by design or measured in the Infineon
Evalboard as described in Section 4.2.
Preliminary Specification
38
V 1.1, 2004-10-20
TDA 5221
Reference
4.1.4
AC/DC Characteristics at TAMB= -40 to 105°C
Currents flowing into the device are denoted as positive currents and vice versa.
Table 10
#
AC/DC Characteristics with TAMB = -40°C ...+105°C, VVCC=4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions/
Notes
max.
50
400
nA
Pin 27 (PDWN) open
or tied to 0 V
L
SUPPLY
Supply Current
1
Supply current,
standby mode
IS PDWN
2
Supply current,
device operating in
FSK mode
ISF
4.1
6.2
8.1
mA
Pin 11 (FSEL) open,
Pin 15 (MSEL) tied to
GND
3
Supply current,
device operating in
ASK mode
ISA
3.5
5.5
7.3
mA
Pin 11 (FSEL) open,
Pin 15 (MSEL) open
Signal Input 3VOUT (PIN 24)
1
Output voltage
V3VOUT
2.9
3.1
3.3
V
3VOUT Pin open
2
Current out
I3VOUT
-3
-5
-10
µA
see Section 4.1
VTHRES
0
VS-1
V
see Section 4.1
Signal THRES (PIN 23)
1
Input Voltage range
2
LNA low gain mode
VTHRES
0
3
LNA high gain mode
VTHRES
3
4
Current in
ITHRES_in
V
VS-1
5
V
or shorted to Pin 24
■
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-1
-4.2
-8
µA
RSSI > VTHRES
2
Current in, LNA high
gain state
VTAGC_in
0.5
1.5
5
µA
RSSI < VTHRES
MIXER
1
Conversion Voltage
Gain fRF = 315 MHz
GMIX
+19
dB
LIMITER
Preliminary Specification
39
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Conditions/
Notes
L
Signal Input LIM/X (PINS 17/18)
1
RSSI dynamic range
DRRSSI
70
dB
2
RSSI Level at Data
Filter Output SLP,
RFIN= -103dBm
RSSIlow
1.1
V
LNA in high gain mode
3
RSSI Level at Data
Filter Output SLP,
RFIN= -30dBm
RSSIhigh
2.65
V
LNA in high gain mode
DATA FILTER
Slicer, Signal Output DATA (PIN 25)
1
Maximum Datarate
DRmax
2
LOW output voltage
VSLIC_L
0
3
HIGH output voltage
VSLIC_H
VS1.5
-100
100
kBps NRZ, 20pF capacitive
loading
0.1
V
VS-1
VS0.5
V
output current=200µA
-220
-300
µA
see Section 3.9
µA
static load current must
not exceed -500µA
■
Slicer, Negative Input (PIN 20)
1
Precharge Current
Out
IPCH_SLN
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
Load current
Iload
2
Internal resistive load R
-400
356
446
575
kΩ
CRYSTAL OSCILLATOR
Signals CRSTL 1, CRSTL 2 (PINS 1/28)
1
Operating frequency
fCRSTL
5
11
VMSEL
1.4
4
MHz fundamental mode,
series resonance
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
ASK Mode
Preliminary Specification
40
V
or open
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
2
FSK Mode
VMSEL
3
Input bias current
MSEL
IMSEL
typ.
max.
0
-11
Unit Test Conditions/
Notes
0.2
V
-20
µA
L
MSEL tied to GND
FSK DEMODULATOR
1
Demodulation Gain
GFMDEM
2
Useable IF
Bandwidth
BWIFPLL
200
10.4
10.7
µV/k
Hz
11
MHz
VS
V
POWER DOWN MODE
Signal PDWN (PIN 27)
1
2
3
Powerdown Mode On PWDNON 2.8
Powerdown Mode Off PWDNOff 0
Start-up Time until
valid signal is
detected at IF
TSU
0.8
1
V
ms
depends on the used
crystal
■
PLL DIVIDER
Signal FSEL (PIN 11)
1
Overal divison ratio
32
VFSEL
1.4
4
V
or open
2
Overal division ratio
32.25
VFSEL
0
0.2
V
or tied to GND
3
Input bias current
FSEL
IFSEL
-20
µA
FSEL tied to GND
4
V
or open
-11
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1
Slicer-Reference is
voltage at Pin 20
(SLN)
Preliminary Specification
VSSEL
1.4
41
V 1.1, 2004-10-20
TDA 5221
Reference
#
Parameter
Symbol
Limit Values
min.
2
Slicer-Reference is
approx. 87% of the
voltage at Pin 26
(PDO)
VSSEL
3
Input bias current
SSEL
ISSEL
typ.
0
-11
max.
Unit Test Conditions/
Notes
0.2
V
-20
µA
L
SSEL tied to GND
■ Not part of the production test - either verified by design or measured in the Infineon
Evalboard as described in Section 4.2.
4.2
Test Circuit
The device performance parameters marked with ■ in Section 4.1 were either verified
by design or measured on an Infineon evaluation board. This evaluation board can be
obtained together with evaluation boards of the accompanying transmitter device
TDK5110 in an evaluation kit that may be ordered on the INFINEON Webpage
www.infineon.com/Products More information on the kit is available on request.
Figure 15
Schematic of the Evaluation Board
Preliminary Specification
42
V 1.1, 2004-10-20
TDA 5221
Reference
4.3
Test Board Layouts
Figure 16
Top Side of the Evaluation Board
Figure 17
Bottom Side of the Evaluation Board
Preliminary Specification
43
V 1.1, 2004-10-20
TDA 5221
Reference
Figure 18
4.4
Component Placement on the Evaluation Board
Bill of Materials
The following components are necessary for evaluation of the TDA5221.
Table 11
Bill of Materials (cont’d)
Ref.
Value
Specification 315MHz
C1
3.3pF
0805, COG, +/-0.1pF
C2
10pF
0805, COG, +/-0.1pF
C3
6.8pF
0805, COG, +/-0.1pF
C4
100pF
0805, COG, +/-5%
C5
47nF
1206, X7R, +/-10%
C6
15nH
Toko, PTL2012-F15N0G
C7
100pF
0805, COG, +/-5%
C8
33pF
0805, COG, +/-5%
C9
100pF
0805, COG, +/-5%
C10
10nF
0805, X7R, +/-10%
C11
10nF
0805, X7R, +/-10%
C12
220pF
0805, COG, +/-5%
Preliminary Specification
44
V 1.1, 2004-10-20
TDA 5221
Reference
Ref.
Value
Specification 315MHz
C13
47nF
0805, X7R, +/-10%
C14
470pF
0805, COG, +/-5%
C15
47nF
0805, COG, +/-5%
C16
12pF
0805, COG, +/-1%
C17
22pF
0805, COG, +/-1%
C18
22nF
0805, X7R, +/-5%
C21
100nF
1206, X7R, +/-10%
IC1
TDA5221
Infineon
L1
15nH
Toko, PTL2012-F15N0G
L2
12pF
0805, COG, +/-1%
Q1
10,209375 MHz
1053-925
Q2
SFE_10.7MA5-A
Murata
R1
100kΩ
0805, +/-5%
R4
240kΩ
0805, +/-5%
R5
360kΩ
0805, +/-5%
R6
10kΩ
0805, +/-5%
S1
STL_2POL
2-pole pin connector
S2
SOL_JUMP
SOL_JUMP
S3
SOL_JUMP
SOL_JUMP
S6
SOL_JUMP
SOL_JUMP
X1
STL_2POL
2-pole pin connector
X2
A107-900A (1.6mm gold plated)
INPUT OUTPUT ENTERPRISE CORP
X3
A107-900A (1.6mm gold plated)
INPUT OUTPUT ENTERPRISE CORP
Please note that a capacitor has to be soldered in place L2 and an inductor in place C6.
Preliminary Specification
45
V 1.1, 2004-10-20
TDA 5221
Package Outlines
5
Package Outlines
P_TSSOP_28.eps
Figure 19
<Dev_Package1>
Table 12
Order Information
Type
TDA 5221
Ordering Code
Package
Q67100-H2051
<Dev_Package1>
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Preliminary Specification
46
V 1.1, 2004-10-20
TDA 5221
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Page
Pin Defintion and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Dependence of PLL overall division ratio on FSEL . . . . . . . . . . . . . . . 16
MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Dependence of PLL Overall Division Ratio on FSEL . . . . . . . . . . . . . . 23
Absolute Maximum Ratings, Tamb = -40 °C … +105 °C . . . . . . . . . . . . 32
Operating Range, Tamb = -40 °C … +105 °C . . . . . . . . . . . . . . . . . . . . 32
AC/DC Characteristics with TA 25°C, VVCC=4.5 ... 5.5 V / . . . . . . . . . . 33
AC/DC Characteristics with TAMB = -40°C ...+105°C, VVCC=5.5V . . . . 39
Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Order Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Preliminary Specification
47
V 1.1, 2004-10-20
TDA 5221
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Page
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LNA Automatic Gain Control Circuity . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . 20
Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Determination of Series Capacitance Vale for the Quartz Oscillator . . 22
Data Slicer Threshold Generation with External R-C Integrator . . . . . 24
Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . 25
ASK/FSK mode datapath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Frequency characteristic in case of FSK mode . . . . . . . . . . . . . . . . . . 27
Frequency characteristic in case of ASK mode . . . . . . . . . . . . . . . . . . 28
Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Voltage appearing on C18 during precharging process. . . . . . . . . . . . 30
Voltage transient on capacitor C13 attached to pin 20 . . . . . . . . . . . . 31
Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . 44
P-TSSOP-28-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Preliminary Specification
48
V 1.1, 2004-10-20
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG