Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) ISL23428 Features The ISL23428 is a volatile, low voltage, low noise, low power, 128-tap, dual digitally controlled potentiometer (DCP) with an SPI Bus™ interface. It integrates two DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. • Two potentiometers per package Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (64 tap position). The low voltage, low power consumption, and small package of the ISL23428 make it an ideal choice for use in battery operated equipment. In addition, the ISL23428 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23428 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Applications • 128 resistor taps • 10k 50kor 100k total resistance • SPI serial interface - No additional level translator for low bus supply - Daisy Chaining of multiple DCPs • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V SPI bus/logic power supply • Maximum supply current without serial bus activity (standby) - 4µA @ VCC and VLOGIC = 5V - 1.7µA @ VCC and VLOGIC = 1.7V • Shutdown Mode - Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally - Reduces power consumption by disconnecting the DCP resistor from the circuit • Wiper resistance: 70 typical @ VCC = 3.3V • Power-on preset to mid-scale (64 tap position) • Extended industrial temperature range: -40°C to +125°C • Power supply margining • 14 Ld TSSOP or 16 Ld UTQFN packages • Trimming sensor circuits • Pb-free (RoHS compliant) • Gain adjustment in battery powered instruments • RF power amplifier bias compensation 10000 VREF RESISTANCE (Ω) 8000 6000 RH - 4000 RW ISL23428 2000 0 VREF_M + ISL28114 RL 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP August 25, 2011 FN7904.0 1 FIGURE 2. VREF ADJUSTMENT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners ISL23428 Block Diagram VLOGIC VCC SCK POWER UP INTERFACE, CONTROL AND STATUS LOGIC SDI SDO SPI INTERFACE CS RH0 WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY WR1 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY RW0 GND Pin Configurations RH1 RL0 RW1 RL1 Pin Descriptions ISL23428 (14 LD TSSOP) TOP VIEW GND 1 14 VCC VLOGIC 2 13 RL0 SDO 3 12 RW0 SCK 4 11 RH0 SDI 5 10 RH1 CS 6 9 RW1 GND 7 8 RL1 TSSOP UTQFN SYMBOL DESCRIPTION 1, 7 5, 6, 15 GND 2 16 VLOGIC 3 1 SDO Logic Pin - Serial bus data output (configurable) 4 2 SCK Logic Pin - Serial bus clock input 5 3 SDI Logic Pin - Serial bus data input 6 4 CS Logic Pin - Active low chip select 8 8 RL1 DCP1 “low” terminal 9 9 RW1 DCP1 wiper terminal Ground pin SPI bus/logic supply Range 1.2V to 5.5V TOP VIEW 12 12 RW0 DCP0 wiper terminal 13 13 RL0 DCP0 “low” terminal 14 14 VCC Analog power supply. Range 1.7V to 5.5V 7 NC Not Connected RL0 DCP0 “high” terminal 13 RH0 VCC 11 GND 11 14 DCP1 “high” terminal 15 RH1 VLOGIC 10 16 10 ISL23428 (16 LD UTQFN) RH1 CS 4 9 RW1 8 10 RL1 3 7 SDI 6 RH0 NC RW0 11 GND 12 2 5 1 SCK GND SDO 2 FN7904.0 August 25, 2011 ISL23428 Ordering Information PART NUMBER (Note 4) PART MARKING RESISTANCE OPTION (kΩ) TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL23428TFVZ (Note 2) 23428 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23428TFVZ-T7A (Notes 1, 2) 23428 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23428TFVZ-TK (Notes 1, 2) 23428 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23428UFVZ (Note 2) 23428 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL23428UFVZ-T7A (Notes 1, 2) 23428 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL23428UFVZ-TK (Notes 1, 2) 23428 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 23425WFVZ (Note 2) 23428 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 23425WFVZ-T7A (Notes 1, 2) 23428 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 23425WFVZ-TK (Notes 1, 2) 23428 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23428TFRUZ-T7A (Notes 1, 3) GBR 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23428TFRUZ-TK (Notes 1, 3) GBR 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23428UFRUZ-T7A (Notes 1, 3) GBP 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23428UFRUZ-TK (Notes 1, 3) GBP 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23428WFRUZ-T7A (Notes 1, 3) GBN 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23428WFRUZ-TK (Notes 1, 3) GBN 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL23428. For more information on MSL please see techbrief TB363. 3 FN7904.0 August 25, 2011 ISL23428 Absolute Maximum Ratings Thermal Information Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .4.5kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 14 Ld TSSOP Package (Notes 5, 6) . . . . . . 112 40 16 Ld UTQFN Package (Notes 5, 6) . . . . . . 110 64 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the “case temp” location is the center top of the package. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL RTOTAL PARAMETER RH to RL Resistance TEST CONDITIONS W option RW MAX (Note 19) UNITS kΩ U option 50 kΩ T option 100 kΩ -20 W option ±2 +20 125 % ppm/°C U option 65 ppm/°C T option 45 ppm/°C DCP Terminal Voltage VRH or VRL to GND Wiper Resistance RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V 0 70 VCC = 1.7V CH/CL/CW Terminal Capacitance TYP (Note 7) 10 RH to RL Resistance Tolerance End-to-End Temperature Coefficient VRH, VRL MIN (Note 19) See “DCP Macro Model” on page 9 V Ω 580 Ω 32/32/32 pF ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC Noise Resistor Noise Density Wiper at middle point, W option 16 Wiper at middle point, U option 49 nV/√Hz Wiper at middle point, T option 61 nV/√Hz Feed Thru Digital Feed-through from Bus to Wiper PSRR Power Supply Reject Ratio 4 -0.4 VCC 200 <0.1 0.4 µA nV/√Hz Wiper at middle point -65 dB Wiper output change if VCC change ±10%; wiper at middle point -75 dB FN7904.0 August 25, 2011 ISL23428 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL MIN (Note 19) TYP (Note 7) MAX (Note 19) W option -0.5 ±0.15 +0.5 LSB (Note 8) U, T option -0.5 ±0.15 +0.5 LSB (Note 8) W option -0.5 ±0.15 +0.5 LSB (Note 8) U, T option -0.5 ±0.15 +0.5 LSB (Note 8) -3 -1.5 0 LSB (Note 8) -1.5 -0.9 0 LSB (Note 8) W option 0 1.5 3 LSB (Note 8) U, T option 0 0.9 1.5 LSB (Note 8) DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals -2 ±0.5 2 LSB (Note 8) PARAMETER TEST CONDITIONS UNITS VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 12) DNL (Note 11) FSerror (Note 10) Integral Non-linearity, Guaranteed Monotonic Differential Non-linearity, Guaranteed Monotonic Full-scale Error W option U, T option ZSerror (Note 9) Zero-scale Error Vmatch (Note 21) DCP to DCP Matching TCV (Note 13) Ratiometric Temperature Coefficient tLS_Settling Large Signal Wiper Settling Time fcutoff -3dB Cutoff Frequency W option, Wiper Register set to 40 hex 8 ppm/°C U option, Wiper Register set to 40 hex 4 ppm/°C T option, Wiper Register set to 40 hex 2.3 ppm/°C From code 0 to 7F hex, measured from 0 to 1 LSB settling of the wiper 300 ns 1200 kHz Wiper at middle point W option Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL (Note 17) Integral Non-Linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -1.0 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V Differential Non-Linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -0.5 U, T option; VCC = 1.7V 5 ±0.15 -0.5 ±0.15 +0.5 ±0.15 ±0.4 MI (Note 14) MI (Note 14) +0.5 ±0.4 -0.5 MI (Note 14) MI (Note 14) 1 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V +1.0 4 U, T option; VCC = 1.7V RDNL (Note 16) ±0.5 MI (Note 14) MI (Note 14) +0.5 MI (Note 14) MI (Note 14) FN7904.0 August 25, 2011 ISL23428 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER Roffset (Note 15) Offset, Wiper at 0 Position TEST CONDITIONS MIN (Note 19) TYP (Note 7) MAX (Note 19) 0 1.8 3 W option; VCC = 2.7V to 5.5V W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V MI (Note 14) 3 0 MI (Note 14) 0.3 U, T option; VCC = 1.7V 1 MI (Note 14) 0.5 -2 UNITS ±0.5 MI (Note 14) Rmatch (Note 22) DCP to DCP Matching Any two DCPs at the same tap position with the same terminal voltages 2 LSB (Note 8) TCR (Note 18) Resistance TemperatureCoefficient W option; Wiper register set between 19 hex and 7F hex 170 ppm/°C U option; Wiper register set between 19 hex and 7F hex 80 ppm/°C T option; Wiper register set between 19 hex and 7F hex 50 ppm/°C Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL ILOGIC ICC ILOGIC SB PARAMETER VLOGIC Supply Current (Write/Read) VCC Supply Current (Write/Read) VLOGIC Standby Current MAX (Note 19) UNITS VLOGIC = 5.5V, VCC = 5.5V, fSCK = 5MHz (for SPI active read and write) 1.5 mA VLOGIC = 1.2V, VCC = 1.7V, fSCK = 1MHz (for SPI active read and write) 30 µA VLOGIC = 5.5V, VCC = 5.5V 100 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA VLOGIC = VCC = 5.5V, SPI interface in standby 2 µA 0.5 µA 2 µA 1.2 µA 2 µA 0.5 µA 2 µA 1.2 µA 0.4 µA TEST CONDITIONS MIN (Note 19) TYP (Note 7) VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ILOGIC VLOGIC Shutdown Current SHDN VLOGIC = VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby ILkgDig Leakage Current, at Pins CS, SDO, SDI, SCK Voltage at pin from GND to VLOGIC 6 -0.4 <0.1 FN7904.0 August 25, 2011 ISL23428 Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL tDCP tShdnRec PARAMETER Wiper Response Time DCP Recall Time from Shutdown Mode VCC, VLOGIC VCC ,VLOGIC Ramp Rate (Note 20) Ramp Serial Interface Specification SYMBOL MIN (Note 19) TEST CONDITIONS TYP (Note 7) MAX (Note 19) UNITS W option; CS rising edge to wiper new position, from 10% to 90% of final value. 0.4 µs U option; CS rising edge to wiper new position, from 10% to 90% of final value. 1.5 µs T option; CS rising edge to wiper new position, from 10% to 90% of final value. 3.5 µs CS rising edge to wiper recalled position and RH connection 1.5 µs Ramp monotonic at any level 0.01 50 V/ms For SCK, SDI, SDO, CS Unless Otherwise Noted. PARAMETER TEST CONDITIONS MIN (Note 19) TYP (Note 7) MAX (Note 19) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC+ 0.3 V Hysteresis VOL SDI and SCK Input Buffer Hysteresis SDO Output Buffer LOW Voltage VLOGIC > 2V 0.05 x VLOGIC V VLOGIC < 2V 0.1 x VLOGIC V IOL = 3mA, VLOGIC > 2V 0 IOL = 1.5mA, VLOGIC < 2V Rpu SDO Pull-Up Resistor Off-Chip Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 0.4 V 0.2 x VLOGIC V 1.5 kΩ 5 MHz 1 MHz Cpin SCK, SDO, SDI, CS Pin Capacitance fSCK SCK Frequency VLOGIC = 1.7V to 5.5V 10 tCYC SPI Clock Cycle Time VLOGIC ≥ 1.7V 200 ns tWH SPI Clock High Time VLOGIC ≥ 1.7V 100 ns tWL SPI Clock Low Time VLOGIC ≥ 1.7V 100 ns tLEAD Lead Time VLOGIC ≥ 1.7V 250 ns tLAG Lag Time VLOGIC ≥ 1.7V 250 ns tSU SDI, SCK and CS Input Setup Time VLOGIC ≥ 1.7V 50 ns tH SDI, SCK and CS Input Hold Time VLOGIC ≥ 1.7V 50 ns tRI SDI, SCK and CS Input Rise Time VLOGIC ≥ 1.7V 10 tFI SDI, SCK and CS Input Fall Time VLOGIC ≥ 1.7V 10 20 ns 100 ns VLOGIC = 1.2V to 1.6V pF ns tDIS SDO Output Disable Time VLOGIC ≥ 1.7V 0 tSO SDO Output Setup Time VLOGIC ≥ 1.7V 50 ns tV SDO Output Valid Time VLOGIC ≥ 1.7V 150 ns tHO SDO Output Hold Time VLOGIC ≥ 1.7V 0 ns 7 FN7904.0 August 25, 2011 ISL23428 Serial Interface Specification SYMBOL For SCK, SDI, SDO, CS Unless Otherwise Noted. (Continued) PARAMETER TEST CONDITIONS MIN (Note 19) TYP (Note 7) MAX (Note 19) UNITS tRO SDO Output Rise Time Rpu = 1.5k, Cbus = 30pF 60 ns tFO SDO Output Fall Time Rpu = 1.5k, Cbus = 30pF 60 ns tCS CS Deselect Time 2 µs NOTES: 7. Typical values are for TA = +25°C and 3.3V supply voltages. 8. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 9. ZS error = V(RW)0/LSB. 10. FS error = [V(RW)127 – VCC]/LSB. 11. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 12. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 Max V RW i – Min V RW i 10 6 13. TC = ----------------------------------------------------------------------------- --------------------- for i = 8 to 127decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage V V RW i +25°C +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 14. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 15. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 16. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 17. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 18. 6 Max Ri – Min Ri 10 TC R = ------------------------------------------------------- --------------------Ri +25°C +165°C for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the minimum value of the resistance over the temperature range. 19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 20. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible it is recommended to ramp-up the VLOGIC first followed by the VCC. 21. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 22. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 8 FN7904.0 August 25, 2011 ISL23428 DCP Macro Model RTOTAL RH CL CH CW 32pF RL 32pF 32pF RW Timing Diagrams Input Timing tCS CS tCYC tLEAD SCK tSU tH tLAG ... tWH tWL ... MSB SDI tRI tFI LSB SDO Output Timing CS SCK ... tSO tHO tDIS ... MSB SDO LSB tV SDI ADDR XDCP™ Timing (for All Load Instructions) CS tDCP SCK SDI ... ... MSB LSB VW SDO *When CS is HIGH SDO at Z or Hi-Z state 9 FN7904.0 August 25, 2011 ISL23428 0.20 0.04 0.10 0.02 DNL (LSB) DNL (LSB) Typical Performance Curves 0.00 -0.10 0.00 -0.02 -0.20 0 32 64 96 -0.04 128 0 32 64 0.12 0.15 0.09 INL (LSB) INL (LSB) 0.30 0.00 0.06 0.03 -0.15 0 32 64 96 0.00 128 0 TAP POSITION (DECIMAL) 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C 0.20 0.04 0.10 0.02 RDNL (MI) RDNL (MI) 128 FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C -0.30 96 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) 0.00 -0.10 0.00 -0.02 -0.20 -0.04 0 32 64 96 TAP POSITION (DECIMAL) FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C 10 128 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FN7904.0 August 25, 2011 ISL23428 (Continued) 0.30 0.08 0.15 0.04 RINL (MI) RINL (MI) Typical Performance Curves 0.00 -0.15 -0.30 0.00 -0.04 0 32 64 96 -0.08 128 0 32 +125°C 100 WIPER RESISTANCE () WIPER RESISTANCE () +25°C 80 60 40 -40°C 20 +125°C +25°C 80 60 -40°C 40 20 0 32 64 96 TAP POSITION (DECIMAL) 0 128 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 200 40 150 30 TCv (ppm/°C) TCv (ppm/°C) 128 120 100 100 20 10 50 0 96 FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C 0 64 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) 15 43 71 99 TAP POSITION (DECIMAL) FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V 11 127 0 15 43 71 99 127 TAP POSITION (DECIMAL) FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V FN7904.0 August 25, 2011 ISL23428 Typical Performance Curves (Continued) 120 500 90 TCr (ppm/°C) TCr (ppm/°C) 400 300 200 30 100 0 60 15 43 71 99 0 127 15 43 TAP POSITION (DECIMAL) 20 120 15 90 10 5 0 127 FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V TCr (ppm/°C) TCv (ppm/°C) FIGURE 15. 10kΩ TCr vs TAP POSITION 71 99 TAP POSITION (DECIMAL) 60 30 15 43 71 99 TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V SCK CLOCK 127 0 15 43 71 99 TAP POSITION (DECIMAL) 127 FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V WIPER CS RISING RW PIN CH1: 20mV/DIV, 2µs/DIV CH2: 2V/DIV, 2µs/DIV CH1: 1V/DIV, 1µs/DIV CH2: 10mV/DIV, 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH 12 FIGURE 20. WIPER TRANSITION GLITCH FN7904.0 August 25, 2011 ISL23428 Typical Performance Curves (Continued) 1V/DIV 0.2µs/DIV 0.5V/DIV 20µs/DIV VCC CS RISING WIPER WIPER FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE CH1: RH TERMINAL CH2: RW TERMINAL 1.8 STANDBY CURRENT ICC (µA) 1.6 1.4 1.2 1.0 VCC = 5.5V, VLOGIC = 5.5V 0.8 0.6 VCC = 1.7V, VLOGIC = 1.2V 0.4 0.2 0 -40 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP -15 10 35 60 85 110 TEMPERATURE (°C) FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions Potentiometers Pins Power Pins RHI AND RLI VCC The high (RHi, i = 0, 1) and low (RLi, i = 0, 1) terminals of the ISL23428 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. Power terminal for the potentiometer section analog power source. Can be any value needed to support voltage range of DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. RWI This input is the serial clock of the SPI serial interface. RWi (i = 0, 1) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. 13 Bus Interface Pins SERIAL CLOCK (SCK) SERIAL DATA INPUT (SDI) The SDI is a serial data input pin for SPI interface. It receives operation code, wiper address and data from the SPI remote host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. FN7904.0 August 25, 2011 ISL23428 SERIAL DATA OUTPUT (SDO) The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. The output type is configured through ACR[1] bit for Push-Pull or Open Drain operation. Default setting for this pin is Push-Pull. An external pull-up resistor is required for Open Drain output operation. When CS is HIGH, the SDO pin is in tri-state (Z) or high-tri-state (Hi-Z) depends on the selected configuration. CHIP SELECT (CS) CS LOW enables the ISL23428, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power-up. When CS is HIGH, the ISL23428 is deselected and the SDO pin is at high impedance, and the device will be in the standby state. VLOGIC Digital power source for the logic control section. It supplies an internal level translator for 1.2V to 5.5V serial bus operation. Use the same supply as the I2C logic source. Principles of Operation The ISL23428 is an integrated circuit incorporating two DCPs with its associated registers and an SPI serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the SPI logic source which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has lower levels than DCP analog supply. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WR of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RWi) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = 7Fh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At 14 the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL23428 is being powered up, both WRi are reset to 40h (64 decimal), which positions RWi at the center between RLi and RHi. The WRi can be read or written to directly using the SPI serial interface, as described in the following sections. Memory Description The ISL23428 contains three volatile 8-bit registers: Wiper Register WR0, Wiper Register WR1, and Access Control Register (ACR). Memory map of ISL23428 is shown in Table 1. The Wiper Register WR0 at address 0 contains current wiper position of DCP0; the Wiper Register WR1 at address 1 contains current wiper position of DCP1. The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. TABLE 1. MEMORY MAP ADDRESS (hex) VOLATILE REGISTER NAME DEFAULT SETTING (hex) 10 ACR 40 1 WR1 40 0 WR0 40 TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 NAME/ VALUE 0 SHDN 0 0 0 0 SDO 0 The SDO bit (ACR[1]) configures type of SDO output pin. The default value of SDO bit is 0 for Push-Pull output. The SDO pin can be configured as Open Drain output for some applications. In this case, an external pull-up resistor is required; reference the “Serial Interface Specification” on page 7. Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e., each DCP is forced to end-to-end open circuit and each RW shorted to RL through a 2kΩ serial resistor, as shown in Figure 25. Default value of the SHDN bit is 1. RH RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE FN7904.0 August 25, 2011 ISL23428 WIPER VOLTAGE, VRW (V) When the device enters shutdown, all current DCP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). POWER-UP SHDN ACTIVATED Protocol Conventions AFTER SHDN SHDN RELEASED WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 The ISL23428 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL23428. The SCK and CS lines are controlled by the host or master. The ISL23428 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. MID SCALE = 40H USER PROGRAMMED SPI Serial Interface The SPI protocol contains Instruction Byte followed by one or more Data Bytes. A valid Instruction Byte contains instruction as the three MSBs, with the following five register address bits (see Table 3). The next byte sent to the ISL23428 is the Data Byte. TIME (s) TABLE 3. INSTRUCTION BYTE FORMAT FIGURE 26. SHUTDOWN MODE WIPER RESPONSE BIT # 7 6 5 4 3 2 1 0 I2 I1 I0 R4 R3 R2 R1 R0 Table 4 contains a valid instruction set for ISL23428. If the [R4:R0] bits are zero or one, then the read or write is to the WRi register. If the [R4:R0] are 10000, then the operation is to the ACR. TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 I1 I0 R4 R3 R2 R1 R0 OPERATION 0 0 0 X X X X X NOP 0 0 1 X X X X X ACR READ 0 1 1 X X X X X ACR WRTE 1 0 0 R4 R3 R2 R1 R0 WRi or ACR READ 1 1 0 R4 R3 R2 R1 R0 WRi or ACR WRTE Where X means “do not care”. 15 FN7904.0 August 25, 2011 ISL23428 CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK WR INSTRUCTION SDI DATA BYTE ADDR SDO FIGURE 27. TWO BYTE WRITE SEQUENCE CS 1 8 16 24 32 SCK SDI RD NOP ADDR RD SDO ADDR READ DATA FIGURE 28. FOUR BYTE READ SEQUENCE Write Operation Read Operation A write operation to the ISL23428 is a two or more bytes operation. First, It requires the CS transition from HIGH-to-LOW. Then the host sends a valid Instruction Byte, followed by one or more Data Bytes to the SDI pin. The host terminates the write operation by pulling the CS pin from LOW-to-HIGH. Instruction is executed on the rising edge of CS (see Figure 27). A Read operation to the ISL23428 is a four byte operation. First, It requires the CS transition from HIGH-to-LOW. Then the host sends a valid Instruction Byte, followed by a “dummy” Data Byte, NOP Instruction Byte and another “dummy” Data Byte to SDI pin. The SPI host receives the Instruction Byte (instruction code + register address) and requested Data Byte from SDO pin on the rising edge of SCK during third and fourth bytes, respectively. The host terminates the read by pulling the CS pin from LOW-to-HIGH (see Figure 28). 16 FN7904.0 August 25, 2011 ISL23428 Applications Information The first part starts by HIGH-to-LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW-to-HIGH transition on CS line. The read instructions are executed during the second part of read sequence. It also starts by HIGH-to-LOW transition on CS line, followed by N number of two bytes NOP instructions on SDI line and LOW-to-HIGH transition of CS. The data is read on every even byte during the second part of the read sequence while every odd byte contains code 111b followed by address from which the data is being read. Communicating with ISL23428 Communication with ISL23428 proceeds using SPI interface through the ACR (address 10000b), WR0 (addresses 00000b) and WR1 (addresses 00001b) registers. The wiper of the potentiometer is controlled by the WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position. Daisy Chain Configuration Wiper Transition When an application needs more than one ISL23428, it can communicate with all of them without additional CS lines by daisy chaining the DCPs as shown in Figure 29. In Daisy Chain configuration, the SDO pin of the previous chip is connected to the SDI pin of the following chip, and each CS and SCK pins are connected to the corresponding microcontroller pins in parallel, like regular SPI interface implementation. The Daisy Chain configuration can also be used for simultaneous setting of multiple DCPs. Note, the number of daisy chained DCPs is limited only by the driving capabilities of the SCK and CS pins of the microcontroller; for larger number of SPI devices, buffering of SCK and CS lines is required. When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (<1µs). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., 6Fh to 7Fh, which have higher transient glitch. Note that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus this may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. Daisy Chain Write Operation The write operation starts by HIGH-to-LOW transition on CS line, followed by N number of two bytes write instructions on SDI line with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown in Figure 30, where N is a number of DCPs in chain. The serial data is going through DCPs from DCP0 to DCP(N-1) as follows: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously. VLOGIC Requirements It is recommended to keep VLOGIC powered all the time during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23428. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VLOGIC pin. Daisy Chain Read Operation The read operation consists of two parts: first, send the read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation) as shown in Figures 31 and 32. VCC Requirements and Placement It is recommended to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VCC pin. N DCP IN A CHAIN CS SCK DCP0 MOSI MISO µC DCP1 DCP2 CS CS CS SCK SCK SCK SDI SDO SDI SDO SDI DCP(N-1) CS SCK SDO SDI SDO FIGURE 29. DAISY CHAIN CONFIGURATION 17 FN7904.0 August 25, 2011 ISL23428 CS SCK 16 CLKLS WR SDI 16 CLKS 16 CLKS D C P2 SDO 0 WR D C P1 WR D C P0 WR D C P2 WR D C P1 WR D C P2 SDO 1 SDO 2 FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR DATA IN SDO DATA OUT FIGURE 31. TWO BYTE READ INSTRUCTION CS SCK 16 CLKS SDI RD DCP2 16 CLKS RD DCP1 SDO 16 CLKS 16 CLKS 16 CLKS 16 CLKS RD DCP0 NOP NOP NOP DCP2 OUT DCP1 OUT DCP0 OUT FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP 18 FN7904.0 August 25, 2011 ISL23428 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 8/25/11 FN7904.0 CHANGE Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL23428 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN7904.0 August 25, 2011 ISL23428 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN 20 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. FN7904.0 August 25, 2011 ISL23428 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D L16.2.6x1.8A B 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 6 INDEX AREA 2X A N SYMBOL E 0.10 C 1 2 2X 0.10 C MIN 0.10 C C A 0.05 C A1 SIDE VIEW e PIN #1 ID K 1 2 NX L L1 0.45 0.50 0.55 - - - 0.05 - 0.127 REF (DATUM B) (DATUM A) BOTTOM VIEW - b 0.15 0.20 0.25 5 D 2.55 2.60 2.65 - E 1.75 1.80 1.85 - 0.40 BSC - K 0.15 - - - L 0.35 0.40 0.45 - L1 0.45 0.50 0.55 - N 16 2 Nd 4 3 Ne 4 3 NX b 5 16X 0.10 M C A B 0.05 M C NOTES A e SEATING PLANE MAX A1 A3 TOP VIEW NOMINAL 0 - 12 4 Rev. 5 2/09 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. CL (A1) NX (b) L 5 e SECTION "C-C" 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. TERMINAL TIP C C 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 3.00 1.80 1.40 1.40 2.20 0.90 0.40 0.20 0.50 0.20 0.40 10 LAND PATTERN 21 FN7904.0 August 25, 2011